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... just like has been made the case recently for movzb and movzw.
Note that this exposed a bug in check_qword_reg(): A missing 'r' (or
wrong 'e') register prefix needs to be complained about if the template
allows for a 64-bit register, not a 32-bit one. I assume this was a
copy-and-paste type of mistake (from check_long_reg()).
gas/
2016-07-01 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (check_qword_reg): Correct register kind
checked.
* testsuite/gas/i386/movs.s: New.
* testsuite/gas/i386/movs32.d: New.
* testsuite/gas/i386/movs64.d: New.
* testsuite/gas/i386/i386.exp: Run new tests.
opcodes/
2016-07-01 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (movsbl, movsbw, movsbq, movswl, movswq,
movslq): Remove.
(movsb, movzw, movsl): New (one sign-extending and two string
instances each).
(movsd): Move string variant next to other string insns.
* i386-tbl.h: Re-generate.
--- 2016-07-01/gas/config/tc-i386.c
+++ 2016-07-01/gas/config/tc-i386.c
@@ -5670,7 +5670,7 @@ check_qword_reg (void)
/* Warn if the r prefix on a general reg is missing. */
else if ((i.types[op].bitfield.reg16
|| i.types[op].bitfield.reg32)
- && (i.tm.operand_types[op].bitfield.reg32
+ && (i.tm.operand_types[op].bitfield.reg64
|| i.tm.operand_types[op].bitfield.acc))
{
/* Prohibit these changes in the 64bit mode, since the
--- 2016-07-01/gas/testsuite/gas/i386/i386.exp
+++ 2016-07-01/gas/testsuite/gas/i386/i386.exp
@@ -59,6 +59,7 @@ if [expr ([istarget "i*86-*-*"] || [ist
run_dump_test "amd"
run_dump_test "katmai"
run_dump_test "jump"
+ run_dump_test "movs32"
run_dump_test "movz32"
run_dump_test "relax-1"
run_dump_test "relax-2"
@@ -510,6 +511,7 @@ if [expr ([istarget "i*86-*-*"] || [ista
run_dump_test "x86-64-segovr"
run_list_test "x86-64-inval-seg" "-al"
run_dump_test "x86-64-branch"
+ run_dump_test "movs64"
run_dump_test "movz64"
run_dump_test "x86-64-relax-1"
run_dump_test "svme64"
--- 2016-07-01/gas/testsuite/gas/i386/movs.s
+++ 2016-07-01/gas/testsuite/gas/i386/movs.s
@@ -0,0 +1,41 @@
+ .text
+movs:
+ movsb
+ movsb %al,%ax
+ movsb (%eax),%ax
+ movsb %al,%eax
+ movsb (%eax),%eax
+.ifdef x86_64
+ movsb %al,%rax
+ movsb (%rax),%rax
+.endif
+
+ movsbw %al,%ax
+ movsbw (%eax),%ax
+ movsbl %al,%eax
+ movsbl (%eax),%eax
+.ifdef x86_64
+ movsbq %al,%rax
+ movsbq (%rax),%rax
+.endif
+
+ movsw
+ movsw %ax,%eax
+ movsw (%eax),%eax
+.ifdef x86_64
+ movsw %ax,%rax
+ movsw (%rax),%rax
+.endif
+
+ movswl %ax,%eax
+ movswl (%eax),%eax
+.ifdef x86_64
+ movswq %ax,%rax
+ movswq (%rax),%rax
+
+ movsl
+ movsl %eax,%rax
+ movsl (%rax),%rax
+ movslq %eax,%rax
+ movslq (%rax),%rax
+.endif
--- 2016-07-01/gas/testsuite/gas/i386/movs32.d
+++ 2016-07-01/gas/testsuite/gas/i386/movs32.d
@@ -0,0 +1,24 @@
+#objdump: -dw
+#source: movs.s
+#name: x86 mov with sign-extend (32-bit object)
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <movs>:
+[ ]*[a-f0-9]+: a4 * movsb *((%ds:)?\(%esi\),%es:\(%edi\))?
+[ ]*[a-f0-9]+: 66 0f be c0 * movsbw %al,%ax
+[ ]*[a-f0-9]+: 66 0f be 00 * movsbw \(%eax\),%ax
+[ ]*[a-f0-9]+: 0f be c0 * movsbl %al,%eax
+[ ]*[a-f0-9]+: 0f be 00 * movsbl \(%eax\),%eax
+[ ]*[a-f0-9]+: 66 0f be c0 * movsbw %al,%ax
+[ ]*[a-f0-9]+: 66 0f be 00 * movsbw \(%eax\),%ax
+[ ]*[a-f0-9]+: 0f be c0 * movsbl %al,%eax
+[ ]*[a-f0-9]+: 0f be 00 * movsbl \(%eax\),%eax
+[ ]*[a-f0-9]+: 66 a5 * movsw *((%ds:)?\(%esi\),%es:\(%edi\))?
+[ ]*[a-f0-9]+: 0f bf c0 * movswl %ax,%eax
+[ ]*[a-f0-9]+: 0f bf 00 * movswl \(%eax\),%eax
+[ ]*[a-f0-9]+: 0f bf c0 * movswl %ax,%eax
+[ ]*[a-f0-9]+: 0f bf 00 * movswl \(%eax\),%eax
+#pass
--- 2016-07-01/gas/testsuite/gas/i386/movs64.d
+++ 2016-07-01/gas/testsuite/gas/i386/movs64.d
@@ -0,0 +1,37 @@
+#objdump: -dw
+#source: movs.s
+#name: x86 mov with sign-extend (64-bit object)
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+0+ <movs>:
+[ ]*[a-f0-9]+: a4 * movsb *((%ds:)?\(%rsi\),%es:\(%rdi\))?
+[ ]*[a-f0-9]+: 66 0f be c0 * movsbw %al,%ax
+[ ]*[a-f0-9]+: 67 66 0f be 00 * movsbw \(%eax\),%ax
+[ ]*[a-f0-9]+: 0f be c0 * movsbl %al,%eax
+[ ]*[a-f0-9]+: 67 0f be 00 * movsbl \(%eax\),%eax
+[ ]*[a-f0-9]+: 48 0f be c0 * movsbq %al,%rax
+[ ]*[a-f0-9]+: 48 0f be 00 * movsbq \(%rax\),%rax
+[ ]*[a-f0-9]+: 66 0f be c0 * movsbw %al,%ax
+[ ]*[a-f0-9]+: 67 66 0f be 00 * movsbw \(%eax\),%ax
+[ ]*[a-f0-9]+: 0f be c0 * movsbl %al,%eax
+[ ]*[a-f0-9]+: 67 0f be 00 * movsbl \(%eax\),%eax
+[ ]*[a-f0-9]+: 48 0f be c0 * movsbq %al,%rax
+[ ]*[a-f0-9]+: 48 0f be 00 * movsbq \(%rax\),%rax
+[ ]*[a-f0-9]+: 66 a5 * movsw *((%ds:)?\(%rsi\),%es:\(%rdi\))?
+[ ]*[a-f0-9]+: 0f bf c0 * movswl %ax,%eax
+[ ]*[a-f0-9]+: 67 0f bf 00 * movswl \(%eax\),%eax
+[ ]*[a-f0-9]+: 48 0f bf c0 * movswq %ax,%rax
+[ ]*[a-f0-9]+: 48 0f bf 00 * movswq \(%rax\),%rax
+[ ]*[a-f0-9]+: 0f bf c0 * movswl %ax,%eax
+[ ]*[a-f0-9]+: 67 0f bf 00 * movswl \(%eax\),%eax
+[ ]*[a-f0-9]+: 48 0f bf c0 * movswq %ax,%rax
+[ ]*[a-f0-9]+: 48 0f bf 00 * movswq \(%rax\),%rax
+[ ]*[a-f0-9]+: a5 * movsl *((%ds:)?\(%rsi\),%es:\(%rdi\))?
+[ ]*[a-f0-9]+: 48 63 c0 * movslq %eax,%rax
+[ ]*[a-f0-9]+: 48 63 00 * movslq \(%rax\),%rax
+[ ]*[a-f0-9]+: 48 63 c0 * movslq %eax,%rax
+[ ]*[a-f0-9]+: 48 63 00 * movslq \(%rax\),%rax
+#pass
--- 2016-07-01/opcodes/i386-opc.tbl
+++ 2016-07-01/opcodes/i386-opc.tbl
@@ -57,14 +57,9 @@ movbe, 2, 0x0f38f0, None, 3, CpuMovbe, M
movbe, 2, 0x0f38f1, None, 3, CpuMovbe, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64, Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
// Move with sign extend.
-// "movsbl" & "movsbw" must not be unified into "movsb" to avoid
-// conflict with the "movs" string move instruction.
-movsbl, 2, 0xfbe, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 }
-movsbw, 2, 0xfbe, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16 }
-movswl, 2, 0xfbf, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32 }
-movsbq, 2, 0xfbe, None, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp32|Disp32S, Reg64 }
-movswq, 2, 0xfbf, None, 2, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg16|Word|Unspecified|BaseIndex|Disp8|Disp32|Disp32S, Reg64 }
-movslq, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S, Reg64 }
+movsb, 2, 0xfbe, None, 2, Cpu386, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg8|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
+movsw, 2, 0xfbf, None, 2, Cpu386, Modrm|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg16|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 }
+movsl, 2, 0x63, None, 1, Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S, Reg64 }
// Intel Syntax next 3 insns
movsx, 2, 0xfbe, None, 2, Cpu386, Modrm|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg8|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
movsx, 2, 0xfbf, None, 2, Cpu386, Modrm|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Reg16|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 }
@@ -451,6 +446,17 @@ slod, 1, 0xac, None, 1, 0, W|No_sSuf|No_
slod, 2, 0xac, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Acc|Byte|Word|Dword|Qword }
movs, 0, 0xa4, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { 0 }
movs, 2, 0xa4, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg }
+// These entries with suffixes explicitly specified cannot be removed to
+// avoid conflicts with the "movs{b,w,l}" sign-extend move instructions.
+movsb, 0, 0xa4, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { 0 }
+movsb, 2, 0xa4, None, 1, 0, No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Unspecified|BaseIndex, Byte|Unspecified|BaseIndex|EsSeg }
+movsw, 0, 0xa5, None, 1, 0, Size16|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { 0 }
+movsw, 2, 0xa5, None, 1, 0, Size16|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Word|Unspecified|BaseIndex, Word|Unspecified|BaseIndex|EsSeg }
+movsl, 0, 0xa5, None, 1, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { 0 }
+movsl, 2, 0xa5, None, 1, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Dword|Unspecified|BaseIndex, Dword|Unspecified|BaseIndex|EsSeg }
+// Intel variant, avoiding conflict with the scalar double move instruction.
+movsd, 0, 0xa5, None, 1, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, { 0 }
+movsd, 2, 0xa5, None, 1, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, { Unspecified|BaseIndex, Unspecified|BaseIndex|EsSeg }
smov, 0, 0xa4, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { 0 }
smov, 2, 0xa4, None, 1, 0, W|CheckRegSize|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Byte|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg }
scas, 0, 0xae, None, 1, 0, W|No_sSuf|No_ldSuf|IsString|RepPrefixOk, { 0 }
@@ -1404,9 +1410,6 @@ movmskpd, 2, 0x6650, None, 1, CpuAVX, Mo
movmskpd, 2, 0x660f50, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { RegXMM, Reg32|Reg64 }
movntpd, 2, 0x662b, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
movntpd, 2, 0x660f2b, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-// Intel mode string move.
-movsd, 0, 0xa5, None, 1, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, { 0 }
-movsd, 2, 0xa5, None, 1, 0, Size32|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsString|RepPrefixOk, { Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|EsSeg }
movsd, 2, 0xf211, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
movsd, 2, 0xf210, None, 1, CpuAVX, Modrm|Vex=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM }
movsd, 2, 0xf210, None, 1, CpuAVX, S|Modrm|Vex=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM }
Attachment:
binutils-master-x86-movs.patch
Description: Text document
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