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[PATCH 0/4] opcodes/bfd SPARC arches revamp and GAS fixes

Hi folks!  Time for some sparc binutils improvements :)

The sparc code in GAS knows about a set of different architectures,
that roughly speaking correspond to the several revisions of the sparc
specification and processor-specific extensions.  Currently these are:

 v6   : V6 specification.
 v7   : V7 specification.
 v8   : V8 specification.
 leon : V7 with leon additions.
 v9  : V9 specification.
 v9a : V9 with ultrasparc additions.
 v9b : V9 with cheetah additions.
 v9c : V9 with UA2005 and T1 additions.
 v9d : V9 with UA2007 and T3 additions.
 v9e : V9 with OSA2011 and T4 additions minus integer multiply-add.
 v9v : V9 V9 with OSA2011 and T4 additions, integer multiply and
       Fujitsu's floating-poing multiply-add instructions.
 v9m : V9 with OSA0215 and M7 additions.

However, starting with v9a these gas "arches" don't correspond with
opcodes arches:

 | opcodes arch | GAS arch                     |
 | v6           | v6                           |
 | v7           | v7                           |
 | v8           | v8                           |
 | leon         | leon                         |
 | sparclet     | sparclet                     |
 | sparclite    | sparclite                    |
 | v9           | v9                           |
 | v9a          | v9a                          |
 | v9b          | v9b, v9c, v9d, v9e, v9v, v9m |

This means that all the instructions introduced by v9{c,d,e,v,m} are
annotated in opcodes/sparc-opc.c as being part of the v9b
architecture.  This approach has the following disadvantages:

(a) The assembler relies on the opcodes arches in order to detect
    whether a new instruction has a dependency on a higher
    architecture, and react accordingly, either emitting an error or
    bumping the current architecture.  Thus, code like:

       addxc %g1,%g2,%g3

    Will be assembled even if the user specifies -Av9b when invoking
    GAS.  If for example -Av9a is specified, an incorrect message is

       Error: Architecture mismatch on "addxc".
       (Requires v9b; requested architecture is v9a.)

    But the addxc instruction was introduced in UA2007, i.e. v9d.

    The architecture handling (bumping, rejection of not supported
    instructions, etc) in the assembler is basically useless in sparc
    objects after v9b (UltraSPARC III).

(b) Since opcodes lacks any nothion of the sparc arches after v9b, the
    assembler needs to use ad-hoc tests in order to reject accesses to
    registers (and other stuff) introduced in some later architecture.
    An example of such checks is this snippet from

       if (p->regnum >= 24
           && (insn->architecture
          /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */
          error_message = _(": unrecognizable v9a ancillary state register");
          goto error;

    Extending these checks to all the ancillary state registers
    introduced in any of the v9{c,d,e,v,m} (and combinations of
    arches) would be cumbersome and error-prone.

(c) The disassembler supports to specify the machine type along with
    the architecture using the -m command line option.  In sparc this
    won't work after v9b, as opcodes lack's these arches:

       $ objdump -d -m sparc:v9m
       objdump: Can't use supplied machine sparc:v9m

(d) For sparc architectures up to v9b the object files are annotated
    so BFD is able to recognize the sparc machine number when reading
    the object back.  This allows the disassembler to adapt its output
    accordingly, for example emitting "unkonwn" instructions for
    instructions not existing in this architecture level.  However,
    currently this doesn't work for architectures v9{c,d,e,m,v}.

This patch serie addresses all the problems above by introducing
proper opcodes arches for all the sparc models after v9b and adapting
the assembler and disassembler accordingly.  See the descriptions in
the individual patches.



Jose E. Marchesi (4):
  bfd,opcodes: sparc: new opcode v9{c,d,e,v,m} architectures and bfd
    machine numbers.
  gas: sparc: fix collision of registers and pseudo-ops.
  opcodes,gas: adjust sparc insns and make GAS aware of it
  opcodes,gas: sparc: fix rdasr,wrasr,rdpr,wrpr,rdhpr,wrhpr insns.

 bfd/ChangeLog                      |  22 ++
 bfd/aoutx.h                        |  12 +-
 bfd/archures.c                     |  20 +-
 bfd/bfd-in2.h                      |  20 +-
 bfd/cpu-sparc.c                    | 150 ++++++++++
 bfd/elf32-sparc.c                  |   5 +
 bfd/elfxx-sparc.c                  |  57 +++-
 gas/ChangeLog                      |  62 +++++
 gas/config/tc-sparc.c              | 472 +++++++++++++++++++------------
 gas/testsuite/gas/sparc/ldx_efsr.d |   4 +-
 gas/testsuite/gas/sparc/mism-1.s   |   7 +
 gas/testsuite/gas/sparc/mism-2.s   |  23 ++
 gas/testsuite/gas/sparc/mwait.d    |   7 +-
 gas/testsuite/gas/sparc/mwait.s    |   1 -
 gas/testsuite/gas/sparc/rdasr.d    |  18 ++
 gas/testsuite/gas/sparc/rdasr.s    |  11 +
 gas/testsuite/gas/sparc/rdhpr.d    |   5 +-
 gas/testsuite/gas/sparc/rdhpr.s    |   3 +
 gas/testsuite/gas/sparc/rdpr.d     |   2 +-
 gas/testsuite/gas/sparc/sparc.exp  |   2 +
 gas/testsuite/gas/sparc/wrasr.d    |  48 ++++
 gas/testsuite/gas/sparc/wrasr.s    |  41 +++
 gas/testsuite/gas/sparc/wrhpr.d    |  59 +++-
 gas/testsuite/gas/sparc/wrhpr.s    |  57 +++-
 gas/testsuite/gas/sparc/wrpr.d     | 114 ++++++--
 gas/testsuite/gas/sparc/wrpr.s     | 110 ++++++--
 include/ChangeLog                  |   7 +
 include/opcode/sparc.h             |   6 +
 opcodes/ChangeLog                  |  46 +++
 opcodes/sparc-dis.c                |  30 +-
 opcodes/sparc-opc.c                | 556 ++++++++++++++++++++++---------------
 31 files changed, 1504 insertions(+), 473 deletions(-)
 create mode 100644 gas/testsuite/gas/sparc/mism-2.s
 create mode 100644 gas/testsuite/gas/sparc/rdasr.d
 create mode 100644 gas/testsuite/gas/sparc/rdasr.s
 create mode 100644 gas/testsuite/gas/sparc/wrasr.d
 create mode 100644 gas/testsuite/gas/sparc/wrasr.s


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