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Re: [PATCH] [ARC] Add missing variants of rflt instruction

Hi Nick,

On 01/06/16 17:35, Nick Clifton wrote:
Also - just out of curiosity - do you happen to know why these versions
of the rflt instruction were not implemented ?  I am just wondering if
there was a good reason for the omission, or if it was just an accident,
or if this the tip of an unimplemented instruction iceberg...

Just a short note to your question for clarification purposes. Most of the ARC processor instructions (and in particular the extensions ones like the one in question) uses a very well defined syntax. For 3-operation instructions, this is:

OP<.f>      Ra,Rb,Rc
OP<.f>      0, Rb,Rc
OP<.f><.cc> Rb,Rb,Rc
OP<.f>      Ra,Rb,u6
OP<.f>      0, Rb,u6
OP<.f><.cc> Rb,Rb,u6
OP<.f>      Rb,Rb,s12
OP<.f>      Ra,LIMM,Rc
OP<.f>      Ra,Rb,LIMM
OP<.f>      0, LIMM,Rc
OP<.f>      0, Rb,LIMM
OP<.f><.cc> Rb,Rb,LIMM
OP<.f><.cc> 0, LIMM,Rc
OP<.f>      Ra,LIMM,u6
OP<.f>      0, LIMM,u6
OP<.f><.cc> 0, LIMM,u6
OP<.f>      0, LIMM,s12
OP<.f>      Ra,LIMM,LIMM
OP<.f>      0, LIMM,LIMM

Now, it should be easy to generate tests for those instructions which fall in this category and check if the assembler generates all the variants as expected.

I do not try to answer your question, but to add information to the subject.


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