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Re: [PUSHED/OBV] opcodes/arc: Comment and whitespace fixes in opcode table
- From: Claudiu Zissulescu <claziss at gmail dot com>
- To: Andrew Burgess <andrew dot burgess at embecosm dot com>
- Cc: Binutils <binutils at sourceware dot org>
- Date: Thu, 31 Mar 2016 15:38:19 +0200
- Subject: Re: [PUSHED/OBV] opcodes/arc: Comment and whitespace fixes in opcode table
- Authentication-results: sourceware.org; auth=none
- References: <1459358269-10771-1-git-send-email-andrew dot burgess at embecosm dot com>
Ok by me.
//Claudiu
On Wed, Mar 30, 2016 at 7:17 PM, Andrew Burgess
<andrew.burgess@embecosm.com> wrote:
> Add a new comment, and clean up some whitespace issues in the
> instruction table.
>
> opcode/ChangeLog:
>
> * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
> issues. No functional changes.
> ---
> opcodes/ChangeLog | 5 +++++
> opcodes/arc-nps400-tbl.h | 14 ++++++++------
> 2 files changed, 13 insertions(+), 6 deletions(-)
>
> diff --git a/opcodes/arc-nps400-tbl.h b/opcodes/arc-nps400-tbl.h
> index 4b715f9..493c5b6 100644
> --- a/opcodes/arc-nps400-tbl.h
> +++ b/opcodes/arc-nps400-tbl.h
> @@ -1,11 +1,13 @@
> +/**** Bit Manipulation Instructions ****/
> +
> /* movl<.cl> */
> -{ "movh", 0x48080000, 0xf81f0000, ARC_OPCODE_NPS400 , BITOP, NONE, { NPS_R_DST, NPS_R_SRC1, NPS_UIMM16 }, { 0 }},
> -{ "movh", 0x48180000, 0xf81f0000, ARC_OPCODE_NPS400 , BITOP, NONE, { NPS_R_DST, NPS_UIMM16 }, { C_NPS_CL }},
> +{ "movh", 0x48080000, 0xf81f0000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST, NPS_R_SRC1, NPS_UIMM16 }, { 0 }},
> +{ "movh", 0x48180000, 0xf81f0000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST, NPS_UIMM16 }, { C_NPS_CL }},
>
> /* movl<.cl> */
> -{ "movl", 0x48090000, 0xf81f0000, ARC_OPCODE_NPS400 , BITOP, NONE, { NPS_R_DST, NPS_R_SRC1, NPS_UIMM16 }, { 0 }},
> -{ "movl", 0x48190000, 0xf81f0000, ARC_OPCODE_NPS400 , BITOP, NONE, { NPS_R_DST, NPS_UIMM16 }, { C_NPS_CL }},
> +{ "movl", 0x48090000, 0xf81f0000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST, NPS_R_SRC1, NPS_UIMM16 }, { 0 }},
> +{ "movl", 0x48190000, 0xf81f0000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST, NPS_UIMM16 }, { C_NPS_CL }},
>
> /* movb<.f><.cl> */
> -{ "movb", 0x48010000, 0xf80f8000, ARC_OPCODE_NPS400 , BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }},
> -{ "movb", 0x48018000, 0xf80f8000, ARC_OPCODE_NPS400 , BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F, C_NPS_CL }},
> +{ "movb", 0x48010000, 0xf80f8000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }},
> +{ "movb", 0x48018000, 0xf80f8000, ARC_OPCODE_NPS400, BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F, C_NPS_CL }},
> --
> 2.6.4
>