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[PATCHv2 2/2] gas/opcodes: Add initial arc nps400 support


The ARC NPS400 is an ARC700 with some additional instructions, created
by Mellanox (formally EZchip).  This commit adds initial support for the
ARC NPS400 variant.

At this stage I have added only one new instruction, movb, this is to
allow a discussion of the correct approach for adding additional
instructions to the arc target.  Additional instructions, and supporting
relocations will be added in future commits.

When binutils is configured for NPS400, by specifying 'mellanox' as the
vendor name in the target tuple, then the additional NPS400 instructions
are added into the ARC700 instruction set (within the opcodes library),
and in the assembler, the default architecture is changed to be ARC700.

There's a test for the new instruction, a test for the default
architecture, and one test needs updating slightly.

gas/ChangeLog:

	* testsuite/gas/arc/nps400-0.d: New file.
	* testsuite/gas/arc/nps400-0.s: New file.
	* testsuite/gas/arc/nps400-1.d: New file.
	* testsuite/gas/arc/nps400-1.s: New file.

opcodes/ChangeLog:

	* arc-nps400-tbl.h: New file.
	* arc-opc.c: Add top level comment.
	(insert_nps_dst): New function.
	(extract_nps_dst): New function.
	(extract_nps_dst_cl_z): New function.
	(extract_nps_src1_in_dst): New function.
	(insert_nps_src2): New function.
	(extract_nps_src2): New function.
	(insert_nps_bitop_size): New function.
	(extract_nps_bitop_size): New function.
	(arc_flag_operands): Add nps400 entries.
	(arc_flag_classes): Add nps400 entries.
	(arc_operands): Add nps400 entries.
	(arc_opcodes): Add nps400 entries.
	* config.in: Regenerate.
	* configure: Regenerate.
	* configure.ac: Setup extension instruction file for arc nps400.
---
 gas/ChangeLog                    |   7 ++
 gas/testsuite/gas/arc/nps400-0.d |  16 ++++
 gas/testsuite/gas/arc/nps400-0.s |   2 +
 gas/testsuite/gas/arc/nps400-1.d |  15 ++++
 gas/testsuite/gas/arc/nps400-1.s |   7 ++
 opcodes/ChangeLog                |  20 +++++
 opcodes/arc-nps400-tbl.h         |   3 +
 opcodes/arc-opc.c                | 177 +++++++++++++++++++++++++++++++++++++++
 opcodes/config.in                |   3 +
 opcodes/configure                |   8 ++
 opcodes/configure.ac             |   6 ++
 11 files changed, 264 insertions(+)
 create mode 100644 gas/testsuite/gas/arc/nps400-0.d
 create mode 100644 gas/testsuite/gas/arc/nps400-0.s
 create mode 100644 gas/testsuite/gas/arc/nps400-1.d
 create mode 100644 gas/testsuite/gas/arc/nps400-1.s
 create mode 100644 opcodes/arc-nps400-tbl.h

diff --git a/gas/ChangeLog b/gas/ChangeLog
index d9975a6..dddb06f 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2016-02-25  Andrew Burgess  <andrew.burgess@embecosm.com>
+
+	* testsuite/gas/arc/nps400-0.d: New file.
+	* testsuite/gas/arc/nps400-0.s: New file.
+	* testsuite/gas/arc/nps400-1.d: New file.
+	* testsuite/gas/arc/nps400-1.s: New file.
+
 2016-03-01  Andrew Burgess  <andrew.burgess@embecosm.com>
 
 	* config/tc-arc.c (arc_target): Delay initialisation until
diff --git a/gas/testsuite/gas/arc/nps400-0.d b/gas/testsuite/gas/arc/nps400-0.d
new file mode 100644
index 0000000..09e62b3
--- /dev/null
+++ b/gas/testsuite/gas/arc/nps400-0.d
@@ -0,0 +1,16 @@
+#as:
+#target: arc*-mellanox-*
+#readelf: -h
+
+#...
+  Class:                             ELF32
+  Data:                              2's complement, .* endian
+  Version:                           1 \(current\)
+  OS/ABI:                            UNIX - System V
+  ABI Version:                       0
+  Type:                              REL \(Relocatable file\)
+  Machine:                           ARCompact
+  Version:                           0x1
+#...
+  Flags:                             0x303, ARC 700, v3 no-legacy-syscalls ABI
+#...
\ No newline at end of file
diff --git a/gas/testsuite/gas/arc/nps400-0.s b/gas/testsuite/gas/arc/nps400-0.s
new file mode 100644
index 0000000..2b6cc1d
--- /dev/null
+++ b/gas/testsuite/gas/arc/nps400-0.s
@@ -0,0 +1,2 @@
+        .text
+        nop
diff --git a/gas/testsuite/gas/arc/nps400-1.d b/gas/testsuite/gas/arc/nps400-1.d
new file mode 100644
index 0000000..bd68eb0
--- /dev/null
+++ b/gas/testsuite/gas/arc/nps400-1.d
@@ -0,0 +1,15 @@
+#as: -mcpu=arc700
+#target: arc*-mellanox-*
+#objdump: -dr
+
+.*: +file format .*arc.*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <.*>:
+   0:	4821 1485           	movb	r0,r0,r1,0x4,0x5,0x6
+   4:	4881 1485           	movb	r0,r0,r12,0x4,0x5,0x6
+   8:	4f81 1485           	movb	r15,r15,r12,0x4,0x5,0x6
+   c:	4821 9485           	movb.cl	r0,r1,0x4,0x5,0x6
+  10:	48c1 9485           	movb.cl	r0,r14,0x4,0x5,0x6
+  14:	4d21 9485           	movb.cl	r13,r1,0x4,0x5,0x6
diff --git a/gas/testsuite/gas/arc/nps400-1.s b/gas/testsuite/gas/arc/nps400-1.s
new file mode 100644
index 0000000..1d340b3
--- /dev/null
+++ b/gas/testsuite/gas/arc/nps400-1.s
@@ -0,0 +1,7 @@
+        .text
+        movb		r0, r0, r1, 4, 5, 6
+        movb		r0, r0, r12, 4, 5, 6
+        movb		r15, r15, r12, 4, 5, 6
+        movb.cl		r0, r1, 4, 5, 6
+        movb.cl		r0, r14, 4, 5, 6
+        movb.cl		r13, r1, 4, 5, 6
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index eb2b61c..24b2940 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,23 @@
+2016-02-25  Andrew Burgess  <andrew.burgess@embecosm.com>
+
+	* arc-nps400-tbl.h: New file.
+	* arc-opc.c: Add top level comment.
+	(insert_nps_dst): New function.
+	(extract_nps_dst): New function.
+	(extract_nps_dst_cl_z): New function.
+	(extract_nps_src1_in_dst): New function.
+	(insert_nps_src2): New function.
+	(extract_nps_src2): New function.
+	(insert_nps_bitop_size): New function.
+	(extract_nps_bitop_size): New function.
+	(arc_flag_operands): Add nps400 entries.
+	(arc_flag_classes): Add nps400 entries.
+	(arc_operands): Add nps400 entries.
+	(arc_opcodes): Add nps400 entries.
+	* config.in: Regenerate.
+	* configure: Regenerate.
+	* configure.ac: Setup extension instruction file for arc nps400.
+
 2016-03-01  Andrew Burgess  <andrew.burgess@embecosm.com>
 
 	* arc-opc.c (BASE): Delete.
diff --git a/opcodes/arc-nps400-tbl.h b/opcodes/arc-nps400-tbl.h
new file mode 100644
index 0000000..8347e68
--- /dev/null
+++ b/opcodes/arc-nps400-tbl.h
@@ -0,0 +1,3 @@
+/* movb<.f><.cl> */
+{ "movb", 0x48010000, 0xf80f0000, ARC_OPCODE_ARC700 , ARITH, NONE, { NPS_R_DST, NPS_R_SRC1_IN_DST, NPS_R_SRC2, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }},
+{ "movb", 0x48010000, 0xf80f0000, ARC_OPCODE_ARC700 , ARITH, NONE, { NPS_R_DST_CL_Z, NPS_R_SRC2, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F, C_NPS_CL }},
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index a4fdaff..a745fc1 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -26,6 +26,12 @@
 #include "opintl.h"
 #include "libiberty.h"
 
+/* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom
+   instructions.  Support for this target is available when binutils is
+   configured and built for the 'arc*-mellanox-*-*' target.  As far as
+   possible all ARC NPS400 features are built into all ARC target builds as
+   this reduces the chances that regressions might creep in.  */
+
 /* Insert RB register into a 32-bit opcode.  */
 static unsigned
 insert_rb (unsigned insn,
@@ -637,6 +643,136 @@ extract_g_s (unsigned insn ATTRIBUTE_UNUSED,
   return value;
 }
 
+/* ARC NPS400 Support: See comment near head of file.  */
+static unsigned
+insert_nps_dst (unsigned insn ATTRIBUTE_UNUSED,
+               int value ATTRIBUTE_UNUSED,
+               const char **errmsg ATTRIBUTE_UNUSED)
+{
+  switch (value)
+    {
+    case 0:
+    case 1:
+    case 2:
+    case 3:
+      insn |= value << 24;
+      break;
+    case 12:
+    case 13:
+    case 14:
+    case 15:
+      insn |= (value - 8) << 24;
+      break;
+    default:
+      *errmsg = _("Register must be either r0-r3 or r12-r15.");
+      break;
+    }
+  return insn;
+}
+
+static int
+extract_nps_dst (unsigned insn ATTRIBUTE_UNUSED,
+                bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  int value = (insn >> 24) & 0x07;
+  if (value > 3)
+    return (value + 8);
+  else
+    return value;
+}
+
+static int
+extract_nps_dst_cl_z (unsigned insn ATTRIBUTE_UNUSED,
+                      bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  int value;
+
+  /* If the CL flag is not set then this is invalid.  */
+  if (((insn >> 15) & 0x1) == 0)
+    *invalid = TRUE;
+  value = (insn >> 24) & 0x07;
+  if (value > 3)
+    return (value + 8);
+  else
+    return value;
+}
+
+static int
+extract_nps_src1_in_dst (unsigned insn ATTRIBUTE_UNUSED,
+                         bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  int value;
+
+  /* If the CL flag is set then this is invalid.  */
+  if (((insn >> 15) & 0x1) == 0x1)
+    *invalid = TRUE;
+  value = (insn >> 24) & 0x07;
+  if (value > 3)
+    return (value + 8);
+  else
+    return value;
+}
+
+static unsigned
+insert_nps_src2 (unsigned insn ATTRIBUTE_UNUSED,
+                int value ATTRIBUTE_UNUSED,
+                const char **errmsg ATTRIBUTE_UNUSED)
+{
+  switch (value)
+    {
+    case 0:
+    case 1:
+    case 2:
+    case 3:
+      insn |= value << 21;
+      break;
+    case 12:
+    case 13:
+    case 14:
+    case 15:
+      insn |= (value - 8) << 21;
+      break;
+    default:
+      *errmsg = _("Register must be either r0-r3 or r12-r15.");
+      break;
+    }
+  return insn;
+}
+
+static int
+extract_nps_src2 (unsigned insn ATTRIBUTE_UNUSED,
+                 bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  int value = (insn >> 21) & 0x07;
+  if (value > 3)
+    return (value + 8);
+  else
+    return value;
+}
+
+static unsigned
+insert_nps_bitop_size (unsigned insn ATTRIBUTE_UNUSED,
+                      int value ATTRIBUTE_UNUSED,
+                      const char **errmsg ATTRIBUTE_UNUSED)
+{
+  if (value < 1 || value > 32)
+    {
+      *errmsg = _("Invalid bit size, should be between 1 and 32 inclusive.");
+      return insn;
+    }
+
+  --value;
+  insn |= ((value & 0x1f) << 10);
+  return insn;
+}
+
+static int
+extract_nps_bitop_size (unsigned insn ATTRIBUTE_UNUSED,
+                       bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+  return ((insn >> 10) & 0x1f) + 1;
+}
+
 /* Include the generic extract/insert functions.  Order is important
    as some of the functions present in the .h may be disabled via
    defines.  */
@@ -792,6 +928,13 @@ const struct arc_flag_operand arc_flag_operands[] =
   /* Fake Flags.  */
 #define F_NE   (F_H17 + 1)
   { "ne", 0, 0, 0, 1 },
+
+  /* ARC NPS400 Support: See comment near head of file.  */
+#define F_NPS_CL (F_NE + 1)
+  { "cl", 1, 1, 15, 1 },
+
+#define F_NPS_FLAG (F_NPS_CL + 1)
+  { "f", 1, 1, 20, 1 },
 };
 
 const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands);
@@ -862,6 +1005,13 @@ const struct arc_flag_class arc_flag_classes[] =
 
 #define C_NE	    (C_AS + 1)
   { CND, { F_NE, F_NULL}},
+
+  /* ARC NPS400 Support: See comment near head of file.  */
+#define C_NPS_CL     (C_NE + 1)
+  { FLG, { F_NPS_CL, F_NULL}},
+
+#define C_NPS_F     (C_NPS_CL + 1)
+  { FLG, { F_NPS_FLAG, F_NULL}},
 };
 
 /* The operands table.
@@ -1180,6 +1330,29 @@ const struct arc_operand arc_operands[] =
   /* UIMM6_5_S mask = 0000011111100000.  */
 #define UIMM6_5_S	(W6 + 1)
   {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s},
+
+  /* ARC NPS400 Support: See comment near head of file.  */
+#define NPS_R_DST	(UIMM6_5_S + 1)
+  { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_dst, extract_nps_dst },
+
+#define NPS_R_DST_CL_Z	(NPS_R_DST + 1)
+  { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_dst, extract_nps_dst_cl_z },
+
+#define NPS_R_SRC1_IN_DST	(NPS_R_DST_CL_Z + 1)
+  { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_dst, extract_nps_src1_in_dst },
+
+#define NPS_R_SRC2	(NPS_R_SRC1_IN_DST + 1)
+  { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_src2, extract_nps_src2 },
+
+  /* Next 3 operands are integer immediate for bitops.  */
+#define NPS_BITOP_DST_POS	(NPS_R_SRC2 + 1)
+  { 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
+
+#define NPS_BITOP_SRC_POS	(NPS_BITOP_DST_POS + 1)
+  { 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
+
+#define NPS_BITOP_SIZE		(NPS_BITOP_SRC_POS + 1)
+  { 5, 10, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_size, extract_nps_bitop_size },
 };
 
 const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
@@ -1195,6 +1368,10 @@ const unsigned arc_NToperand = FKT_NT;
 const struct arc_opcode arc_opcodes[] =
 {
 #include "arc-tbl.h"
+
+#ifdef ARC_OPCODE_EXTENSION_INSN_FILE
+#include ARC_OPCODE_EXTENSION_INSN_FILE
+#endif /* ARC_OPCODE_EXTENSION_INSN_FILE */
 };
 
 const unsigned arc_num_opcodes = ARRAY_SIZE (arc_opcodes);
diff --git a/opcodes/config.in b/opcodes/config.in
index 55a80fd..174bfb4 100644
--- a/opcodes/config.in
+++ b/opcodes/config.in
@@ -7,6 +7,9 @@
 #endif
 #define __CONFIG_H__ 1
 
+/* ARC extension instructions. */
+#undef ARC_OPCODE_EXTENSION_INSN_FILE
+
 /* Define to 1 if translation of program messages to the user's native
    language is requested. */
 #undef ENABLE_NLS
diff --git a/opcodes/configure b/opcodes/configure
index 75c6573..78d4a59 100755
--- a/opcodes/configure
+++ b/opcodes/configure
@@ -12505,6 +12505,14 @@ fi
 
 # target-specific stuff:
 
+case ${target} in
+  arc*-mellanox-*)
+
+$as_echo "#define ARC_OPCODE_EXTENSION_INSN_FILE \"arc-nps400-tbl.h\"" >>confdefs.h
+
+    ;;
+esac
+
 # Canonicalize the secondary target names.
 if test -n "$enable_targets" ; then
     for targ in `echo $enable_targets | sed 's/,/ /g'`
diff --git a/opcodes/configure.ac b/opcodes/configure.ac
index c7f4783..05b55ca 100644
--- a/opcodes/configure.ac
+++ b/opcodes/configure.ac
@@ -210,6 +210,12 @@ AC_SUBST(SHARED_DEPENDENCIES)
 
 # target-specific stuff:
 
+case ${target} in
+  arc*-mellanox-*)
+    AC_DEFINE(ARC_OPCODE_EXTENSION_INSN_FILE, "arc-nps400-tbl.h", [ARC extension instructions.])
+    ;;
+esac
+
 # Canonicalize the secondary target names.
 if test -n "$enable_targets" ; then
     for targ in `echo $enable_targets | sed 's/,/ /g'`
-- 
2.6.4


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