This is the mail archive of the
binutils@sourceware.org
mailing list for the binutils project.
[OPCODES][ARM]Fix mask for a few coprocessor opcodes.
- From: Renlin Li <renlin dot li at foss dot arm dot com>
- To: binutils at sourceware dot org
- Cc: Nicholas Clifton <nickc at redhat dot com>, Marcus Shawcroft <Marcus dot Shawcroft at arm dot com>, Ramana Radhakrishnan <Ramana dot Radhakrishnan at arm dot com>
- Date: Thu, 18 Feb 2016 15:13:29 +0000
- Subject: [OPCODES][ARM]Fix mask for a few coprocessor opcodes.
- Authentication-results: sourceware.org; auth=none
- References: <56C5DDC8 dot 4080901 at foss dot arm dot com>
Hi all,
This is a simple patch to fix a few coprocessor opcode masks.
for example:
.inst 0xfe011a10 //unpredictable mcr2 instruction.
.inst 0xfe011a00 // valid vsel.
However, when objdumped, those two all dumped as:
0: fe011a10 vseleq.f32 s2, s2, s0
4: fe011a00 vseleq.f32 s2, s2, s0
This is not correct. The correct dump should be:
0: fe011a10 mcr2 10, 0, r1, cr1, cr0, {0} ; <UNPREDICTABLE>
4: fe011a00 vseleq.f32 s2, s2, s0
The mask here is not strict enough to differentiate is from other instructions.
I discovered this when you were adding support for armv8.2.
This patch depends on another patch post earlier to give the unpredictable
information about mcr2 instruction:
https://sourceware.org/ml/binutils/2016-02/msg00261.html
All Binutils regression tests run Okay without any new issues. Okay to commit?
opcodes/ChangeLog:
2016-02-18 Renlin Li <renlin.li@arm.com>
* arm-dis.c (coprocessor_opcodes): Fix mask for vsel, vmaxnm, vminnm,
vrint(mpna).
* testsuite/gas/arm/mask_1.d: New.
* testsuite/gas/arm/mask_1.s: New.
commit fcca0d37f1ffa9dec1c75fa98614afb3e98696c6
Author: Renlin Li <renlin.li@arm.com>
Date: Thu Sep 17 09:31:17 2015 +0100
fix mask bug
diff --git a/gas/testsuite/gas/arm/mask_1.d b/gas/testsuite/gas/arm/mask_1.d
new file mode 100644
index 0000000..eddcd65
--- /dev/null
+++ b/gas/testsuite/gas/arm/mask_1.d
@@ -0,0 +1,28 @@
+#objdump: -dr --prefix-address --show-raw-insn
+#name: vsel, vmaxnm, vminnm, vrint decoding mask.
+#as: -march=armv8-a
+# This test is only valid on ELF based ports.
+#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+
+# Test VFMA instruction disassembly
+
+.*: *file format .*arm.*
+
+
+Disassembly of section .text:
+0+000 <.*> fe011a10 mcr2 10, 0, r1, cr1, cr0, \{0\} ; <UNPREDICTABLE>
+0+004 <.*> fe011b10 mcr2 11, 0, r1, cr1, cr0, \{0\} ; <UNPREDICTABLE>
+0+008 <.*> fe811a10 mcr2 10, 4, r1, cr1, cr0, \{0\} ; <UNPREDICTABLE>
+0+00c <.*> fe811b10 mcr2 11, 4, r1, cr1, cr0, \{0\} ; <UNPREDICTABLE>
+0+010 <.*> fe811a50 mcr2 10, 4, r1, cr1, cr0, \{2\} ; <UNPREDICTABLE>
+0+014 <.*> fe811b50 mcr2 11, 4, r1, cr1, cr0, \{2\} ; <UNPREDICTABLE>
+0+018 <.*> fefb0ae0 ; <UNDEFINED> instruction: 0xfefb0ae0
+0+01c <.*> fefb0be0 ; <UNDEFINED> instruction: 0xfefb0be0
+0+020 <.*> fefb0ae0 ; <UNDEFINED> instruction: 0xfefb0ae0
+0+024 <.*> fefb0be0 ; <UNDEFINED> instruction: 0xfefb0be0
+0+028 <.*> fef80ae0 ; <UNDEFINED> instruction: 0xfef80ae0
+0+02c <.*> fef80be0 ; <UNDEFINED> instruction: 0xfef80be0
+0+030 <.*> fef90ae0 ; <UNDEFINED> instruction: 0xfef90ae0
+0+034 <.*> fef90be0 ; <UNDEFINED> instruction: 0xfef90be0
+0+038 <.*> fefa0ae0 ; <UNDEFINED> instruction: 0xfefa0ae0
+0+03c <.*> fefa0be0 ; <UNDEFINED> instruction: 0xfefa0be0
diff --git a/gas/testsuite/gas/arm/mask_1.s b/gas/testsuite/gas/arm/mask_1.s
new file mode 100644
index 0000000..7a347d8
--- /dev/null
+++ b/gas/testsuite/gas/arm/mask_1.s
@@ -0,0 +1,17 @@
+ .text
+ .inst 0xfe011a10 @ mcr2 10, 0, r1, cr1, cr0, {0} <UNPREDICTABLE>
+ .inst 0xfe011b10 @ mcr2 11, 0, r1, cr1, cr0, {0} <UNPREDICTABLE>
+ .inst 0xfe811a10 @ mcr2 10, 4, r1, cr1, cr0, {0} <UNPREDICTABLE>
+ .inst 0xfe811b10 @ mcr2 11, 4, r1, cr1, cr0, {0} <UNPREDICTABLE>
+ .inst 0xfe811a50 @ mcr2 10, 4, r1, cr1, cr0, {2} <UNPREDICTABLE>
+ .inst 0xfe811b50 @ mcr2 11, 4, r1, cr1, cr0, {2} <UNPREDICTABLE>
+ .inst 0xfefb0ae0 @ <UNDEFINED> instruction: 0xfefb0ae0
+ .inst 0xfefb0be0 @ <UNDEFINED> instruction: 0xfefb0be0
+ .inst 0xfefb0ae0 @ <UNDEFINED> instruction: 0xfefb0ae0
+ .inst 0xfefb0be0 @ <UNDEFINED> instruction: 0xfefb0be0
+ .inst 0xfef80ae0 @ <UNDEFINED> instruction: 0xfef80ae0
+ .inst 0xfef80be0 @ <UNDEFINED> instruction: 0xfef80be0
+ .inst 0xfef90ae0 @ <UNDEFINED> instruction: 0xfef90ae0
+ .inst 0xfef90be0 @ <UNDEFINED> instruction: 0xfef90be0
+ .inst 0xfefa0ae0 @ <UNDEFINED> instruction: 0xfefa0ae0
+ .inst 0xfefa0be0 @ <UNDEFINED> instruction: 0xfefa0be0
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 430da08..62934f1 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -819,17 +819,17 @@ static const struct opcode32 coprocessor_opcodes[] =
/* FP v5. */
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
- 0xfe000a00, 0xff800f00, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
+ 0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
- 0xfe000b00, 0xff800f00, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
+ 0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
- 0xfe800a00, 0xffb00f40, "vmaxnm%u.f32\t%y1, %y2, %y0"},
+ 0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
- 0xfe800b00, 0xffb00f40, "vmaxnm%u.f64\t%z1, %z2, %z0"},
+ 0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
- 0xfe800a40, 0xffb00f40, "vminnm%u.f32\t%y1, %y2, %y0"},
+ 0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
- 0xfe800b40, 0xffb00f40, "vminnm%u.f64\t%z1, %z2, %z0"},
+ 0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
@@ -839,9 +839,9 @@ static const struct opcode32 coprocessor_opcodes[] =
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
- 0xfeb80a40, 0xffbc0f50, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
+ 0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
{ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
- 0xfeb80b40, 0xffbc0f50, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
+ 0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
/* Generic coprocessor instructions. */
{ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },