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[AArch64][PATCH 9/14] Support FP16 Adv.SIMD Modified Immediate instructions.
- From: Matthew Wahab <matthew dot wahab at foss dot arm dot com>
- To: binutils at sourceware dot org
- Date: Fri, 11 Dec 2015 12:14:27 +0000
- Subject: [AArch64][PATCH 9/14] Support FP16 Adv.SIMD Modified Immediate instructions.
- Authentication-results: sourceware.org; auth=none
- References: <566AB800 dot 1090308 at foss dot arm dot com>
ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds an FP16
instruction to the group Adv.SIMD Modified Immediate, making it
available when +simd+fp16 is enabled.
The instruction added is: FMOV.
The form of this instructions is
<OP> <Hd>, #<imm>
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
Ok for trunk?
Matthew
gas/testsuite/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/advsimd-fp16.d: Update expected output.
* gas/aarch64/advsimd-fp16.s: Add tests for Adv.SIMD modified immediate
instructions.
opcodes/
2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-tbl.h (QL_SIMD_IMM_H): New.
(aarch64_opcode_table): Add fp16 version of fmov to the Adv.SIMD
modified immediate group.
>From 1ca28d5a28129d4b76e87780102998a52883c132 Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Thu, 10 Sep 2015 17:07:29 +0100
Subject: [PATCH 09/14] [AArch64] Add FP16 Adv.SIMD modified immediate
instructions (VIII).
---
gas/testsuite/gas/aarch64/advsimd-fp16.d | 7 +
gas/testsuite/gas/aarch64/advsimd-fp16.s | 9 +
opcodes/aarch64-asm-2.c | 684 ++++-----
opcodes/aarch64-dis-2.c | 2306 +++++++++++++++---------------
opcodes/aarch64-opc-2.c | 74 +-
opcodes/aarch64-tbl.h | 9 +
6 files changed, 1558 insertions(+), 1531 deletions(-)
diff --git a/gas/testsuite/gas/aarch64/advsimd-fp16.d b/gas/testsuite/gas/aarch64/advsimd-fp16.d
index 241dc3f..5abad7e 100644
--- a/gas/testsuite/gas/aarch64/advsimd-fp16.d
+++ b/gas/testsuite/gas/aarch64/advsimd-fp16.d
@@ -492,3 +492,10 @@ Disassembly of section \.text:
[0-9a-f]+: 4eb0f841 fminv h1, v2.8h
[0-9a-f]+: 0eb0f800 fminv h0, v0.4h
[0-9a-f]+: 4eb0f800 fminv h0, v0.8h
+ [0-9a-f]+: 6f00f401 fmov v1.2d, #2.000000000000000000e\+00
+ [0-9a-f]+: 0f00f401 fmov v1.2s, #2.000000000000000000e\+00
+ [0-9a-f]+: 4f00f401 fmov v1.4s, #2.000000000000000000e\+00
+ [0-9a-f]+: 0f00fc01 fmov v1.4h, #2.000000000000000000e\+00
+ [0-9a-f]+: 4f00fc01 fmov v1.8h, #2.000000000000000000e\+00
+ [0-9a-f]+: 0f03fe00 fmov v0.4h, #1.000000000000000000e\+00
+ [0-9a-f]+: 4f03fe00 fmov v0.8h, #1.000000000000000000e\+00
diff --git a/gas/testsuite/gas/aarch64/advsimd-fp16.s b/gas/testsuite/gas/aarch64/advsimd-fp16.s
index c4e0ad1..75aacf6 100644
--- a/gas/testsuite/gas/aarch64/advsimd-fp16.s
+++ b/gas/testsuite/gas/aarch64/advsimd-fp16.s
@@ -203,3 +203,12 @@
across_lanes fminnmv
across_lanes fminv
+ /* Adv.SIMD modified immediate. */
+
+ fmov v1.2d, #2.0
+ fmov v1.2s, #2.0
+ fmov v1.4s, #2.0
+ fmov v1.4h, #2.0
+ fmov v1.8h, #2.0
+ fmov v0.4h, #1.0
+ fmov v0.8h, #1.0
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 12b44f3..c359903 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1313,6 +1313,13 @@
QLF2(S_D, NIL), \
}
+/* e.g. FMOV <Vd>.<T>, #<imm>. */
+#define QL_SIMD_IMM_H \
+{ \
+ QLF2 (V_4H, NIL), \
+ QLF2 (V_8H, NIL), \
+}
+
/* e.g. MOVI <Vd>.2D, #<imm>. */
#define QL_SIMD_IMM_V2D \
{ \
@@ -1512,6 +1519,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
{"movi", 0xf00c400, 0xbff8ec00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S1W, F_SIZEQ},
{"movi", 0xf00e400, 0xbff8fc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_B, F_SIZEQ},
{"fmov", 0xf00f400, 0xbff8fc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_S, F_SIZEQ},
+ {"fmov", 0xf00fc00, 0xbff8fc00, asimdimm, 0, SIMD_F16,
+ OP2 (Vd, SIMD_FPIMM), QL_SIMD_IMM_H, F_SIZEQ},
{"mvni", 0x2f000400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ},
{"bic", 0x2f001400, 0xbff89c00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0W, F_SIZEQ},
{"mvni", 0x2f008400, 0xbff8dc00, asimdimm, 0, SIMD, OP2 (Vd, SIMD_IMM_SFT), QL_SIMD_IMM_S0H, F_SIZEQ},
--
2.1.4