[AArch64][PATCH 7/14] Support FP16 Scalar Indexed Element instructions.

[Matthew Wahab <matthew dot wahab at foss dot arm dot com>]

ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. This patch adds FP16
instructions to the group Scalar Indexed Element, making them available
when +simd+fp16 is enabled.

The instructions added are: FMLA, FMLS, FMUL and FMULX.

The general form for these instructions is
  <OP> <Hd>, <Hs>, <V>.h[<idx>]

Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.

Ok for trunk?
Matthew

gas/testsuite/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* gas/aarch64/advsimd-fp16.d: Update expected output.
	* gas/aarch64/advsimd-fp16.s: Add tests for scalar indexed element
	instructions.

opcodes/
2015-12-10  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of fmla,
	fmls, fmul and fmulx to the scalar indexed element group.

>From dabaaf5c60c04e7c51ecdf3f2734377216ece5be Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Thu, 10 Sep 2015 15:45:00 +0100
Subject: [PATCH 07/14] [AArch64] Add FP16 Scalar indexed element instructions
 (VI).

---
 gas/testsuite/gas/aarch64/advsimd-fp16.d |   16 +
 gas/testsuite/gas/aarch64/advsimd-fp16.s |   15 +
 opcodes/aarch64-asm-2.c                  |  612 +++++------
 opcodes/aarch64-dis-2.c                  | 1766 +++++++++++++++---------------
 opcodes/aarch64-opc-2.c                  |   88 +-
 opcodes/aarch64-tbl.h                    |    8 +
 6 files changed, 1294 insertions(+), 1211 deletions(-)

diff --git a/gas/testsuite/gas/aarch64/advsimd-fp16.d b/gas/testsuite/gas/aarch64/advsimd-fp16.d
index 3fd4dcb..dacd51b 100644
--- a/gas/testsuite/gas/aarch64/advsimd-fp16.d
+++ b/gas/testsuite/gas/aarch64/advsimd-fp16.d
@@ -456,3 +456,19 @@ Disassembly of section \.text:
  [0-9a-f]+:	2f039041 	fmulx	v1.4h, v2.4h, v3.h\[0\]
  [0-9a-f]+:	6f009000 	fmulx	v0.8h, v0.8h, v0.h\[0\]
  [0-9a-f]+:	6f039041 	fmulx	v1.8h, v2.8h, v3.h\[0\]
+ [0-9a-f]+:	5fc31841 	fmla	d1, d2, v3.d\[1\]
+ [0-9a-f]+:	5fa31041 	fmla	s1, s2, v3.s\[1\]
+ [0-9a-f]+:	5f131041 	fmla	h1, h2, v3.h\[1\]
+ [0-9a-f]+:	5f001000 	fmla	h0, h0, v0.h\[0\]
+ [0-9a-f]+:	5fc35841 	fmls	d1, d2, v3.d\[1\]
+ [0-9a-f]+:	5fa35041 	fmls	s1, s2, v3.s\[1\]
+ [0-9a-f]+:	5f135041 	fmls	h1, h2, v3.h\[1\]
+ [0-9a-f]+:	5f005000 	fmls	h0, h0, v0.h\[0\]
+ [0-9a-f]+:	5fc39841 	fmul	d1, d2, v3.d\[1\]
+ [0-9a-f]+:	5fa39041 	fmul	s1, s2, v3.s\[1\]
+ [0-9a-f]+:	5f139041 	fmul	h1, h2, v3.h\[1\]
+ [0-9a-f]+:	5f009000 	fmul	h0, h0, v0.h\[0\]
+ [0-9a-f]+:	7fc39841 	fmulx	d1, d2, v3.d\[1\]
+ [0-9a-f]+:	7fa39041 	fmulx	s1, s2, v3.s\[1\]
+ [0-9a-f]+:	7f139041 	fmulx	h1, h2, v3.h\[1\]
+ [0-9a-f]+:	7f009000 	fmulx	h0, h0, v0.h\[0\]
diff --git a/gas/testsuite/gas/aarch64/advsimd-fp16.s b/gas/testsuite/gas/aarch64/advsimd-fp16.s
index ebdb97a..10f9067 100644
--- a/gas/testsuite/gas/aarch64/advsimd-fp16.s
+++ b/gas/testsuite/gas/aarch64/advsimd-fp16.s
@@ -172,3 +172,18 @@
 
 	indexed_elem fmul
 	indexed_elem fmulx
+
+	/* Scalar indexed element.  */
+
+	.macro sindexed_elem, op
+	\op	d1, d2, v3.d[1]
+	\op	s1, s2, v3.s[1]
+	\op	h1, h2, v3.h[1]
+	\op	h0, h0, v0.h[0]
+	.endm
+
+	sindexed_elem fmla
+	sindexed_elem fmls
+
+	sindexed_elem fmul
+	sindexed_elem fmulx
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index fe21511..147e3f3 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1839,9 +1839,17 @@ struct aarch64_opcode aarch64_opcode_table[] =
   {"sqdmulh", 0x5f00c000, 0xff00f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE},
   {"sqrdmulh", 0x5f00d000, 0xff00f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE},
   {"fmla", 0x5f801000, 0xff80f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE},
+  {"fmla", 0x5f001000, 0xffc0f400, asisdelem, 0, SIMD_F16,
+   OP3 (Sd, Sn, Em), QL_FP3_H, F_SSIZE},
   {"fmls", 0x5f805000, 0xff80f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE},
+  {"fmls", 0x5f005000, 0xffc0f400, asisdelem, 0, SIMD_F16,
+   OP3 (Sd, Sn, Em), QL_FP3_H, F_SSIZE},
   {"fmul", 0x5f809000, 0xff80f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE},
+  {"fmul", 0x5f009000, 0xffc0f400, asisdelem, 0, SIMD_F16,
+   OP3 (Sd, Sn, Em), QL_FP3_H, F_SSIZE},
   {"fmulx", 0x7f809000, 0xff80f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE},
+  {"fmulx", 0x7f009000, 0xffc0f400, asisdelem, 0, SIMD_F16,
+   OP3 (Sd, Sn, Em), QL_FP3_H, F_SSIZE},
   {"sqrdmlah", 0x7f00d000, 0xff00f400, asisdelem, 0, RDMA, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE},
   {"sqrdmlsh", 0x7f00f000, 0xff00f400, asisdelem, 0, RDMA, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE},
   /* AdvSIMD load/store multiple structures.  */
-- 
2.1.4