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[Aarch64] Support ARMv8.2 AT instructions
- From: Matthew Wahab <matthew dot wahab at foss dot arm dot com>
- To: "binutils at sourceware dot org" <binutils at sourceware dot org>
- Date: Thu, 10 Dec 2015 12:30:49 +0000
- Subject: [Aarch64] Support ARMv8.2 AT instructions
- Authentication-results: sourceware.org; auth=none
Hello,
ARMv8.2 adds new instructions AT S1E1RP and AT S1E1WP to Aarch64. This
patch adds support for the instructions, making them available when
-march=armv8.2-a is selected.
Tested aarch64-none-linux-gnu with cross-compiled check-binutils and
check-gas.
Ok for trunk?
Matthew
gas/testsuite/
2015-12-09 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/sysreg-2.d: Update for new tests for AT S1E1RP and
AT S1E1WP.
* gas/aarch64/sysreg-2.s: Add tests for AT S1E1RP and AT S1E1WP.
opcodes/
2015-12-09 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
(aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
feature test for "s1e1rp" and "s1e1wp".
>From b571a152d31e272937050219ee2b965c32c42957 Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Thu, 12 Nov 2015 13:01:38 +0000
Subject: [PATCH] [Aarch64] Support ARMv8.2 AT instructions
Change-Id: I07cafaa422492be3ebc4fc17ffd9ac01b2fdd06e
---
gas/testsuite/gas/aarch64/sysreg-2.d | 3 ++-
gas/testsuite/gas/aarch64/sysreg-2.s | 4 ++++
opcodes/aarch64-opc.c | 8 ++++++++
3 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/gas/testsuite/gas/aarch64/sysreg-2.d b/gas/testsuite/gas/aarch64/sysreg-2.d
index 5c9838f..ececfa7 100644
--- a/gas/testsuite/gas/aarch64/sysreg-2.d
+++ b/gas/testsuite/gas/aarch64/sysreg-2.d
@@ -12,4 +12,5 @@ Disassembly of section .text:
[0-9a-f]+: d50b7a20 dc cvac, x0
[0-9a-f]+: d50b7b21 dc cvau, x1
[0-9a-f]+: d50b7c22 dc cvap, x2
-
+ [0-9a-f]+: d5087900 at s1e1rp, x0
+ [0-9a-f]+: d5087921 at s1e1wp, x1
diff --git a/gas/testsuite/gas/aarch64/sysreg-2.s b/gas/testsuite/gas/aarch64/sysreg-2.s
index d45aaa0..a249d96 100644
--- a/gas/testsuite/gas/aarch64/sysreg-2.s
+++ b/gas/testsuite/gas/aarch64/sysreg-2.s
@@ -20,3 +20,7 @@
dc cvau, x1
dc cvap, x2
+ /* AT. */
+
+ at s1e1rp, x0
+ at s1e1wp, x1
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 59303a0..f7ce850 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -3233,6 +3233,8 @@ const aarch64_sys_ins_reg aarch64_sys_regs_at[] =
{ "s1e2w", CPENS (4, C7, C8, 1), F_HASXT },
{ "s1e3r", CPENS (6, C7, C8, 0), F_HASXT },
{ "s1e3w", CPENS (6, C7, C8, 1), F_HASXT },
+ { "s1e1rp", CPENS (0, C7, C9, 0), F_HASXT | F_ARCHEXT },
+ { "s1e1wp", CPENS (0, C7, C9, 1), F_HASXT | F_ARCHEXT },
{ 0, CPENS(0,0,0,0), 0 }
};
@@ -3291,6 +3293,12 @@ aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
return FALSE;
+ /* AT S1E1RP, AT S1E1WP. Values are from aarch64_sys_regs_at. */
+ if ((reg->value == CPENS (0, C7, C9, 0)
+ || reg->value == CPENS (0, C7, C9, 1))
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
+ return FALSE;
+
return TRUE;
}
--
2.1.4