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[AArch64][PATCH 1/2] Add support for ARMv8.2 DC CVAP instruction.
- From: Matthew Wahab <matthew dot wahab at foss dot arm dot com>
- To: "binutils at sourceware dot org" <binutils at sourceware dot org>
- Date: Wed, 9 Dec 2015 09:52:03 +0000
- Subject: [AArch64][PATCH 1/2] Add support for ARMv8.2 DC CVAP instruction.
- Authentication-results: sourceware.org; auth=none
Hello,
ARMv8.2 adds the new system instruction DC CVAP. This patch series adds
support for this instruction to binutils, enabled when -march=armv8.2-a
is selected.
The AArch64 binutils record of some system registers uses a boolean
value to hold the single flag currently supported for them. To allow
these registers to be limited to specific architectures, the first patch
in this series replaces the boolean flag with a bitset and feature test.
The following patch adds support for the DC CVAP instruction.
Tested the series for aarch64-none-linux-gnu with cross-compiled
check-binutils and check-gas.
Ok for trunk?
Matthew
include/opcode/
2015-12-09 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags.
(aarch64_sys_ins_reg_has_xt): Declare.
opcodes/
2015-12-09 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
with aarch64_sys_ins_reg_has_xt.
(aarch64_ext_sysins_op): Likewise.
* aarch64-opc.c (operand_general_constraint_met_p): Likewise.
(F_HASXT): New.
(aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
(aarch64_sys_regs_dc): Likewise.
(aarch64_sys_regs_at): Likewise.
(aarch64_sys_regs_tlbi): Likewise.
(aarch64_sys_ins_reg_has_xt): New.
>From 788dcd8c300ee853e5335d4ac0b5335e0343ab52 Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Thu, 12 Nov 2015 10:49:37 +0000
Subject: [PATCH 1/2] [AArch64][PATCH 1/2] Add support for ARMv8.2 DC CVAP
instruction.
---
include/opcode/aarch64.h | 4 +-
opcodes/aarch64-dis.c | 4 +-
opcodes/aarch64-opc.c | 104 +++++++++++++++++++++++++++--------------------
3 files changed, 64 insertions(+), 48 deletions(-)
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index f1658bc..68a949f 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -667,9 +667,11 @@ typedef struct
{
const char *name;
uint32_t value;
- int has_xt;
+ uint32_t flags ;
} aarch64_sys_ins_reg;
+extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
+
extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index efa1074..631f076 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -248,7 +248,7 @@ aarch64_ext_regrt_sysins (const aarch64_operand *self, aarch64_opnd_info *info,
/* This will make the constraint checking happy and more importantly will
help the disassembler determine whether this operand is optional or
not. */
- info->present = inst->operands[0].sysins_op->has_xt;
+ info->present = aarch64_sys_ins_reg_has_xt (inst->operands[0].sysins_op);
return 1;
}
@@ -1034,7 +1034,7 @@ aarch64_ext_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED,
DEBUG_TRACE ("%s found value: %x, has_xt: %d, i: %d.",
info->sysins_op->name,
(unsigned)info->sysins_op->value,
- info->sysins_op->has_xt, i);
+ aarch64_sys_ins_reg_has_xt (info->sysins_op), i);
return 1;
}
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index db14ce2..9fa7467 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -1279,12 +1279,14 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
{
assert (idx == 1 && (aarch64_get_operand_class (opnds[0].type)
== AARCH64_OPND_CLASS_SYSTEM));
- if (opnds[1].present && !opnds[0].sysins_op->has_xt)
+ if (opnds[1].present
+ && !aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
{
set_other_error (mismatch_detail, idx, _("extraneous register"));
return 0;
}
- if (!opnds[1].present && opnds[0].sysins_op->has_xt)
+ if (!opnds[1].present
+ && aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
{
set_other_error (mismatch_detail, idx, _("missing register"));
return 0;
@@ -2756,6 +2758,12 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
#endif
#define F_ARCHEXT 0x2 /* Architecture dependent system register. */
+#ifdef F_HASXT
+#undef F_HASXT
+#endif
+#define F_HASXT 0x4 /* System instruction register <Xt>
+ operand. */
+
/* TODO there are two more issues need to be resolved
1. handle read-only and write-only system registers
@@ -3193,77 +3201,83 @@ const aarch64_sys_ins_reg aarch64_sys_regs_ic[] =
{
{ "ialluis", CPENS(0,C7,C1,0), 0 },
{ "iallu", CPENS(0,C7,C5,0), 0 },
- { "ivau", CPENS(3,C7,C5,1), 1 },
+ { "ivau", CPENS (3, C7, C5, 1), F_HASXT },
{ 0, CPENS(0,0,0,0), 0 }
};
const aarch64_sys_ins_reg aarch64_sys_regs_dc[] =
{
- { "zva", CPENS(3,C7,C4,1), 1 },
- { "ivac", CPENS(0,C7,C6,1), 1 },
- { "isw", CPENS(0,C7,C6,2), 1 },
- { "cvac", CPENS(3,C7,C10,1), 1 },
- { "csw", CPENS(0,C7,C10,2), 1 },
- { "cvau", CPENS(3,C7,C11,1), 1 },
- { "civac", CPENS(3,C7,C14,1), 1 },
- { "cisw", CPENS(0,C7,C14,2), 1 },
+ { "zva", CPENS (3, C7, C4, 1), F_HASXT },
+ { "ivac", CPENS (0, C7, C6, 1), F_HASXT },
+ { "isw", CPENS (0, C7, C6, 2), F_HASXT },
+ { "cvac", CPENS (3, C7, C10, 1), F_HASXT },
+ { "csw", CPENS (0, C7, C10, 2), F_HASXT },
+ { "cvau", CPENS (3, C7, C11, 1), F_HASXT },
+ { "civac", CPENS (3, C7, C14, 1), F_HASXT },
+ { "cisw", CPENS (0, C7, C14, 2), F_HASXT },
{ 0, CPENS(0,0,0,0), 0 }
};
const aarch64_sys_ins_reg aarch64_sys_regs_at[] =
{
- { "s1e1r", CPENS(0,C7,C8,0), 1 },
- { "s1e1w", CPENS(0,C7,C8,1), 1 },
- { "s1e0r", CPENS(0,C7,C8,2), 1 },
- { "s1e0w", CPENS(0,C7,C8,3), 1 },
- { "s12e1r", CPENS(4,C7,C8,4), 1 },
- { "s12e1w", CPENS(4,C7,C8,5), 1 },
- { "s12e0r", CPENS(4,C7,C8,6), 1 },
- { "s12e0w", CPENS(4,C7,C8,7), 1 },
- { "s1e2r", CPENS(4,C7,C8,0), 1 },
- { "s1e2w", CPENS(4,C7,C8,1), 1 },
- { "s1e3r", CPENS(6,C7,C8,0), 1 },
- { "s1e3w", CPENS(6,C7,C8,1), 1 },
+ { "s1e1r", CPENS (0, C7, C8, 0), F_HASXT },
+ { "s1e1w", CPENS (0, C7, C8, 1), F_HASXT },
+ { "s1e0r", CPENS (0, C7, C8, 2), F_HASXT },
+ { "s1e0w", CPENS (0, C7, C8, 3), F_HASXT },
+ { "s12e1r", CPENS (4, C7, C8, 4), F_HASXT },
+ { "s12e1w", CPENS (4, C7, C8, 5), F_HASXT },
+ { "s12e0r", CPENS (4, C7, C8, 6), F_HASXT },
+ { "s12e0w", CPENS (4, C7, C8, 7), F_HASXT },
+ { "s1e2r", CPENS (4, C7, C8, 0), F_HASXT },
+ { "s1e2w", CPENS (4, C7, C8, 1), F_HASXT },
+ { "s1e3r", CPENS (6, C7, C8, 0), F_HASXT },
+ { "s1e3w", CPENS (6, C7, C8, 1), F_HASXT },
{ 0, CPENS(0,0,0,0), 0 }
};
const aarch64_sys_ins_reg aarch64_sys_regs_tlbi[] =
{
{ "vmalle1", CPENS(0,C8,C7,0), 0 },
- { "vae1", CPENS(0,C8,C7,1), 1 },
- { "aside1", CPENS(0,C8,C7,2), 1 },
- { "vaae1", CPENS(0,C8,C7,3), 1 },
+ { "vae1", CPENS (0, C8, C7, 1), F_HASXT },
+ { "aside1", CPENS (0, C8, C7, 2), F_HASXT },
+ { "vaae1", CPENS (0, C8, C7, 3), F_HASXT },
{ "vmalle1is", CPENS(0,C8,C3,0), 0 },
- { "vae1is", CPENS(0,C8,C3,1), 1 },
- { "aside1is", CPENS(0,C8,C3,2), 1 },
- { "vaae1is", CPENS(0,C8,C3,3), 1 },
- { "ipas2e1is", CPENS(4,C8,C0,1), 1 },
- { "ipas2le1is",CPENS(4,C8,C0,5), 1 },
- { "ipas2e1", CPENS(4,C8,C4,1), 1 },
- { "ipas2le1", CPENS(4,C8,C4,5), 1 },
- { "vae2", CPENS(4,C8,C7,1), 1 },
- { "vae2is", CPENS(4,C8,C3,1), 1 },
+ { "vae1is", CPENS (0, C8, C3, 1), F_HASXT },
+ { "aside1is", CPENS (0, C8, C3, 2), F_HASXT },
+ { "vaae1is", CPENS (0, C8, C3, 3), F_HASXT },
+ { "ipas2e1is", CPENS (4, C8, C0, 1), F_HASXT },
+ { "ipas2le1is",CPENS (4, C8, C0, 5), F_HASXT },
+ { "ipas2e1", CPENS (4, C8, C4, 1), F_HASXT },
+ { "ipas2le1", CPENS (4, C8, C4, 5), F_HASXT },
+ { "vae2", CPENS (4, C8, C7, 1), F_HASXT },
+ { "vae2is", CPENS (4, C8, C3, 1), F_HASXT },
{ "vmalls12e1",CPENS(4,C8,C7,6), 0 },
{ "vmalls12e1is",CPENS(4,C8,C3,6), 0 },
- { "vae3", CPENS(6,C8,C7,1), 1 },
- { "vae3is", CPENS(6,C8,C3,1), 1 },
+ { "vae3", CPENS (6, C8, C7, 1), F_HASXT },
+ { "vae3is", CPENS (6, C8, C3, 1), F_HASXT },
{ "alle2", CPENS(4,C8,C7,0), 0 },
{ "alle2is", CPENS(4,C8,C3,0), 0 },
{ "alle1", CPENS(4,C8,C7,4), 0 },
{ "alle1is", CPENS(4,C8,C3,4), 0 },
{ "alle3", CPENS(6,C8,C7,0), 0 },
{ "alle3is", CPENS(6,C8,C3,0), 0 },
- { "vale1is", CPENS(0,C8,C3,5), 1 },
- { "vale2is", CPENS(4,C8,C3,5), 1 },
- { "vale3is", CPENS(6,C8,C3,5), 1 },
- { "vaale1is", CPENS(0,C8,C3,7), 1 },
- { "vale1", CPENS(0,C8,C7,5), 1 },
- { "vale2", CPENS(4,C8,C7,5), 1 },
- { "vale3", CPENS(6,C8,C7,5), 1 },
- { "vaale1", CPENS(0,C8,C7,7), 1 },
+ { "vale1is", CPENS (0, C8, C3, 5), F_HASXT },
+ { "vale2is", CPENS (4, C8, C3, 5), F_HASXT },
+ { "vale3is", CPENS (6, C8, C3, 5), F_HASXT },
+ { "vaale1is", CPENS (0, C8, C3, 7), F_HASXT },
+ { "vale1", CPENS (0, C8, C7, 5), F_HASXT },
+ { "vale2", CPENS (4, C8, C7, 5), F_HASXT },
+ { "vale3", CPENS (6, C8, C7, 5), F_HASXT },
+ { "vaale1", CPENS (0, C8, C7, 7), F_HASXT },
{ 0, CPENS(0,0,0,0), 0 }
};
+bfd_boolean
+aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *sys_ins_reg)
+{
+ return (sys_ins_reg->flags & F_HASXT) != 0;
+}
+
#undef C0
#undef C1
#undef C2
--
2.1.4