[PATCH] MIPS: Enable tlbinv and tlbinvf instructions for microMIPS; and mips32r3 and above

[Andrew Bennett <Andrew dot Bennett at imgtec dot com>]

Hi,

Currently the tlbinv and tlbinvf instructions are only enabled if the user 
enables the EVA ASE.  There are two issues with this.  Firstly these 
instructions are now in the Virtualization, not the EVA ASE (please see:
http://imgtec.com/mips/architectures/virtualization/).  Secondly they can
be optionally supported in MIPS ISA mips32r3 and above (in mips32r6 they
are supported by default).  This patch addresses these issues by:

1. Enabling the tlbinv and tlbinvf instructions by default for microMIPS 
   (because microMIPS is also mips32r3).

2. Enabling the tlbinv and tlbinvf instructions for MIPS when the ISA
   is mips32r3 and above, or if the user enabled the EVA or Virtualization
   ASEs.

I have also added some tests to the testsuite to check for tlbinv and 
tlbinvf.

The patch and ChangeLog is below.

Ok to commit?


Many thanks,



Andrew


gas/testsuite
	* gas/mips/micromips@mips32r3-tlb.d: New test.
	* gas/mips/mips32r3-tlb.d: Ditto.
	* gas/mips/mips32r3-tlb.s: Ditto.
	* gas/mips/mips.exp: Add in the mips32r3-tlb test.

opcodes/
	* micromips-opc.c (TLBINV): Add ASE_VIRT support.
	(micromips_opcodes): Enable tlbinv and tlbinvf by default.
	* mips-opc.c (TLBINV): Add ASE_VIRT support.
	(mips_builtin_opcodes): Enable tlbinv and tlbinvf for
	mips32r3 and above. 


diff --git a/gas/testsuite/gas/mips/micromips@mips32r3-tlb.d b/gas/testsuite/gas/mips/micromips@mips32r3-tlb.d
new file mode 100644
index 0000000..1dd3260
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromips@mips32r3-tlb.d
@@ -0,0 +1,13 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS32r3 TLB instructions
+#as: -32
+#source: mips32r3-tlb.s
+
+# Check MIPS32r3 TLB instructions assembly and disassembly (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 0000 437c 	tlbinv
+[0-9a-f]+ <[^>]*> 0000 537c 	tlbinvf
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 74e0a79..6fcda2f 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -1481,4 +1481,7 @@ if { [istarget mips*-*-vxworks*] } {
 
     run_list_test_arches "r6-branch-constraints"  "-32" \
 			[mips_arch_list_matching mips32r6]
+    run_dump_test_arches "mips32r3-tlb" [lsort -dictionary -unique [concat \
+					[mips_arch_list_matching micromips] \
+					[mips_arch_list_matching mips32r3] ] ]
 }
diff --git a/gas/testsuite/gas/mips/mips32r3-tlb.d b/gas/testsuite/gas/mips/mips32r3-tlb.d
new file mode 100644
index 0000000..64042ea
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips32r3-tlb.d
@@ -0,0 +1,13 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS32r3 TLB instructions
+#as: -32
+#source: mips32r3-tlb.s
+
+# Check MIPS32r3 TLB instructions assembly and disassembly
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 42000003 	tlbinv
+[0-9a-f]+ <[^>]*> 42000004 	tlbinvf
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mips32r3-tlb.s b/gas/testsuite/gas/mips/mips32r3-tlb.s
new file mode 100644
index 0000000..e1b7f02
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips32r3-tlb.s
@@ -0,0 +1,10 @@
+# Source file to test assembly of MIPS32r3 TLB instructions.
+
+	.text
+foo:
+	tlbinv
+	tlbinvf
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+	.align	2
+	.space  8
diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c
index 92ae40c..de39cb6 100644
--- a/opcodes/micromips-opc.c
+++ b/opcodes/micromips-opc.c
@@ -269,7 +269,7 @@ decode_micromips_operand (const char *p)
 #define EVA	ASE_EVA
 
 /* TLB invalidate instruction support.  */
-#define TLBINV	ASE_EVA
+#define TLBINV	(ASE_EVA | ASE_VIRT)
 
 /* MIPS Virtualization ASE.  */
 #define IVIRT	ASE_VIRT
@@ -1081,8 +1081,8 @@ const struct mips_opcode micromips_opcodes[] =
 {"tgeu",		"s,t,|",	0x0000043c, 0xfc000fff,	RD_1|RD_2|TRAP,		0,		I1,		0,	0 },
 {"tgeu",		"s,j",		0x41600000, 0xffe00000,	RD_1|TRAP,		0,		I1,		0,	0 }, /* tgeiu */
 {"tgeu",		"s,I",		0,    (int) M_TGEU_I,	INSN_MACRO,		0,		I1,		0,	0 },
-{"tlbinv",		"",		0x0000437c, 0xffffffff,	INSN_TLB,		0,		0,		TLBINV,	0 },
-{"tlbinvf",		"",		0x0000537c, 0xffffffff,	INSN_TLB,		0,		0,		TLBINV,	0 },
+{"tlbinv",		"",		0x0000437c, 0xffffffff,	INSN_TLB,		0,		I1,		0,	0 },
+{"tlbinvf",		"",		0x0000537c, 0xffffffff,	INSN_TLB,		0,		I1,		0,	0 },
 {"tlbginv",		"",		0x0000417c, 0xffffffff,	INSN_TLB,		0,		0,		IVIRT,	0 },
 {"tlbginvf",		"",		0x0000517c, 0xffffffff,	INSN_TLB,		0,		0,		IVIRT,	0 },
 {"tlbgp",		"",		0x0000017c, 0xffffffff,	INSN_TLB,		0,		0,		IVIRT,	0 },
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index b29a8ed..3e139f6 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -386,7 +386,7 @@ decode_mips_operand (const char *p)
 #define EVA	ASE_EVA
 
 /* TLB invalidate instruction support.  */
-#define TLBINV	ASE_EVA
+#define TLBINV	(ASE_EVA | ASE_VIRT)
 
 /* MSA support.  */
 #define MSA	ASE_MSA
@@ -1992,8 +1992,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"tgeu",		"s,t,q",	0x00000031, 0xfc00003f, RD_1|RD_2|TRAP,		0,		I2,		0,	0 },
 {"tgeu",		"s,j",		0x04090000, 0xfc1f0000, RD_1|TRAP,		0,		I2,		0,	I37 }, /* tgeiu */
 {"tgeu",		"s,I",		0,    (int) M_TGEU_I,	INSN_MACRO,		0,		I2,		0,	0 },
-{"tlbinv",		"",		0x42000003, 0xffffffff, INSN_TLB,       	0,		I37,		TLBINV,	0 },
-{"tlbinvf",		"",		0x42000004, 0xffffffff, INSN_TLB,       	0,		I37,		TLBINV,	0 },
+{"tlbinv",		"",		0x42000003, 0xffffffff, INSN_TLB,       	0,		I34,		TLBINV,	0 },
+{"tlbinvf",		"",		0x42000004, 0xffffffff, INSN_TLB,       	0,		I34,		TLBINV,	0 },
 {"tlbp",		"",		0x42000008, 0xffffffff, INSN_TLB,       	0,		I1,		0,	0 },
 {"tlbr",		"",		0x42000001, 0xffffffff, INSN_TLB,       	0,		I1,		0,	0 },
 {"tlbwi",		"",		0x42000002, 0xffffffff, INSN_TLB,       	0,		I1,		0,	0 },