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[PATCH] opcodes/ppc-opc.c: Add dscr and ctrl SPR mnemonics

2015-09-09  Anton Blanchard  <>

        * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.


diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 66ab438..4c821a4 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -4879,6 +4879,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mflr",	XSPR(31,339,  8), XSPR_MASK, COM|PPCVLE, PPCNONE,	{RT}},
 {"mfctr",	XSPR(31,339,  9), XSPR_MASK, COM|PPCVLE, PPCNONE,	{RT}},
 {"mftid",	XSPR(31,339, 17), XSPR_MASK, POWER,	PPCNONE,	{RT}},
+{"mfdscr",	XSPR(31,339, 17), XSPR_MASK, POWER6,	PPCNONE,	{RT}},
 {"mfdsisr",	XSPR(31,339, 18), XSPR_MASK, COM,	TITAN,  	{RT}},
 {"mfdar",	XSPR(31,339, 19), XSPR_MASK, COM,	TITAN,  	{RT}},
 {"mfdec",	XSPR(31,339, 22), XSPR_MASK, MFDEC2,	MFDEC1,		{RT}},
@@ -4893,6 +4894,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mfdear",	XSPR(31,339, 61), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,	{RT}},
 {"mfesr",	XSPR(31,339, 62), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,	{RT}},
 {"mfivpr",	XSPR(31,339, 63), XSPR_MASK, BOOKE|PPCVLE, PPCNONE,	{RT}},
+{"mfctrl",	XSPR(31,339,136), XSPR_MASK, POWER4,	PPCNONE,	{RT}},
 {"mfcmpa",	XSPR(31,339,144), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
 {"mfcmpb",	XSPR(31,339,145), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
 {"mfcmpc",	XSPR(31,339,146), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
@@ -5217,6 +5219,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mtlr",	XSPR(31,467,  8), XSPR_MASK, COM|PPCVLE, PPCNONE,	{RS}},
 {"mtctr", 	XSPR(31,467,  9), XSPR_MASK, COM|PPCVLE, PPCNONE,	{RS}},
 {"mttid",	XSPR(31,467, 17), XSPR_MASK, POWER,	PPCNONE,	{RS}},
+{"mtdscr",	XSPR(31,467, 17), XSPR_MASK, POWER6,	PPCNONE,	{RS}},
 {"mtdsisr",	XSPR(31,467, 18), XSPR_MASK, COM,	TITAN,  	{RS}},
 {"mtdar",	XSPR(31,467, 19), XSPR_MASK, COM,	TITAN,  	{RS}},
 {"mtrtcu",	XSPR(31,467, 20), XSPR_MASK, COM,	TITAN,  	{RS}},
@@ -5243,6 +5246,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mtcounta",	XSPR(31,467,150), XSPR_MASK, PPC860,	PPCNONE,	{RS}},
 {"mtcountb",	XSPR(31,467,151), XSPR_MASK, PPC860,	PPCNONE,	{RS}},
 {"mtcmpe",	XSPR(31,467,152), XSPR_MASK, PPC860,	PPCNONE,	{RS}},
+{"mtctrl",	XSPR(31,467,152), XSPR_MASK, POWER4,	PPCNONE,	{RS}},
 {"mtcmpf",	XSPR(31,467,153), XSPR_MASK, PPC860,	PPCNONE,	{RS}},
 {"mtcmpg",	XSPR(31,467,154), XSPR_MASK, PPC860,	PPCNONE,	{RS}},
 {"mtcmph",	XSPR(31,467,155), XSPR_MASK, PPC860,

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