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[PATCH] x86/Intel: fix mask instructions decoding.


For most of mask instructions, ModRM[7:6] must be 11b.
For some of them, ModRM[7:6] must be not 11b.
The patch makes decoder to conform these constraints.

opcodes/

	PR binutils/18257
	* i386-dis.c Use MOD_TABLE for most of mask instructions.
	(MOD enum) Add MOD_VEX_W_0_0F41_P_0_LEN_1, MOD_VEX_W_1_0F41_P_0_LEN_1,
	MOD_VEX_W_0_0F41_P_2_LEN_1, MOD_VEX_W_1_0F41_P_2_LEN_1,
	MOD_VEX_W_0_0F42_P_0_LEN_1, MOD_VEX_W_1_0F42_P_0_LEN_1,
	MOD_VEX_W_0_0F42_P_2_LEN_1, MOD_VEX_W_1_0F42_P_2_LEN_1,
	MOD_VEX_W_0_0F44_P_0_LEN_1, MOD_VEX_W_1_0F44_P_0_LEN_1,
	MOD_VEX_W_0_0F44_P_2_LEN_1, MOD_VEX_W_1_0F44_P_2_LEN_1,
	MOD_VEX_W_0_0F45_P_0_LEN_1, MOD_VEX_W_1_0F45_P_0_LEN_1,
	MOD_VEX_W_0_0F45_P_2_LEN_1, MOD_VEX_W_1_0F45_P_2_LEN_1,
	MOD_VEX_W_0_0F46_P_0_LEN_1, MOD_VEX_W_1_0F46_P_0_LEN_1,
	MOD_VEX_W_0_0F46_P_2_LEN_1, MOD_VEX_W_1_0F46_P_2_LEN_1,
	MOD_VEX_W_0_0F47_P_0_LEN_1, MOD_VEX_W_1_0F47_P_0_LEN_1,
	MOD_VEX_W_0_0F47_P_2_LEN_1, MOD_VEX_W_1_0F47_P_2_LEN_1,
	MOD_VEX_W_0_0F4A_P_0_LEN_1, MOD_VEX_W_1_0F4A_P_0_LEN_1,
	MOD_VEX_W_0_0F4A_P_2_LEN_1, MOD_VEX_W_1_0F4A_P_2_LEN_1,
	MOD_VEX_W_0_0F4B_P_0_LEN_1, MOD_VEX_W_1_0F4B_P_0_LEN_1,
	MOD_VEX_W_0_0F4B_P_2_LEN_1, MOD_VEX_W_0_0F91_P_0_LEN_0,
	MOD_VEX_W_1_0F91_P_0_LEN_0, MOD_VEX_W_0_0F91_P_2_LEN_0,
	MOD_VEX_W_1_0F91_P_2_LEN_0, MOD_VEX_W_0_0F92_P_0_LEN_0,
	MOD_VEX_W_0_0F92_P_2_LEN_0, MOD_VEX_W_0_0F92_P_3_LEN_0,
	MOD_VEX_W_1_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
	MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_W_0_0F93_P_3_LEN_0,
	MOD_VEX_W_1_0F93_P_3_LEN_0, MOD_VEX_W_0_0F98_P_0_LEN_0,
	MOD_VEX_W_1_0F98_P_0_LEN_0, MOD_VEX_W_0_0F98_P_2_LEN_0,
	MOD_VEX_W_1_0F98_P_2_LEN_0, MOD_VEX_W_0_0F99_P_0_LEN_0,
	MOD_VEX_W_1_0F99_P_0_LEN_0, MOD_VEX_W_0_0F99_P_2_LEN_0,
	MOD_VEX_W_1_0F99_P_2_LEN_0, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
	MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
	MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
	MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
	MOD_VEX_W_1_0F3A33_P_2_LEN_0.
	(vex_w_table) Replace terminals with MOD_TABLE entries for
	most of mask instructions.


---
 opcodes/i386-dis.c | 472 ++++++++++++++++++++++++++++++++++++++++++++++-------
 1 file changed, 413 insertions(+), 59 deletions(-)

diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index a279b56..e194956 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -819,6 +819,37 @@ enum
   MOD_VEX_0F16_PREFIX_0,
   MOD_VEX_0F17,
   MOD_VEX_0F2B,
+  MOD_VEX_W_0_0F41_P_0_LEN_1,
+  MOD_VEX_W_1_0F41_P_0_LEN_1,
+  MOD_VEX_W_0_0F41_P_2_LEN_1,
+  MOD_VEX_W_1_0F41_P_2_LEN_1,
+  MOD_VEX_W_0_0F42_P_0_LEN_1,
+  MOD_VEX_W_1_0F42_P_0_LEN_1,
+  MOD_VEX_W_0_0F42_P_2_LEN_1,
+  MOD_VEX_W_1_0F42_P_2_LEN_1,
+  MOD_VEX_W_0_0F44_P_0_LEN_1,
+  MOD_VEX_W_1_0F44_P_0_LEN_1,
+  MOD_VEX_W_0_0F44_P_2_LEN_1,
+  MOD_VEX_W_1_0F44_P_2_LEN_1,
+  MOD_VEX_W_0_0F45_P_0_LEN_1,
+  MOD_VEX_W_1_0F45_P_0_LEN_1,
+  MOD_VEX_W_0_0F45_P_2_LEN_1,
+  MOD_VEX_W_1_0F45_P_2_LEN_1,
+  MOD_VEX_W_0_0F46_P_0_LEN_1,
+  MOD_VEX_W_1_0F46_P_0_LEN_1,
+  MOD_VEX_W_0_0F46_P_2_LEN_1,
+  MOD_VEX_W_1_0F46_P_2_LEN_1,
+  MOD_VEX_W_0_0F47_P_0_LEN_1,
+  MOD_VEX_W_1_0F47_P_0_LEN_1,
+  MOD_VEX_W_0_0F47_P_2_LEN_1,
+  MOD_VEX_W_1_0F47_P_2_LEN_1,
+  MOD_VEX_W_0_0F4A_P_0_LEN_1,
+  MOD_VEX_W_1_0F4A_P_0_LEN_1,
+  MOD_VEX_W_0_0F4A_P_2_LEN_1,
+  MOD_VEX_W_1_0F4A_P_2_LEN_1,
+  MOD_VEX_W_0_0F4B_P_0_LEN_1,
+  MOD_VEX_W_1_0F4B_P_0_LEN_1,
+  MOD_VEX_W_0_0F4B_P_2_LEN_1,
   MOD_VEX_0F50,
   MOD_VEX_0F71_REG_2,
   MOD_VEX_0F71_REG_4,
@@ -830,6 +861,26 @@ enum
   MOD_VEX_0F73_REG_3,
   MOD_VEX_0F73_REG_6,
   MOD_VEX_0F73_REG_7,
+  MOD_VEX_W_0_0F91_P_0_LEN_0,
+  MOD_VEX_W_1_0F91_P_0_LEN_0,
+  MOD_VEX_W_0_0F91_P_2_LEN_0,
+  MOD_VEX_W_1_0F91_P_2_LEN_0,
+  MOD_VEX_W_0_0F92_P_0_LEN_0,
+  MOD_VEX_W_0_0F92_P_2_LEN_0,
+  MOD_VEX_W_0_0F92_P_3_LEN_0,
+  MOD_VEX_W_1_0F92_P_3_LEN_0,
+  MOD_VEX_W_0_0F93_P_0_LEN_0,
+  MOD_VEX_W_0_0F93_P_2_LEN_0,
+  MOD_VEX_W_0_0F93_P_3_LEN_0,
+  MOD_VEX_W_1_0F93_P_3_LEN_0,
+  MOD_VEX_W_0_0F98_P_0_LEN_0,
+  MOD_VEX_W_1_0F98_P_0_LEN_0,
+  MOD_VEX_W_0_0F98_P_2_LEN_0,
+  MOD_VEX_W_1_0F98_P_2_LEN_0,
+  MOD_VEX_W_0_0F99_P_0_LEN_0,
+  MOD_VEX_W_1_0F99_P_0_LEN_0,
+  MOD_VEX_W_0_0F99_P_2_LEN_0,
+  MOD_VEX_W_1_0F99_P_2_LEN_0,
   MOD_VEX_0FAE_REG_2,
   MOD_VEX_0FAE_REG_3,
   MOD_VEX_0FD7_PREFIX_2,
@@ -844,6 +895,14 @@ enum
   MOD_VEX_0F385A_PREFIX_2,
   MOD_VEX_0F388C_PREFIX_2,
   MOD_VEX_0F388E_PREFIX_2,
+  MOD_VEX_W_0_0F3A30_P_2_LEN_0,
+  MOD_VEX_W_1_0F3A30_P_2_LEN_0,
+  MOD_VEX_W_0_0F3A31_P_2_LEN_0,
+  MOD_VEX_W_1_0F3A31_P_2_LEN_0,
+  MOD_VEX_W_0_0F3A32_P_2_LEN_0,
+  MOD_VEX_W_1_0F3A32_P_2_LEN_0,
+  MOD_VEX_W_0_0F3A33_P_2_LEN_0,
+  MOD_VEX_W_1_0F3A33_P_2_LEN_0,
 
   MOD_EVEX_0F10_PREFIX_1,
   MOD_EVEX_0F10_PREFIX_3,
@@ -10445,82 +10504,82 @@ static const struct dis386 vex_w_table[][2] = {
   },
   {
     /* VEX_W_0F41_P_0_LEN_1 */
-    { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
-    { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
+    { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
+    { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) },
   },
   {
     /* VEX_W_0F41_P_2_LEN_1 */
-    { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
-    { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
+    { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) },
+    { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) }
   },
   {
     /* VEX_W_0F42_P_0_LEN_1 */
-    { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
-    { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
+    { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) },
+    { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) },
   },
   {
     /* VEX_W_0F42_P_2_LEN_1 */
-    { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
-    { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
+    { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) },
+    { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) },
   },
   {
     /* VEX_W_0F44_P_0_LEN_0 */
-    { "knotw",		{ MaskG, MaskR }, 0 },
-    { "knotq",		{ MaskG, MaskR }, 0 },
+    { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) },
+    { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) },
   },
   {
     /* VEX_W_0F44_P_2_LEN_0 */
-    { "knotb",		{ MaskG, MaskR }, 0 },
-    { "knotd",		{ MaskG, MaskR }, 0 },
+    { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) },
+    { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) },
   },
   {
     /* VEX_W_0F45_P_0_LEN_1 */
-    { "korw",           { MaskG, MaskVex, MaskR }, 0 },
-    { "korq",           { MaskG, MaskVex, MaskR }, 0 },
+    { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) },
+    { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) },
   },
   {
     /* VEX_W_0F45_P_2_LEN_1 */
-    { "korb",           { MaskG, MaskVex, MaskR }, 0 },
-    { "kord",           { MaskG, MaskVex, MaskR }, 0 },
+    { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) },
+    { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) },
   },
   {
     /* VEX_W_0F46_P_0_LEN_1 */
-    { "kxnorw",         { MaskG, MaskVex, MaskR }, 0 },
-    { "kxnorq",         { MaskG, MaskVex, MaskR }, 0 },
+    { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) },
+    { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) },
   },
   {
     /* VEX_W_0F46_P_2_LEN_1 */
-    { "kxnorb",         { MaskG, MaskVex, MaskR }, 0 },
-    { "kxnord",         { MaskG, MaskVex, MaskR }, 0 },
+    { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) },
+    { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) },
   },
   {
     /* VEX_W_0F47_P_0_LEN_1 */
-    { "kxorw",          { MaskG, MaskVex, MaskR }, 0 },
-    { "kxorq",          { MaskG, MaskVex, MaskR }, 0 },
+    { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) },
+    { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) },
   },
   {
     /* VEX_W_0F47_P_2_LEN_1 */
-    { "kxorb",          { MaskG, MaskVex, MaskR }, 0 },
-    { "kxord",          { MaskG, MaskVex, MaskR }, 0 },
+    { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) },
+    { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) },
   },
   {
     /* VEX_W_0F4A_P_0_LEN_1 */
-    { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
-    { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
+    { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) },
+    { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) },
   },
   {
     /* VEX_W_0F4A_P_2_LEN_1 */
-    { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
-    { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
+    { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) },
+    { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) },
   },
   {
     /* VEX_W_0F4B_P_0_LEN_1 */
-    { "kunpckwd",	{ MaskG, MaskVex, MaskR }, 0 },
-    { "kunpckdq",	{ MaskG, MaskVex, MaskR }, 0 },
+    { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) },
+    { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) },
   },
   {
     /* VEX_W_0F4B_P_2_LEN_1 */
-    { "kunpckbw",	{ MaskG, MaskVex, MaskR }, 0 },
+    { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
   },
   {
     /* VEX_W_0F50_M_0 */
@@ -10850,59 +10909,59 @@ static const struct dis386 vex_w_table[][2] = {
   },
   {
     /* VEX_W_0F91_P_0_LEN_0 */
-    { "kmovw",		{ Ew, MaskG }, 0 },
-    { "kmovq",		{ Eq, MaskG }, 0 },
+    { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
+    { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
   },
   {
     /* VEX_W_0F91_P_2_LEN_0 */
-    { "kmovb",		{ Eb, MaskG }, 0 },
-    { "kmovd",		{ Ed, MaskG }, 0 },
+    { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
+    { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
   },
   {
     /* VEX_W_0F92_P_0_LEN_0 */
-    { "kmovw",		{ MaskG, Rdq }, 0 },
+    { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
   },
   {
     /* VEX_W_0F92_P_2_LEN_0 */
-    { "kmovb",		{ MaskG, Rdq }, 0 },
+    { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
   },
   {
     /* VEX_W_0F92_P_3_LEN_0 */
-    { "kmovd",		{ MaskG, Rdq }, 0 },
-    { "kmovq",		{ MaskG, Rdq }, 0 },
+    { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
+    { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
   },
   {
     /* VEX_W_0F93_P_0_LEN_0 */
-    { "kmovw",		{ Gdq, MaskR }, 0 },
+    { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
   },
   {
     /* VEX_W_0F93_P_2_LEN_0 */
-    { "kmovb",		{ Gdq, MaskR }, 0 },
+    { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
   },
   {
     /* VEX_W_0F93_P_3_LEN_0 */
-    { "kmovd",		{ Gdq, MaskR }, 0 },
-    { "kmovq",		{ Gdq, MaskR }, 0 },
+    { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
+    { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
   },
   {
     /* VEX_W_0F98_P_0_LEN_0 */
-    { "kortestw",	{ MaskG, MaskR }, 0 },
-    { "kortestq",	{ MaskG, MaskR }, 0 },
+    { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
+    { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
   },
   {
     /* VEX_W_0F98_P_2_LEN_0 */
-    { "kortestb",	{ MaskG, MaskR }, 0 },
-    { "kortestd",	{ MaskG, MaskR }, 0 },
+    { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
+    { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
   },
   {
     /* VEX_W_0F99_P_0_LEN_0 */
-    { "ktestw",	{ MaskG, MaskR }, 0 },
-    { "ktestq",	{ MaskG, MaskR }, 0 },
+    { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
+    { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
   },
   {
     /* VEX_W_0F99_P_2_LEN_0 */
-    { "ktestb",	{ MaskG, MaskR }, 0 },
-    { "ktestd",	{ MaskG, MaskR }, 0 },
+    { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
+    { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
   },
   {
     /* VEX_W_0FAE_R_2_M_0 */
@@ -11488,23 +11547,23 @@ static const struct dis386 vex_w_table[][2] = {
   },
   {
     /* VEX_W_0F3A30_P_2_LEN_0 */
-    { "kshiftrb",	{ MaskG, MaskR, Ib }, 0 },
-    { "kshiftrw",	{ MaskG, MaskR, Ib }, 0 },
+    { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
+    { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
   },
   {
     /* VEX_W_0F3A31_P_2_LEN_0 */
-    { "kshiftrd",	{ MaskG, MaskR, Ib }, 0 },
-    { "kshiftrq",	{ MaskG, MaskR, Ib }, 0 },
+    { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
+    { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
   },
   {
     /* VEX_W_0F3A32_P_2_LEN_0 */
-    { "kshiftlb",	{ MaskG, MaskR, Ib }, 0 },
-    { "kshiftlw",	{ MaskG, MaskR, Ib }, 0 },
+    { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
+    { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
   },
   {
     /* VEX_W_0F3A33_P_2_LEN_0 */
-    { "kshiftld",	{ MaskG, MaskR, Ib }, 0 },
-    { "kshiftlq",	{ MaskG, MaskR, Ib }, 0 },
+    { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
+    { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
   },
   {
     /* VEX_W_0F3A38_P_2 */
@@ -11903,6 +11962,161 @@ static const struct dis386 mod_table[][2] = {
     { VEX_W_TABLE (VEX_W_0F2B_M_0) },
   },
   {
+    /* MOD_VEX_W_0_0F41_P_0_LEN_1 */
+    { Bad_Opcode },
+    { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_1_0F41_P_0_LEN_1 */
+    { Bad_Opcode },
+    { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_0_0F41_P_2_LEN_1 */
+    { Bad_Opcode },
+    { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_1_0F41_P_2_LEN_1 */
+    { Bad_Opcode },
+    { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_0_0F42_P_0_LEN_1 */
+    { Bad_Opcode },
+    { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_1_0F42_P_0_LEN_1 */
+    { Bad_Opcode },
+    { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_0_0F42_P_2_LEN_1 */
+    { Bad_Opcode },
+    { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_1_0F42_P_2_LEN_1 */
+    { Bad_Opcode },
+    { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_0_0F44_P_0_LEN_0 */
+    { Bad_Opcode },
+    { "knotw",          { MaskG, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_1_0F44_P_0_LEN_0 */
+    { Bad_Opcode },
+    { "knotq",          { MaskG, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_0_0F44_P_2_LEN_0 */
+    { Bad_Opcode },
+    { "knotb",          { MaskG, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_1_0F44_P_2_LEN_0 */
+    { Bad_Opcode },
+    { "knotd",          { MaskG, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_0_0F45_P_0_LEN_1 */
+    { Bad_Opcode },
+    { "korw",       { MaskG, MaskVex, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_1_0F45_P_0_LEN_1 */
+    { Bad_Opcode },
+    { "korq",       { MaskG, MaskVex, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_0_0F45_P_2_LEN_1 */
+    { Bad_Opcode },
+    { "korb",       { MaskG, MaskVex, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_1_0F45_P_2_LEN_1 */
+    { Bad_Opcode },
+    { "kord",       { MaskG, MaskVex, MaskR }, 0 },
+  },
+ {
+    /* MOD_VEX_W_0_0F46_P_0_LEN_1 */
+    { Bad_Opcode },
+    { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_1_0F46_P_0_LEN_1 */
+    { Bad_Opcode },
+    { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_0_0F46_P_2_LEN_1 */
+    { Bad_Opcode },
+    { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_1_0F46_P_2_LEN_1 */
+    { Bad_Opcode },
+    { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_0_0F47_P_0_LEN_1 */
+    { Bad_Opcode },
+    { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_1_0F47_P_0_LEN_1 */
+    { Bad_Opcode },
+    { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_0_0F47_P_2_LEN_1 */
+    { Bad_Opcode },
+    { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_1_0F47_P_2_LEN_1 */
+    { Bad_Opcode },
+    { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
+    { Bad_Opcode },
+    { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
+    { Bad_Opcode },
+    { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
+    { Bad_Opcode },
+    { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
+    { Bad_Opcode },
+    { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
+    { Bad_Opcode },
+    { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
+    { Bad_Opcode },
+    { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
+    { Bad_Opcode },
+    { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
+  },
+  {
     /* MOD_VEX_0F50 */
     { Bad_Opcode },
     { VEX_W_TABLE (VEX_W_0F50_M_0) },
@@ -11958,6 +12172,106 @@ static const struct dis386 mod_table[][2] = {
     { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
   },
   {
+    /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
+    { "kmovw",		{ Ew, MaskG }, 0 },
+    { Bad_Opcode },
+  },
+  {
+    /* MOD_VEX_W_0_0F91_P_0_LEN_0 */
+    { "kmovq",		{ Eq, MaskG }, 0 },
+    { Bad_Opcode },
+  },
+  {
+    /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
+    { "kmovb",		{ Eb, MaskG }, 0 },
+    { Bad_Opcode },
+  },
+  {
+    /* MOD_VEX_W_0_0F91_P_2_LEN_0 */
+    { "kmovd",		{ Ed, MaskG }, 0 },
+    { Bad_Opcode },
+  },
+  {
+    /* MOD_VEX_W_0_0F92_P_0_LEN_0 */
+    { Bad_Opcode },
+    { "kmovw",		{ MaskG, Rdq }, 0 },
+  },
+  {
+    /* MOD_VEX_W_0_0F92_P_2_LEN_0 */
+    { Bad_Opcode },
+    { "kmovb",		{ MaskG, Rdq }, 0 },
+  },
+  {
+    /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
+    { Bad_Opcode },
+    { "kmovd",		{ MaskG, Rdq }, 0 },
+  },
+  {
+    /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
+    { Bad_Opcode },
+    { "kmovq",		{ MaskG, Rdq }, 0 },
+  },
+  {
+    /* MOD_VEX_W_0_0F93_P_0_LEN_0 */
+    { Bad_Opcode },
+    { "kmovw",		{ Gdq, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_0_0F93_P_2_LEN_0 */
+    { Bad_Opcode },
+    { "kmovb",		{ Gdq, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
+    { Bad_Opcode },
+    { "kmovd",		{ Gdq, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
+    { Bad_Opcode },
+    { "kmovq",		{ Gdq, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_0_0F98_P_0_LEN_0 */
+    { Bad_Opcode },
+    { "kortestw", { MaskG, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_1_0F98_P_0_LEN_0 */
+    { Bad_Opcode },
+    { "kortestq", { MaskG, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_0_0F98_P_2_LEN_0 */
+    { Bad_Opcode },
+    { "kortestb", { MaskG, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_1_0F98_P_2_LEN_0 */
+    { Bad_Opcode },
+    { "kortestd", { MaskG, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_0_0F99_P_0_LEN_0 */
+    { Bad_Opcode },
+    { "ktestw", { MaskG, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_1_0F99_P_0_LEN_0 */
+    { Bad_Opcode },
+    { "ktestq", { MaskG, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_0_0F99_P_2_LEN_0 */
+    { Bad_Opcode },
+    { "ktestb", { MaskG, MaskR }, 0 },
+  },
+  {
+    /* MOD_VEX_W_1_0F99_P_2_LEN_0 */
+    { Bad_Opcode },
+    { "ktestd", { MaskG, MaskR }, 0 },
+  },
+  {
     /* MOD_VEX_0FAE_REG_2 */
     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) },
   },
@@ -12014,6 +12328,46 @@ static const struct dis386 mod_table[][2] = {
     /* MOD_VEX_0F388E_PREFIX_2 */
     { "vpmaskmov%LW",	{ Mx, Vex, XM }, 0 },
   },
+  {
+    /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
+    { Bad_Opcode },
+    { "kshiftrb",       { MaskG, MaskR, Ib }, 0 },
+  },
+  {
+    /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
+    { Bad_Opcode },
+    { "kshiftrw",       { MaskG, MaskR, Ib }, 0 },
+  },
+  {
+    /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
+    { Bad_Opcode },
+    { "kshiftrd",       { MaskG, MaskR, Ib }, 0 },
+  },
+  {
+    /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
+    { Bad_Opcode },
+    { "kshiftrq",       { MaskG, MaskR, Ib }, 0 },
+  },
+  {
+    /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
+    { Bad_Opcode },
+    { "kshiftlb",       { MaskG, MaskR, Ib }, 0 },
+  },
+  {
+    /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
+    { Bad_Opcode },
+    { "kshiftlw",       { MaskG, MaskR, Ib }, 0 },
+  },
+  {
+    /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
+    { Bad_Opcode },
+    { "kshiftld",       { MaskG, MaskR, Ib }, 0 },
+  },
+  {
+    /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
+    { Bad_Opcode },
+    { "kshiftlq",       { MaskG, MaskR, Ib }, 0 },
+  },
 #define NEED_MOD_TABLE
 #include "i386-dis-evex.h"
 #undef NEED_MOD_TABLE
-- 
1.8.3.1


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