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Re: [PATCH] x86/Intel: accept mandated operand order for vcvt{,u}si2s{d,s}

Hello Jan,
On 26 May 09:04, Jan Beulich wrote:
> >>> On 25.05.15 at 16:55, <> wrote:
> >> Thoughts?
> > Wanted to mention couple of points:
> >   1. I agree w/ HJ: SDM is not a source of syntax
> >   2. We have two product already released: ICC (2 version at the moment) and 
> > GCC
> >   (4.9 and 5) which use existing syntax for emitting those insns
> > 
> > Said that, I don't see any reason to introduce (not replace) alternative 
> > operand order.
> I'm confused - did you perhaps mean to say "I don't see any reason
> not to introduce ..."?
No, this is what I think.  I think that having two variants of operands order
is not good idea.

We have those products which use AVX-512:
  1. ICC (couple of versions):         uses {vreg, vreg, {RC}, GPR} order.
  2. Binutils (couple of versions):    Same.
  3. GCC (4.9, 5):                     Same.
  4. NASM (I tried last ver, 2.11.08): Same.

MASM doesn't support AVX-512 and cannot be source of Intel syntax,
but I'll try to inform them about current variant.

Finally, (I promise, I repeat it last time) as far as SDM is not a source of Intel syntax,
I see no reason to allow another order. IMO, such addition might
even increase confusion about this non-trivial stuff.

Thanks, K

> Jan

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