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Re: [PATCH] A few ppc assembler fixes
- From: Peter Bergner <bergner at vnet dot ibm dot com>
- To: Jan Beulich <JBeulich at suse dot com>
- Cc: Hal Finkel <hfinkel at anl dot gov>, Alan Modra <amodra at gmail dot com>, BillSchmidt <wschmidt at linux dot vnet dot ibm dot com>, Binutils <binutils at sourceware dot org>
- Date: Thu, 23 Apr 2015 08:43:04 -0500
- Subject: Re: [PATCH] A few ppc assembler fixes
- Authentication-results: sourceware.org; auth=none
- References: <1429746727 dot 21947 dot 60 dot camel at otta> <5538B04A0200007800074F57 at mail dot emea dot novell dot com> <1429791153 dot 21947 dot 81 dot camel at otta> <553909670200007800075251 at mail dot emea dot novell dot com>
On Thu, 2015-04-23 at 14:01 +0100, Jan Beulich wrote:
> Oh, this wasn't about the operand ordering part, but the part
> removing or altering the POWER<n> attribute on some insns.
Ahhh, ok. In the waitrsv/waitimpl case, these were going to be added
to ISA 2.06 so I added them to binutils, but they ended up being
yanked from the released ISA at the last second without my knowledge.
Our POWER server chips ended up not implementing them at all, but the
E500MC did. The lbarx/lharx/stbcx./sthcx. instructions were added to
ISA 2.06, but were marked as "Phased-In". This means any ISA 2.06
complaint cpu may or may-not implement the given instruction.
Back to your point, I think as a user myself, I'd rather have the
assembler tell me when I'm attempting to use an instruction that
isn't implemented on the cpu I'm targetting, than hitting a SIGILL
at runtime. Just my $0.02 though.