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[PATCH] x86/Intel: accept mandated operand order for vcvt{,u}si2s{d,s}

From: "Jan Beulich" <JBeulich at suse dot com>
To: <binutils at sourceware dot org>
Cc: "H.J. Lu" <hjl dot tools at gmail dot com>
Date: Thu, 16 Apr 2015 15:16:35 +0100
Subject: [PATCH] x86/Intel: accept mandated operand order for vcvt{,u}si2s{d,s}
Authentication-results: sourceware.org; auth=none
As pointed out before, the documentation mandates the rounding mode to
follow the GPR, so gas should accept such input. As the brojen code got
released already we sadly will need to continue to also accept the
badly ordered operands.

gas/testsuite/
2015-04-16  Jan Beulich  <jbeulich@suse.com>

	* gas/i386/avx512f-intel.d: Adjust expectations on operand order.
	* gas/i386/evex-lig256-intel.d: Likewise.
	* gas/i386/evex-lig512-intel.d: Likewise.
	* gas/i386/x86-64-avx512f-intel.d: Likewise.
	* gas/i386/x86-64-evex-lig256-intel.d: Likewise.
	* gas/i386/x86-64-evex-lig512-intel.d: Likewise.

opcodes/
2015-04-16  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
	* i386-tbl.h: Regenerate.

--- 2015-04-16/gas/testsuite/gas/i386/avx512f.s
+++ 2015-04-16/gas/testsuite/gas/i386/avx512f.s
@@ -9904,14 +9904,14 @@ _start:
 	vcvtsd2ss	xmm6{k7}, xmm5, QWORD PTR [edx-1032]	 # AVX512F
 
 
-	vcvtsi2ss	xmm6, xmm5, {rn-sae}, eax	 # AVX512F
-	vcvtsi2ss	xmm6, xmm5, {ru-sae}, eax	 # AVX512F
-	vcvtsi2ss	xmm6, xmm5, {rd-sae}, eax	 # AVX512F
-	vcvtsi2ss	xmm6, xmm5, {rz-sae}, eax	 # AVX512F
-	vcvtsi2ss	xmm6, xmm5, {rn-sae}, ebp	 # AVX512F
-	vcvtsi2ss	xmm6, xmm5, {ru-sae}, ebp	 # AVX512F
-	vcvtsi2ss	xmm6, xmm5, {rd-sae}, ebp	 # AVX512F
-	vcvtsi2ss	xmm6, xmm5, {rz-sae}, ebp	 # AVX512F
+	vcvtsi2ss	xmm6, xmm5, eax, {rn-sae}	 # AVX512F
+	vcvtsi2ss	xmm6, xmm5, eax, {ru-sae}	 # AVX512F
+	vcvtsi2ss	xmm6, xmm5, eax, {rd-sae}	 # AVX512F
+	vcvtsi2ss	xmm6, xmm5, eax, {rz-sae}	 # AVX512F
+	vcvtsi2ss	xmm6, xmm5, ebp, {rn-sae}	 # AVX512F
+	vcvtsi2ss	xmm6, xmm5, ebp, {ru-sae}	 # AVX512F
+	vcvtsi2ss	xmm6, xmm5, ebp, {rd-sae}	 # AVX512F
+	vcvtsi2ss	xmm6, xmm5, ebp, {rz-sae}	 # AVX512F
 
 	vcvtss2sd	xmm6{k7}, xmm5, xmm4	 # AVX512F
 	vcvtss2sd	xmm6{k7}{z}, xmm5, xmm4	 # AVX512F
@@ -13704,15 +13704,15 @@ _start:
 	vcvtusi2sd	xmm6, xmm5, DWORD PTR [edx-516]	 # AVX512F
 
 	vcvtusi2ss	xmm6, xmm5, eax	 # AVX512F
-	vcvtusi2ss	xmm6, xmm5, {rn-sae}, eax	 # AVX512F
-	vcvtusi2ss	xmm6, xmm5, {ru-sae}, eax	 # AVX512F
-	vcvtusi2ss	xmm6, xmm5, {rd-sae}, eax	 # AVX512F
-	vcvtusi2ss	xmm6, xmm5, {rz-sae}, eax	 # AVX512F
+	vcvtusi2ss	xmm6, xmm5, eax, {rn-sae}	 # AVX512F
+	vcvtusi2ss	xmm6, xmm5, eax, {ru-sae}	 # AVX512F
+	vcvtusi2ss	xmm6, xmm5, eax, {rd-sae}	 # AVX512F
+	vcvtusi2ss	xmm6, xmm5, eax, {rz-sae}	 # AVX512F
 	vcvtusi2ss	xmm6, xmm5, ebp	 # AVX512F
-	vcvtusi2ss	xmm6, xmm5, {rn-sae}, ebp	 # AVX512F
-	vcvtusi2ss	xmm6, xmm5, {ru-sae}, ebp	 # AVX512F
-	vcvtusi2ss	xmm6, xmm5, {rd-sae}, ebp	 # AVX512F
-	vcvtusi2ss	xmm6, xmm5, {rz-sae}, ebp	 # AVX512F
+	vcvtusi2ss	xmm6, xmm5, ebp, {rn-sae}	 # AVX512F
+	vcvtusi2ss	xmm6, xmm5, ebp, {ru-sae}	 # AVX512F
+	vcvtusi2ss	xmm6, xmm5, ebp, {rd-sae}	 # AVX512F
+	vcvtusi2ss	xmm6, xmm5, ebp, {rz-sae}	 # AVX512F
 	vcvtusi2ss	xmm6, xmm5, DWORD PTR [ecx]	 # AVX512F
 	vcvtusi2ss	xmm6, xmm5, DWORD PTR [esp+esi*8-123456]	 # AVX512F
 	vcvtusi2ss	xmm6, xmm5, DWORD PTR [edx+508]	 # AVX512F Disp8
--- 2015-04-16/gas/testsuite/gas/i386/x86-64-avx512f.s
+++ 2015-04-16/gas/testsuite/gas/i386/x86-64-avx512f.s
@@ -10339,15 +10339,15 @@ _start:
 	vcvtsi2sd	xmm30, xmm29, DWORD PTR [rdx-516]	 # AVX512F
 
 	vcvtsi2sd	xmm30, xmm29, rax	 # AVX512F
-	vcvtsi2sd	xmm30, xmm29, {rn-sae}, rax	 # AVX512F
-	vcvtsi2sd	xmm30, xmm29, {ru-sae}, rax	 # AVX512F
-	vcvtsi2sd	xmm30, xmm29, {rd-sae}, rax	 # AVX512F
-	vcvtsi2sd	xmm30, xmm29, {rz-sae}, rax	 # AVX512F
+	vcvtsi2sd	xmm30, xmm29, rax, {rn-sae}	 # AVX512F
+	vcvtsi2sd	xmm30, xmm29, rax, {ru-sae}	 # AVX512F
+	vcvtsi2sd	xmm30, xmm29, rax, {rd-sae}	 # AVX512F
+	vcvtsi2sd	xmm30, xmm29, rax, {rz-sae}	 # AVX512F
 	vcvtsi2sd	xmm30, xmm29, r8	 # AVX512F
-	vcvtsi2sd	xmm30, xmm29, {rn-sae}, r8	 # AVX512F
-	vcvtsi2sd	xmm30, xmm29, {ru-sae}, r8	 # AVX512F
-	vcvtsi2sd	xmm30, xmm29, {rd-sae}, r8	 # AVX512F
-	vcvtsi2sd	xmm30, xmm29, {rz-sae}, r8	 # AVX512F
+	vcvtsi2sd	xmm30, xmm29, r8, {rn-sae}	 # AVX512F
+	vcvtsi2sd	xmm30, xmm29, r8, {ru-sae}	 # AVX512F
+	vcvtsi2sd	xmm30, xmm29, r8, {rd-sae}	 # AVX512F
+	vcvtsi2sd	xmm30, xmm29, r8, {rz-sae}	 # AVX512F
 	vcvtsi2sd	xmm30, xmm29, QWORD PTR [rcx]	 # AVX512F
 	vcvtsi2sd	xmm30, xmm29, QWORD PTR [rax+r14*8+0x1234]	 # AVX512F
 	vcvtsi2sd	xmm30, xmm29, QWORD PTR [rdx+1016]	 # AVX512F Disp8
@@ -10356,20 +10356,20 @@ _start:
 	vcvtsi2sd	xmm30, xmm29, QWORD PTR [rdx-1032]	 # AVX512F
 
 	vcvtsi2ss	xmm30, xmm29, eax	 # AVX512F
-	vcvtsi2ss	xmm30, xmm29, {rn-sae}, eax	 # AVX512F
-	vcvtsi2ss	xmm30, xmm29, {ru-sae}, eax	 # AVX512F
-	vcvtsi2ss	xmm30, xmm29, {rd-sae}, eax	 # AVX512F
-	vcvtsi2ss	xmm30, xmm29, {rz-sae}, eax	 # AVX512F
+	vcvtsi2ss	xmm30, xmm29, eax, {rn-sae}	 # AVX512F
+	vcvtsi2ss	xmm30, xmm29, eax, {ru-sae}	 # AVX512F
+	vcvtsi2ss	xmm30, xmm29, eax, {rd-sae}	 # AVX512F
+	vcvtsi2ss	xmm30, xmm29, eax, {rz-sae}	 # AVX512F
 	vcvtsi2ss	xmm30, xmm29, ebp	 # AVX512F
-	vcvtsi2ss	xmm30, xmm29, {rn-sae}, ebp	 # AVX512F
-	vcvtsi2ss	xmm30, xmm29, {ru-sae}, ebp	 # AVX512F
-	vcvtsi2ss	xmm30, xmm29, {rd-sae}, ebp	 # AVX512F
-	vcvtsi2ss	xmm30, xmm29, {rz-sae}, ebp	 # AVX512F
+	vcvtsi2ss	xmm30, xmm29, ebp, {rn-sae}	 # AVX512F
+	vcvtsi2ss	xmm30, xmm29, ebp, {ru-sae}	 # AVX512F
+	vcvtsi2ss	xmm30, xmm29, ebp, {rd-sae}	 # AVX512F
+	vcvtsi2ss	xmm30, xmm29, ebp, {rz-sae}	 # AVX512F
 	vcvtsi2ss	xmm30, xmm29, r13d	 # AVX512F
-	vcvtsi2ss	xmm30, xmm29, {rn-sae}, r13d	 # AVX512F
-	vcvtsi2ss	xmm30, xmm29, {ru-sae}, r13d	 # AVX512F
-	vcvtsi2ss	xmm30, xmm29, {rd-sae}, r13d	 # AVX512F
-	vcvtsi2ss	xmm30, xmm29, {rz-sae}, r13d	 # AVX512F
+	vcvtsi2ss	xmm30, xmm29, r13d, {rn-sae}	 # AVX512F
+	vcvtsi2ss	xmm30, xmm29, r13d, {ru-sae}	 # AVX512F
+	vcvtsi2ss	xmm30, xmm29, r13d, {rd-sae}	 # AVX512F
+	vcvtsi2ss	xmm30, xmm29, r13d, {rz-sae}	 # AVX512F
 	vcvtsi2ss	xmm30, xmm29, DWORD PTR [rcx]	 # AVX512F
 	vcvtsi2ss	xmm30, xmm29, DWORD PTR [rax+r14*8+0x1234]	 # AVX512F
 	vcvtsi2ss	xmm30, xmm29, DWORD PTR [rdx+508]	 # AVX512F Disp8
@@ -10378,15 +10378,15 @@ _start:
 	vcvtsi2ss	xmm30, xmm29, DWORD PTR [rdx-516]	 # AVX512F
 
 	vcvtsi2ss	xmm30, xmm29, rax	 # AVX512F
-	vcvtsi2ss	xmm30, xmm29, {rn-sae}, rax	 # AVX512F
-	vcvtsi2ss	xmm30, xmm29, {ru-sae}, rax	 # AVX512F
-	vcvtsi2ss	xmm30, xmm29, {rd-sae}, rax	 # AVX512F
-	vcvtsi2ss	xmm30, xmm29, {rz-sae}, rax	 # AVX512F
+	vcvtsi2ss	xmm30, xmm29, rax, {rn-sae}	 # AVX512F
+	vcvtsi2ss	xmm30, xmm29, rax, {ru-sae}	 # AVX512F
+	vcvtsi2ss	xmm30, xmm29, rax, {rd-sae}	 # AVX512F
+	vcvtsi2ss	xmm30, xmm29, rax, {rz-sae}	 # AVX512F
 	vcvtsi2ss	xmm30, xmm29, r8	 # AVX512F
-	vcvtsi2ss	xmm30, xmm29, {rn-sae}, r8	 # AVX512F
-	vcvtsi2ss	xmm30, xmm29, {ru-sae}, r8	 # AVX512F
-	vcvtsi2ss	xmm30, xmm29, {rd-sae}, r8	 # AVX512F
-	vcvtsi2ss	xmm30, xmm29, {rz-sae}, r8	 # AVX512F
+	vcvtsi2ss	xmm30, xmm29, r8, {rn-sae}	 # AVX512F
+	vcvtsi2ss	xmm30, xmm29, r8, {ru-sae}	 # AVX512F
+	vcvtsi2ss	xmm30, xmm29, r8, {rd-sae}	 # AVX512F
+	vcvtsi2ss	xmm30, xmm29, r8, {rz-sae}	 # AVX512F
 	vcvtsi2ss	xmm30, xmm29, QWORD PTR [rcx]	 # AVX512F
 	vcvtsi2ss	xmm30, xmm29, QWORD PTR [rax+r14*8+0x1234]	 # AVX512F
 	vcvtsi2ss	xmm30, xmm29, QWORD PTR [rdx+1016]	 # AVX512F Disp8
@@ -14409,15 +14409,15 @@ _start:
 	vcvtusi2sd	xmm30, xmm29, DWORD PTR [rdx-516]	 # AVX512F
 
 	vcvtusi2sd	xmm30, xmm29, rax	 # AVX512F
-	vcvtusi2sd	xmm30, xmm29, {rn-sae}, rax	 # AVX512F
-	vcvtusi2sd	xmm30, xmm29, {ru-sae}, rax	 # AVX512F
-	vcvtusi2sd	xmm30, xmm29, {rd-sae}, rax	 # AVX512F
-	vcvtusi2sd	xmm30, xmm29, {rz-sae}, rax	 # AVX512F
+	vcvtusi2sd	xmm30, xmm29, rax, {rn-sae}	 # AVX512F
+	vcvtusi2sd	xmm30, xmm29, rax, {ru-sae}	 # AVX512F
+	vcvtusi2sd	xmm30, xmm29, rax, {rd-sae}	 # AVX512F
+	vcvtusi2sd	xmm30, xmm29, rax, {rz-sae}	 # AVX512F
 	vcvtusi2sd	xmm30, xmm29, r8	 # AVX512F
-	vcvtusi2sd	xmm30, xmm29, {rn-sae}, r8	 # AVX512F
-	vcvtusi2sd	xmm30, xmm29, {ru-sae}, r8	 # AVX512F
-	vcvtusi2sd	xmm30, xmm29, {rd-sae}, r8	 # AVX512F
-	vcvtusi2sd	xmm30, xmm29, {rz-sae}, r8	 # AVX512F
+	vcvtusi2sd	xmm30, xmm29, r8, {rn-sae}	 # AVX512F
+	vcvtusi2sd	xmm30, xmm29, r8, {ru-sae}	 # AVX512F
+	vcvtusi2sd	xmm30, xmm29, r8, {rd-sae}	 # AVX512F
+	vcvtusi2sd	xmm30, xmm29, r8, {rz-sae}	 # AVX512F
 	vcvtusi2sd	xmm30, xmm29, QWORD PTR [rcx]	 # AVX512F
 	vcvtusi2sd	xmm30, xmm29, QWORD PTR [rax+r14*8+0x1234]	 # AVX512F
 	vcvtusi2sd	xmm30, xmm29, QWORD PTR [rdx+1016]	 # AVX512F Disp8
@@ -14426,20 +14426,20 @@ _start:
 	vcvtusi2sd	xmm30, xmm29, QWORD PTR [rdx-1032]	 # AVX512F
 
 	vcvtusi2ss	xmm30, xmm29, eax	 # AVX512F
-	vcvtusi2ss	xmm30, xmm29, {rn-sae}, eax	 # AVX512F
-	vcvtusi2ss	xmm30, xmm29, {ru-sae}, eax	 # AVX512F
-	vcvtusi2ss	xmm30, xmm29, {rd-sae}, eax	 # AVX512F
-	vcvtusi2ss	xmm30, xmm29, {rz-sae}, eax	 # AVX512F
+	vcvtusi2ss	xmm30, xmm29, eax, {rn-sae}	 # AVX512F
+	vcvtusi2ss	xmm30, xmm29, eax, {ru-sae}	 # AVX512F
+	vcvtusi2ss	xmm30, xmm29, eax, {rd-sae}	 # AVX512F
+	vcvtusi2ss	xmm30, xmm29, eax, {rz-sae}	 # AVX512F
 	vcvtusi2ss	xmm30, xmm29, ebp	 # AVX512F
-	vcvtusi2ss	xmm30, xmm29, {rn-sae}, ebp	 # AVX512F
-	vcvtusi2ss	xmm30, xmm29, {ru-sae}, ebp	 # AVX512F
-	vcvtusi2ss	xmm30, xmm29, {rd-sae}, ebp	 # AVX512F
-	vcvtusi2ss	xmm30, xmm29, {rz-sae}, ebp	 # AVX512F
+	vcvtusi2ss	xmm30, xmm29, ebp, {rn-sae}	 # AVX512F
+	vcvtusi2ss	xmm30, xmm29, ebp, {ru-sae}	 # AVX512F
+	vcvtusi2ss	xmm30, xmm29, ebp, {rd-sae}	 # AVX512F
+	vcvtusi2ss	xmm30, xmm29, ebp, {rz-sae}	 # AVX512F
 	vcvtusi2ss	xmm30, xmm29, r13d	 # AVX512F
-	vcvtusi2ss	xmm30, xmm29, {rn-sae}, r13d	 # AVX512F
-	vcvtusi2ss	xmm30, xmm29, {ru-sae}, r13d	 # AVX512F
-	vcvtusi2ss	xmm30, xmm29, {rd-sae}, r13d	 # AVX512F
-	vcvtusi2ss	xmm30, xmm29, {rz-sae}, r13d	 # AVX512F
+	vcvtusi2ss	xmm30, xmm29, r13d, {rn-sae}	 # AVX512F
+	vcvtusi2ss	xmm30, xmm29, r13d, {ru-sae}	 # AVX512F
+	vcvtusi2ss	xmm30, xmm29, r13d, {rd-sae}	 # AVX512F
+	vcvtusi2ss	xmm30, xmm29, r13d, {rz-sae}	 # AVX512F
 	vcvtusi2ss	xmm30, xmm29, DWORD PTR [rcx]	 # AVX512F
 	vcvtusi2ss	xmm30, xmm29, DWORD PTR [rax+r14*8+0x1234]	 # AVX512F
 	vcvtusi2ss	xmm30, xmm29, DWORD PTR [rdx+508]	 # AVX512F Disp8
@@ -14448,15 +14448,15 @@ _start:
 	vcvtusi2ss	xmm30, xmm29, DWORD PTR [rdx-516]	 # AVX512F
 
 	vcvtusi2ss	xmm30, xmm29, rax	 # AVX512F
-	vcvtusi2ss	xmm30, xmm29, {rn-sae}, rax	 # AVX512F
-	vcvtusi2ss	xmm30, xmm29, {ru-sae}, rax	 # AVX512F
-	vcvtusi2ss	xmm30, xmm29, {rd-sae}, rax	 # AVX512F
-	vcvtusi2ss	xmm30, xmm29, {rz-sae}, rax	 # AVX512F
+	vcvtusi2ss	xmm30, xmm29, rax, {rn-sae}	 # AVX512F
+	vcvtusi2ss	xmm30, xmm29, rax, {ru-sae}	 # AVX512F
+	vcvtusi2ss	xmm30, xmm29, rax, {rd-sae}	 # AVX512F
+	vcvtusi2ss	xmm30, xmm29, rax, {rz-sae}	 # AVX512F
 	vcvtusi2ss	xmm30, xmm29, r8	 # AVX512F
-	vcvtusi2ss	xmm30, xmm29, {rn-sae}, r8	 # AVX512F
-	vcvtusi2ss	xmm30, xmm29, {ru-sae}, r8	 # AVX512F
-	vcvtusi2ss	xmm30, xmm29, {rd-sae}, r8	 # AVX512F
-	vcvtusi2ss	xmm30, xmm29, {rz-sae}, r8	 # AVX512F
+	vcvtusi2ss	xmm30, xmm29, r8, {rn-sae}	 # AVX512F
+	vcvtusi2ss	xmm30, xmm29, r8, {ru-sae}	 # AVX512F
+	vcvtusi2ss	xmm30, xmm29, r8, {rd-sae}	 # AVX512F
+	vcvtusi2ss	xmm30, xmm29, r8, {rz-sae}	 # AVX512F
 	vcvtusi2ss	xmm30, xmm29, QWORD PTR [rcx]	 # AVX512F
 	vcvtusi2ss	xmm30, xmm29, QWORD PTR [rax+r14*8+0x1234]	 # AVX512F
 	vcvtusi2ss	xmm30, xmm29, QWORD PTR [rdx+1016]	 # AVX512F Disp8
--- 2015-04-16/opcodes/i386-opc.tbl
+++ 2015-04-16/opcodes/i386-opc.tbl
@@ -3648,18 +3648,24 @@ vcvtsd2ss, 4, 0xF25A, None, 1, CpuAVX512
 vcvtsi2sd, 3, 0xF22A, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
 vcvtsi2sd, 3, 0xF22A, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
 vcvtsi2sd, 4, 0xF22A, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|StaticRounding|SAE, { Reg64, Imm8, RegXMM, RegXMM }
+vcvtsi2sd, 4, 0xF22A, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg64, RegXMM, RegXMM }
 vcvtusi2sd, 3, 0xF27B, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
 vcvtusi2sd, 3, 0xF27B, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
 vcvtusi2sd, 4, 0xF27B, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|StaticRounding|SAE, { Reg64, Imm8, RegXMM, RegXMM }
+vcvtusi2sd, 4, 0xF27B, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg64, RegXMM, RegXMM }
 
 vcvtsi2ss, 3, 0xF32A, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
 vcvtsi2ss, 4, 0xF32A, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Reg32, Imm8, RegXMM, RegXMM }
+vcvtsi2ss, 4, 0xF32A, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg32, RegXMM, RegXMM }
 vcvtsi2ss, 3, 0xF32A, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
 vcvtsi2ss, 4, 0xF32A, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|StaticRounding|SAE, { Reg64, Imm8, RegXMM, RegXMM }
+vcvtsi2ss, 4, 0xF32A, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg64, RegXMM, RegXMM }
 vcvtusi2ss, 3, 0xF37B, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
 vcvtusi2ss, 4, 0xF37B, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { Reg32, Imm8, RegXMM, RegXMM }
+vcvtusi2ss, 4, 0xF37B, None, 1, CpuAVX512F, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg32, RegXMM, RegXMM }
 vcvtusi2ss, 3, 0xF37B, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
 vcvtusi2ss, 4, 0xF37B, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|StaticRounding|SAE, { Reg64, Imm8, RegXMM, RegXMM }
+vcvtusi2ss, 4, 0xF37B, None, 1, CpuAVX512F|Cpu64, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|VexW=2|VecESize=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Imm8, Reg64, RegXMM, RegXMM }
 
 vcvtss2sd, 3, 0xF35A, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Disp8MemShift=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
 vcvtss2sd, 4, 0xF35A, None, 1, CpuAVX512F, Modrm|EVex=4|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM, RegXMM, RegXMM }
Attachment: binutils-master-x86-AVX512F-scalar-convert-asm.patch
Description: Text document
Follow-Ups:
- Re: [PATCH] x86/Intel: accept mandated operand order for vcvt{,u}si2s{d,s}
  - From: H.J. Lu
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