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RE: [PATCH] add znver1 processor.
- From: "Gopalasubramanian, Ganesh" <Ganesh dot Gopalasubramanian at amd dot com>
- To: "H.J. Lu" <hjl dot tools at gmail dot com>
- Cc: "binutils at sourceware dot org" <binutils at sourceware dot org>
- Date: Tue, 10 Mar 2015 16:29:07 +0000
- Subject: RE: [PATCH] add znver1 processor.
- Authentication-results: sourceware.org; auth=none
- Authentication-results: spf=none (sender IP is 126.96.36.199) smtp dot mailfrom=Ganesh dot Gopalasubramanian at amd dot com; gmail.com; dkim=none (message not signed) header.d=none;
- References: <EB4625145972F94C9680D8CADD65161578F54FA4 at SATLEXDAG02 dot amd dot com> <CAMe9rOpDjxwCeuU1nXN4C9VvKr4h_tiWqyfy=QqOijCJZqpL+Q at mail dot gmail dot com>
> It is OK.
I don't have write access (I donât have write after approval access too).
Can you please commit these changes on my behalf and backport it to the latest release of GNU binutils is 2.25?
From: H.J. Lu [mailto:firstname.lastname@example.org]
Sent: Tuesday, March 10, 2015 4:14 PM
To: Gopalasubramanian, Ganesh
Subject: Re: [PATCH] add znver1 processor.
On Tue, Mar 10, 2015 at 12:49 AM, Gopalasubramanian, Ganesh <Ganesh.Gopalasubramanian@amd.com> wrote:
> Attached patch adds the following.
> * New AMD znver1 processor. The architecture has the below features
> * TBM, FMA4, XOP, LWP: ISAs are not supported.
> * SMAP, RDSEED, SHA, XSAVEC, XSAVES, CLFLUSHOPT, ADCX: ISAs are supported.
> * New CLZERO instruction support.
> * clzero has opcode "0F 01 FC".
> * clzero gets enabled with CPUID, 8000_0008, EBX =1.
> * clzero instruction zero's out the 64 byte cache line
> specified in rax. Bits 5:0 of rAX are ignored
> I have added two new arch test files.
> 1. arch-13.s: Lists out the new ISAs that are supported and checks it against the march option.
> 2. x86-64-arch-3.s: The 64-bit version of the test.
> It passes make check on x86-64. Okay to commit?