This is the mail archive of the mailing list for the binutils project.

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

RE: [PATCH] add znver1 processor.

> It is OK.
> Thanks.

I don't have write access (I donât have write after approval access too).
Can you please commit these changes on my behalf and backport it to the latest release of GNU binutils is 2.25?

Thanking you

-----Original Message-----
From: H.J. Lu [] 
Sent: Tuesday, March 10, 2015 4:14 PM
To: Gopalasubramanian, Ganesh
Subject: Re: [PATCH] add znver1 processor.

On Tue, Mar 10, 2015 at 12:49 AM, Gopalasubramanian, Ganesh <> wrote:
> Attached patch adds the following.
>         * New AMD znver1 processor. The architecture has the below features
>                 * TBM, FMA4, XOP, LWP: ISAs are not supported.
>                 * SMAP, RDSEED, SHA, XSAVEC, XSAVES, CLFLUSHOPT, ADCX: ISAs are supported.
>         * New CLZERO instruction support.
>                 * clzero has opcode "0F 01 FC".
>                 * clzero gets enabled with CPUID, 8000_0008, EBX[0] =1.
>                 * clzero instruction zero's out the 64 byte cache line 
> specified in rax. Bits 5:0 of rAX are ignored
> I have added two new arch test files.
>         1. arch-13.s: Lists out the new ISAs that are supported and checks it against the march option.
>         2. x86-64-arch-3.s: The 64-bit version of the test.
> It passes make check on x86-64. Okay to commit?

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]