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Re: [PATCH] Add XPA ASE and MIPS R5 microMIPS support

Andrew Bennett <> writes:
> +{"mfhc0",		"t,G",		0x000000f4, 0xfc00ffff,	WR_1|RD_C0,		0,		0,		XPA,	0 },
> +{"mfhc0",		"t,G,H",	0x000000f4, 0xfc00c7ff,	WR_1|RD_C0,		0,		0,		XPA,	0 },
> +{"mfhgc0",		"t,G",		0x000004f4, 0xfc00ffff,	WR_1|RD_C0,		0,		0,		IVIRT|XPA,	0 },
> +{"mfhgc0",		"t,G,H",	0x000004f4, 0xfc00c7ff,	WR_1|RD_C0,		0,		0,		IVIRT|XPA,	0 },

Genuine question: is this really "IVIRT or XPA" or "IVIRT and XPA"?
Would be good to have virt in the test if it's relevant.

Looks good otherwise.  Until now it's been safe to use the r2 flag for
r3 and r5, since no instructions have been conditional on r3 or r5 alone.
This patch is the first to add a true r5 (microMIPS) instruction.

Is the idea that we'll just rely on .mips.abiflags to enforce r5ness
from now on?  Even though that's more flexible long-term, maybe it
would make sense to have an r5 EF_* anyway, so that there's no gap
between R2 and R6 (which both have flags).


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