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[PATCH] MIPS: Fix constraint issues with the R6 beqc and bnec instructions


Hi,

The encoding for the MIPS R6 beqc and bnec instructions firstly requires 
that the register number in the rs field is less than the rt field; and
secondly the rs and rt fields do not contain the zero register.  However,
the current mips operands for these instructions do not follow these constraints.  
The -u operand allows the zero register; and the -y operand allows the
rs and rt registers to be the same.  The following patch and ChangeLog updates 
these constraints so that they are correct.

Ok to commit?

Many thanks,



Andrew




opcodes/
    	* mips-opc.c (decode_mips_operand): Fix constraint issues
    	with -u and -y operands.


diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 0472b5b..07b3d04 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -48,11 +48,11 @@ decode_mips_operand (const char *p)
 	case 'd': SPECIAL (0, 0, REPEAT_DEST_REG);
 	case 's': SPECIAL (5, 21, NON_ZERO_REG);
 	case 't': SPECIAL (5, 16, NON_ZERO_REG);
-	case 'u': PREV_CHECK (5, 16, TRUE, FALSE, FALSE, TRUE);
+	case 'u': PREV_CHECK (5, 16, TRUE, FALSE, FALSE, FALSE);
 	case 'v': PREV_CHECK (5, 16, TRUE, TRUE, FALSE, FALSE);
 	case 'w': PREV_CHECK (5, 16, FALSE, TRUE, TRUE, TRUE);
 	case 'x': PREV_CHECK (5, 21, TRUE, FALSE, FALSE, TRUE);
-	case 'y': PREV_CHECK (5, 21, FALSE, TRUE, TRUE, FALSE);
+	case 'y': PREV_CHECK (5, 21, FALSE, TRUE, FALSE, FALSE);
 	case 'A': PCREL (19, 0, TRUE, 2, 2, FALSE, FALSE);
 	case 'B': PCREL (18, 0, TRUE, 3, 3, FALSE, FALSE);
 	}


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