diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index 89d51c1..1bc861e 100644
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -11700,6 +11700,7 @@ elf32_arm_merge_eabi_attributes (bfd *ibfd, bfd *obfd)
   static const int order_021[3] = {0, 2, 1};
   int i;
   bfd_boolean result = TRUE;
+  const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
 
   /* Skip the linker stubs file.  This preserves previous behavior
      of accepting unknown attributes in the first input file - but
@@ -11707,6 +11708,12 @@ elf32_arm_merge_eabi_attributes (bfd *ibfd, bfd *obfd)
   if (ibfd->flags & BFD_LINKER_CREATED)
     return TRUE;
 
+  /* Skip any input that hasn't attribute section.
+     This enables to link object files without attribute section with
+     any others.  */
+  if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
+    return TRUE;
+
   if (!elf_known_obj_attributes_proc (obfd)[0].i)
     {
       /* This is the first object.  Copy the attributes.  */
diff --git a/ld/testsuite/ld-arm/arm-elf.exp b/ld/testsuite/ld-arm/arm-elf.exp
index f971afc..d2ff8db 100644
--- a/ld/testsuite/ld-arm/arm-elf.exp
+++ b/ld/testsuite/ld-arm/arm-elf.exp
@@ -878,6 +878,7 @@ run_dump_test "attr-merge-vfp-6r"
 run_dump_test "attr-merge-vfp-7"
 run_dump_test "attr-merge-vfp-7r"
 run_dump_test "attr-merge-incompatible"
+run_dump_test "attr-merge-nosection-1"
 run_dump_test "unresolved-1"
 if { ![istarget "arm*-*-nacl*"] } {
     run_dump_test "unresolved-1-dyn"
diff --git a/ld/testsuite/ld-arm/attr-merge-nosection-1.d b/ld/testsuite/ld-arm/attr-merge-nosection-1.d
new file mode 100644
index 0000000..a2b8d73
--- /dev/null
+++ b/ld/testsuite/ld-arm/attr-merge-nosection-1.d
@@ -0,0 +1,18 @@
+#source: attr-merge-nosection-1a.s RUN_OBJCOPY
+#source: attr-merge-nosection-1b.s
+#as:
+#objcopy_objects: -R '.ARM.attributes'
+#ld:
+#readelf: -A
+# This test is only valid on ELF based ports.
+# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-M4"
+  Tag_CPU_arch: v7E-M
+  Tag_CPU_arch_profile: Microcontroller
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv4-D16
+  Tag_ABI_HardFP_use: SP only
+
diff --git a/ld/testsuite/ld-arm/attr-merge-nosection-1a.s b/ld/testsuite/ld-arm/attr-merge-nosection-1a.s
new file mode 100644
index 0000000..ab358e3
--- /dev/null
+++ b/ld/testsuite/ld-arm/attr-merge-nosection-1a.s
@@ -0,0 +1,10 @@
+	.cpu cortex-m0
+	.fpu softvfp
+	.syntax unified
+	.thumb
+	.text
+	.global foo
+	.thumb_func
+	.type foo, %function
+foo:
+	bx lr
diff --git a/ld/testsuite/ld-arm/attr-merge-nosection-1b.s b/ld/testsuite/ld-arm/attr-merge-nosection-1b.s
new file mode 100644
index 0000000..cd656bd
--- /dev/null
+++ b/ld/testsuite/ld-arm/attr-merge-nosection-1b.s
@@ -0,0 +1,10 @@
+        .syntax unified
+        .cpu cortex-m4
+        .fpu fpv4-sp-d16
+        .thumb
+        .text
+        .global _start
+        .thumb_func
+        .type   _start, %function
+_start:
+	bl foo