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Re: [PATCH][MIPS] Optionally disable odd-numbered single-precision registers

Matthew Fortune <> writes:
> This patch adds support for disabling the use of odd-numbered
> single-precision registers for arithmetic options. It aims
> to implement the restriction on loongson-3a where these registers
> cannot be used for single-precision operations (in FR=0/FP32 mode).
> We have also decided to limit the number of single-precision
> registers usable by default for generic MIPS architectures so that
> generic code can run on the loongson-3a. Targeting a specific
> architecture will however allow access to all registers by default.
> The corresponding (as yet un-committed) GCC patch is:
> After this patch is applied then pre-existing GCC compilers will
> end up with warnings from the assembler when building mips32 or
> mips32r2 code as the pre-existing compilers will use 32 single-
> precision registers. Is this acceptable?

Hmm, it sounds likely to surprise people.  Maybe this is one of
the few cases where GCC and GAS should have different defaults.
In the GCC case it's controlling whether the code uses odd
registers, so -mno-oddspreg is the safe choice.  But in the
GAS code it controls a warning, so -moddspreg is the safe choice.

Maybe we should define ISA_HAS_ODD_SINGLE_FPR so that it takes
the mips_opts.arch as well as the mips_opts.isa, then make it
true for CPU_R5900 and false for CPU_LOONGSON_3A.  Then the error:

> +  if (opts->fp != 64 && opts->arch == CPU_LOONGSON_3A && !opts->nooddspreg)
> +    as_bad (_("`arch=loongson3a' requires `nooddspreg' when using "
> +	      "`fp=32' or `fp=xx'"));

could apply whenever !ISA_HAS_ODD_SINGLE_FPR.  The default could also
be set based on ISA_HAS_ODD_SINGLE_FPR.


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