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Re: [PATCH] Fixing issue with "Rearrange MIPS INSN* masks" patch
- From: Richard Sandiford <rdsandiford at googlemail dot com>
- To: Andrew Bennett <Andrew dot Bennett at imgtec dot com>
- Cc: "binutils\ at sourceware dot org" <binutils at sourceware dot org>
- Date: Tue, 06 May 2014 18:50:23 +0100
- Subject: Re: [PATCH] Fixing issue with "Rearrange MIPS INSN* masks" patch
- Authentication-results: sourceware.org; auth=none
- References: <0DA23CC379F5F945ACB41CF394B98277577F88 at LEMAIL01 dot le dot imgtec dot org>
Andrew Bennett <Andrew.Bennett@imgtec.com> writes:
> 2014-05-05 Andrew Bennett <andrew.bennett@imgtec.com>
>
> ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ * mips-opc.c (G3): Remove I4.
>
>
> diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
> index 9181c3f..f3b287f 100644
> --- a/opcodes/mips-opc.c
> +++ b/opcodes/mips-opc.c
> @@ -296,8 +296,7 @@ decode_mips_operand (const char *p)
> #define G2ÂÂÂÂÂ (T3ÂÂÂÂÂÂÂÂÂÂÂÂ \
> ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ )
>
> -#define G3ÂÂÂÂÂ (I4ÂÂÂÂÂÂÂÂÂÂÂÂ \
> -ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ |EEÂÂÂÂÂÂÂÂÂÂÂ \
> +#define G3ÂÂÂÂÂ (EEÂÂÂÂÂÂÂÂÂÂÂÂ \
> ÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂÂ )
>
> Â/* 64 bit CPU with 32 bit FPU (single float). */
Might as well make it:
#define G3 EE
OK with that change, thanks.
Richard