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Re: [PATCH/ARM] PR 16722, support VLDR s/d0, =Imm

On 25/04/14 16:50, Richard Earnshaw wrote:
On 22/04/14 13:46, Jiong Wang wrote:
PR target/16722
    * config/tc-arm.c (add_to_lit_pool): Add one parameter 'nbytes'.
    Support literal pool entry be 8 byte.
    (s_ltorg): Likewise.
    (enum lit_type): New enum type.
    (encode_arm_cp_address): Generate literal pool entry if possible.
    (move_or_literal_pool): Generate entry for vldr case.
    (do_ldst): Use new enum type.
    (do_ldstv4): Likewise.
    (do_t_ldst): Likewise.
    (neon_write_immbits): Support Thumb-2 mode.
    * gas/arm/ldconst.s: Add new cases for vldr.
    * gas/arm/ldconst.d: Likewise.
    * gas/arm/thumb2_pool.s: Likewise.
    * gas/arm/thumb2_pool.d: Likewise.

I see no evidence that the 8-byte entries have been placed on 8-byte
aligned locations; I think that should be done since misaligned loads
can be slower than aligned loads.  If the pool contains any 8-byte
entries, then the whole pool should be started on an 8-byte boundary;
you'll then have to insert padding before an 8-byte entry if that is
necessary to get back to alignment.  Bonus points for keeping track of
such holes and making use of them for later literal values that are
small enough to fit.
yes, no alignment support for 8-byte aligned locations.

thanks for pointing this out.

For example, the sequence:

	vldr	s0, =33
	vldr	d1, =55
	vldr	s6, =99

should generate a literal pool that contains

	.p2align 3
	.word	33
	.word	99	// Back-filled
	.dword	55

Also, please can you put the new tests in separate files; they are big
enough, and distinct enough to justify doing this.

OK, I will address this and your following comments.

Some additional comments inline.


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