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[PATCH] Add support for the MIPS P5600 family of CPUs
- From: Andrew Bennett <Andrew dot Bennett at imgtec dot com>
- To: "binutils at sourceware dot org" <binutils at sourceware dot org>
- Date: Tue, 8 Apr 2014 14:36:36 +0000
- Subject: [PATCH] Add support for the MIPS P5600 family of CPUs
- Authentication-results: sourceware.org; auth=none
- References: <0DA23CC379F5F945ACB41CF394B9827753FD7D at LEMAIL01 dot le dot imgtec dot org>
Hi,
This patch adds support for the MIPS P5600 family of CPUs. The P5600 cores
support the MIPS32r5 ISA along with the EVA and Virtualization ASEs as standard.
They also optionally support the MSA ASE. For more information please refer to
the following URL:
http://www.imgtec.com/mips/mips-series5-p5600.asp
The patch and ChangeLog entry are shown below.
Ok to commit?
Many thanks,
Andrew
Andrew Bennett
Software Design Engineer, MIPS Processor IP
Imagination Technologies Limited
t: +44 (0)113 2429814
www.imgtec.com
2014-04-08 Andrew Bennett <andrew.bennett@imgtec.com>
* config/tc-mips.c (mips_cpu_info_table): Add P5600
configuation.
* doc/c-mips.texi: Document p5600.
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 318b0b5..47de8d3 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -17902,6 +17902,8 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
{ "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
{ "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
{ "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
+ /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
+ { "p5600", 0, ASE_VIRT | ASE_EVA, ISA_MIPS32R2, CPU_MIPS32R2 },
/* MIPS 64 */
{ "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 },
diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index 184915e..3778ae2 100644
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -337,6 +337,7 @@ m14kec,
1004kf2_1,
1004kf,
1004kf1_1,
+p5600,
5kc,
5kf,
20kc,