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Help needed for porting opcodes for CISC architecture
- From: Usha Gupta <gusha2960 at gmail dot com>
- To: binutils at sourceware dot org
- Date: Tue, 4 Feb 2014 17:29:28 +0530
- Subject: Help needed for porting opcodes for CISC architecture
- Authentication-results: sourceware.org; auth=none
Hi All ,
I want to port binutils for a CISC architecture wherein the
instruction length can vary from 1 byte
to a maximum of 5-bytes.
I am having trouble porting opcodes using CGEN.
I have defined various hardware elements and instruction fields.
I am not sure what should be the values of
(default-insn-word-bitsize 16 )
(word-bitsize 16 )
As mentioned in the CGEN manual, I specified default-insn bitsize as
8 (smallest instruction length) and
rest of the values as 16 ( word length is 2 bytes).
This works for 16-bit instructions where both the operands are
explicit in the instruction encoding.
Another important thing to mention here is that the machine does not
have a fixed length opcode.
Here are some of the instruction formats :
1) IIIIIrrr - 5 bits opcode , 3 bits for register operand (one of
the operand is fixed register, implied from the opcode)
2) IIIddddd - 3 bits opcode, 5 bit displacement
1) IIIIIsss IIIIIttt - 5-bit opcode, 3-bit register operand
(source), 5-bit opcode, 3-bit register operand (destination)
How do I define instructions of varying length?
Any help is appreciated.