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Re: [PATCH] Add MIPS ufr macro instruction

"Maciej W. Rozycki" <> writes:
> On Fri, 13 Dec 2013, Richard Sandiford wrote:
>> Looks good, thanks, but is there any reason not to use mips_cp1_names_mips3264
>> for all MIPS32 and MIPS64 targets?  I realise some of them don't have an FPU,
>> but if we see (presumably emulated) FPU instructions anyway, then I think we
>> might as well follow the architecture names for the registers.
>  Rev. 1 FPUs only had the FIR, FCCR, FEXR, FENR and FCSR registers.  Older 
> ISAs only had the FIR and FCSR registers.  How about we have separate 
> lists just as with CP0?  Furthermore I don't think these additional lists 
> should be a prerequisite for the acceptance of this patch.

I agree extra lists shouldn't be a requirement.  And until more are
added I think the pragmatic thing to do is to use the full list for
"mips32" and "mips64" too, which is what Andrew's patch did.  But if
we do that then I think we should also use the full list for specific
ISA_MIPS32 and ISA_MIPS64 processors as well the generic ISA.

>> If you agree, then the patch is OK with every ISA_MIPS32* and ISA_MIPS64*
>> entry having mips_cp1_names_mips3264.  If not then let me know :-)
>  Shouldn't there be a complementing GAS part though?

I think that's future work too.  There's no corresponding gas support
for CP0 registers (or any notion of ".set arch"-specific registers really),
so it wouldn't be a trivial patch.


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