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Re: [PATCH] Add MIPS ufr macro instruction

On Fri, 13 Dec 2013, Richard Sandiford wrote:

> Looks good, thanks, but is there any reason not to use mips_cp1_names_mips3264
> for all MIPS32 and MIPS64 targets?  I realise some of them don't have an FPU,
> but if we see (presumably emulated) FPU instructions anyway, then I think we
> might as well follow the architecture names for the registers.

 Rev. 1 FPUs only had the FIR, FCCR, FEXR, FENR and FCSR registers.  Older 
ISAs only had the FIR and FCSR registers.  How about we have separate 
lists just as with CP0?  Furthermore I don't think these additional lists 
should be a prerequisite for the acceptance of this patch.

> E.g.:
> Andrew Bennett <> writes:
> > @@ -525,43 +571,43 @@ const struct mips_arch_choice mips_arch_choices[] =
> >    { "sb1",	1, bfd_mach_mips_sb1, CPU_SB1,
> >      ISA_MIPS64 | INSN_SB1,  ASE_MIPS3D,
> >      mips_cp0_names_sb1,
> >      mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
> > -    mips_hwr_names_numeric },
> > +    mips_cp1_names_numeric, mips_hwr_names_numeric },
> SB1 did have an FPU.

 It was rev. 1 however.

> If you agree, then the patch is OK with every ISA_MIPS32* and ISA_MIPS64*
> entry having mips_cp1_names_mips3264.  If not then let me know :-)

 Shouldn't there be a complementing GAS part though?


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