diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am
index 0a65b75..1d43a25 100644
--- a/opcodes/Makefile.am
+++ b/opcodes/Makefile.am
@@ -206,6 +206,8 @@ TARGET_LIBOPCODES_CFILES = \
 	mt-dis.c \
 	mt-ibld.c \
 	mt-opc.c \
+	nds32-asm.c \
+	nds32-dis.c \
 	nios2-dis.c \
 	nios2-opc.c \
 	ns32k-dis.c \
diff --git a/opcodes/configure.in b/opcodes/configure.in
index 8309373..0d5b6d2 100644
--- a/opcodes/configure.in
+++ b/opcodes/configure.in
@@ -293,6 +293,7 @@ if test x${all_targets} = xfalse ; then
 	bfd_mn10300_arch)	ta="$ta m10300-dis.lo m10300-opc.lo" ;;
 	bfd_mt_arch)		ta="$ta mt-asm.lo mt-desc.lo mt-dis.lo mt-ibld.lo mt-opc.lo" using_cgen=yes ;;
 	bfd_msp430_arch)	ta="$ta msp430-dis.lo msp430-decode.lo" ;;
+	bfd_nds32_arch)		ta="$ta nds32-asm.lo nds32-dis.lo" ;;
 	bfd_nios2_arch)		ta="$ta nios2-dis.lo nios2-opc.lo" ;;
 	bfd_ns32k_arch)		ta="$ta ns32k-dis.lo" ;;
 	bfd_openrisc_arch)	ta="$ta openrisc-asm.lo openrisc-desc.lo openrisc-dis.lo openrisc-ibld.lo openrisc-opc.lo" using_cgen=yes ;;
diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c
index 55a44ec..7ed1274 100644
--- a/opcodes/disassemble.c
+++ b/opcodes/disassemble.c
@@ -67,6 +67,7 @@
 #define ARCH_moxie
 #define ARCH_mt
 #define ARCH_msp430
+#define ARCH_nds32
 #define ARCH_nios2
 #define ARCH_ns32k
 #define ARCH_openrisc
@@ -296,6 +297,11 @@ disassembler (abfd)
       disassemble = print_insn_msp430;
       break;
 #endif
+#ifdef ARCH_nds32
+    case bfd_arch_nds32:
+      disassemble = print_insn_nds32;
+      break;
+#endif
 #ifdef ARCH_ns32k
     case bfd_arch_ns32k:
       disassemble = print_insn_ns32k;
diff --git a/opcodes/nds32-asm.c b/opcodes/nds32-asm.c
new file mode 100644
index 0000000..3d354e6
--- /dev/null
+++ b/opcodes/nds32-asm.c
@@ -0,0 +1,1634 @@
+/* NDS32-specific support for 32-bit ELF.
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.*/
+
+
+#include <config.h>
+
+#include <stdlib.h>
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+
+#include "safe-ctype.h"
+#include "libiberty.h"
+#include "hashtab.h"
+#include "bfd.h"
+
+#include "opcode/nds32.h"
+#include "nds32-asm.h"
+
+/* There at at most MAX_LEX_NUM lexical elements in a syntax.  */
+#define MAX_LEX_NUM		32
+/* A operand in syntax string should be at most this long.  */
+#define MAX_LEX_LEN		32
+/* The max length of a keyword can be.  */
+#define MAX_KEYWORD_LEN		32
+/* This LEX is a plain char or operand.  */
+#define IS_LEX_CHAR(c)		(((c) >> 7) == 0)
+#define LEX_SET_FIELD(c)	((c) | SYN_FIELD)
+#define LEX_GET_FIELD(c)	operand_fields[((c) & 0xff)]
+/* Get the char in this lexical element.  */
+#define LEX_CHAR(c)		((c) & 0xff)
+
+#define USRIDX(group, usr)	((group) | ((usr) << 5))
+#define SRIDX(major, minor, ext) \
+				(((major) << 7) | ((minor) << 3) | (ext))
+
+static int parse_re2 (struct nds32_asm_desc *desc, struct nds32_asm_insn *insn,
+		      char **str, int64_t *value);
+static int parse_fe5 (struct nds32_asm_desc *desc, struct nds32_asm_insn *insn,
+		      char **str, int64_t *value);
+static int parse_pi5 (struct nds32_asm_desc *desc, struct nds32_asm_insn *insn,
+		      char **str, int64_t *value);
+
+
+enum
+{
+  /* This is a field (operand) of just a separator char.  */
+  SYN_FIELD = 0x100,
+
+  /* This operand is used for input or output.  (define or use)  */
+  SYN_INPUT = 0x1000,
+  SYN_OUTPUT = 0x2000,
+  SYN_LOPT = 0x4000,
+  SYN_ROPT = 0x8000,
+
+  /* Hardware resources.  */
+  HW_GPR = 0,
+  HW_USR,
+  HW_DXR,
+  HW_SR,
+  HW_FSR,
+  HW_FDR,
+  HW_CP,	/* Co-processor ID.  */
+  HW_CPR,	/* Co-processor registers.  */
+  HW_ABDIM,	/* [ab][di]m? flag for LSMWA?.  */
+  HW_ABM,	/* [ab]m? flag for LSMWZB.  */
+  HW_DTITON,
+  HW_DTITOFF,
+  HW_DPREF_ST,
+  HW_CCTL_ST0,
+  HW_CCTL_ST1,
+  HW_CCTL_ST2,
+  HW_CCTL_ST3,
+  HW_CCTL_ST4,
+  HW_CCTL_ST5,
+  HW_CCTL_LV,
+  HW_TLBOP_ST,
+  HW_STANDBY_ST,
+  HW_MSYNC_ST,
+  _HW_LAST,
+  /* TODO: Maybe we should add a new type to distinguish address and
+	   const int.  Only the former allows symbols and relocations.  */
+  HW_INT,
+  HW_UINT
+};
+
+
+/* These are operand prefixes for input/output semantic.
+
+     %   input
+     =   output
+     &   both
+     {}  optional operand
+
+   Field table for operands and bit-fields.  */
+
+static const field_t operand_fields[] =
+{
+  {"rt",	20, 5, 0, HW_GPR, NULL},
+  {"ra",	15, 5, 0, HW_GPR, NULL},
+  {"rb",	10, 5, 0, HW_GPR, NULL},
+  {"rd",	5, 5, 0, HW_GPR, NULL},
+  {"fst",	20, 5, 0, HW_FSR, NULL},
+  {"fsa",	15, 5, 0, HW_FSR, NULL},
+  {"fsb",	10, 5, 0, HW_FSR, NULL},
+  {"fdt",	20, 5, 0, HW_FDR, NULL},
+  {"fda",	15, 5, 0, HW_FDR, NULL},
+  {"fdb",	10, 5, 0, HW_FDR, NULL},
+  {"cprt",	20, 5, 0, HW_CPR, NULL},
+  {"cp",	13, 2, 0, HW_CP, NULL},
+  {"sh",	5, 5, 0, HW_UINT, NULL},	/* sh in ALU instructions.  */
+  {"sv",	8, 2, 0, HW_UINT, NULL},	/* sv in MEM instructions.  */
+  {"dt",	21, 1, 0, HW_DXR, NULL},
+  {"usr",	10, 10, 0, HW_USR, NULL},	/* User Special Registers.  */
+  {"sr",	10, 10, 0, HW_SR, NULL},	/* System Registers.  */
+  {"ridx",	10, 10, 0, HW_UINT, NULL},	/* Raw value for mfusr/mfsr.  */
+  {"enb4",	6, 9, 0, HW_UINT, NULL},	/* Enable4 for LSMW.  */
+  {"swid",	5, 15, 0, HW_UINT, NULL},
+  {"stdby_st",	5, 2, 0, HW_STANDBY_ST, NULL},
+  {"tlbop_st",	5, 5, 0, HW_TLBOP_ST, NULL},
+  {"tlbop_stx",	5, 5, 0, HW_UINT, NULL},
+  {"cctl_st0",	5, 5, 0, HW_CCTL_ST0, NULL},
+  {"cctl_st1",	5, 5, 0, HW_CCTL_ST1, NULL},
+  {"cctl_st2",	5, 5, 0, HW_CCTL_ST2, NULL},
+  {"cctl_st3",	5, 5, 0, HW_CCTL_ST3, NULL},
+  {"cctl_st4",	5, 5, 0, HW_CCTL_ST4, NULL},
+  {"cctl_st5",	5, 5, 0, HW_CCTL_ST5, NULL},
+  {"cctl_stx",	5, 5, 0, HW_UINT, NULL},
+  {"cctl_lv",	10, 1, 0, HW_CCTL_LV, NULL},
+  {"msync_st",	5, 3, 0, HW_MSYNC_ST, NULL},
+  {"msync_stx",	5, 3, 0, HW_UINT, NULL},
+  {"dpref_st",	20, 5, 0, HW_DPREF_ST, NULL},
+  {"rt5",	5, 5, 0, HW_GPR, NULL},
+  {"ra5",	0, 5, 0, HW_GPR, NULL},
+  {"rt4",	5, 4, 0, HW_GPR, NULL},
+  {"rt3",	6, 3, 0, HW_GPR, NULL},
+  {"rt38",	8, 3, 0, HW_GPR, NULL},	/* rt3 used in 38 form.  */
+  {"ra3",	3, 3, 0, HW_GPR, NULL},
+  {"rb3",	0, 3, 0, HW_GPR, NULL},
+  {"rt5e",	4, 4, 1, HW_GPR, NULL},	/* movd44 */
+  {"ra5e",	0, 4, 1, HW_GPR, NULL},	/* movd44 */
+  {"re2",	5, 2, 0, HW_GPR, parse_re2},	/* re in push25/pop25.  */
+  {"fe5",	0, 5, 2, HW_UINT, parse_fe5},	/* imm5u in lwi45.fe.  */
+  {"pi5",	0, 5, 0, HW_UINT, parse_pi5},	/* imm5u in movpi45.  */
+  {"abdim",	2, 3, 0, HW_ABDIM, NULL},	/* Flags for LSMW. */
+  {"abm",	2, 3, 0, HW_ABM, NULL},	/* Flags for LSMWZB. */
+  {"dtiton",	8, 2, 0, HW_DTITON, NULL},
+  {"dtitoff",	8, 2, 0, HW_DTITOFF, NULL},
+
+  {"i5s",	0, 5, 0, HW_INT, NULL},
+  {"i10s",	0, 10, 0, HW_INT, NULL},
+  {"i15s",	0, 15, 0, HW_INT, NULL},
+  {"i19s",	0, 19, 0, HW_INT, NULL},
+  {"i20s",	0, 20, 0, HW_INT, NULL},
+  {"i8s1",	0, 8, 1, HW_INT, NULL},
+  {"i11br3",	8, 11, 0, HW_INT, NULL},
+  {"i14s1",	0, 14, 1, HW_INT, NULL},
+  {"i15s1",	0, 15, 1, HW_INT, NULL},
+  {"i16s1",	0, 16, 1, HW_INT, NULL},
+  {"i18s1",	0, 18, 1, HW_INT, NULL},
+  {"i24s1",	0, 24, 1, HW_INT, NULL},
+  {"i8s2",	0, 8, 2, HW_INT, NULL},
+  {"i12s2",	0, 12, 2, HW_INT, NULL},
+  {"i15s2",	0, 15, 2, HW_INT, NULL},
+  {"i17s2",	0, 17, 2, HW_INT, NULL},
+  {"i19s2",	0, 19, 2, HW_INT, NULL},
+  {"i3u",	0, 3, 0, HW_UINT, NULL},
+  {"i5u",	0, 5, 0, HW_UINT, NULL},
+  {"ib5u",	10, 5, 0, HW_UINT, NULL},	/* imm5 field in ALU.  */
+  {"ib5s",	10, 5, 0, HW_INT, NULL},	/* imm5 field in ALU.  */
+  {"i9u",	0, 9, 0, HW_UINT, NULL},	/* break16/ex9.it */
+  {"ia3u",	3, 3, 0, HW_UINT, NULL},	/* bmski33, fexti33 */
+  {"i8u",	0, 8, 0, HW_UINT, NULL},
+  {"i15u",	0, 15, 0, HW_UINT, NULL},
+  {"i20u",	0, 20, 0, HW_UINT, NULL},
+  {"i3u1",	0, 3, 1, HW_UINT, NULL},
+  {"i9u1",	0, 9, 1, HW_UINT, NULL},
+  {"i3u2",	0, 3, 2, HW_UINT, NULL},
+  {"i6u2",	0, 6, 2, HW_UINT, NULL},
+  {"i7u2",	0, 7, 2, HW_UINT, NULL},
+  {"i5u3",	0, 5, 3, HW_UINT, NULL},	/* pop25/pop25 */
+  {"i15s3",	0, 15, 3, HW_UINT, NULL},	/* dprefi.d */
+
+  {NULL, 0, 0, 0, 0, NULL}
+};
+
+
+#define OP6(op6)		(N32_OP6_ ## op6 << 25)
+#define DEF_REG(r)		(__BIT (r))
+#define USE_REG(r)		(__BIT (r))
+#define RT(r)			(r << 20)
+#define RA(r)			(r << 15)
+#define RB(r)			(r << 10)
+#define RA5(r)			(r)
+
+static struct nds32_opcode nds32_opcodes[] =
+{
+  /* ALU1 */
+  #define ALU1(sub)	(OP6 (ALU1) | N32_ALU1_ ## sub)
+  {"add", "=rt,%ra,%rb",		ALU1 (ADD), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"sub", "=rt,%ra,%rb",		ALU1 (SUB), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"and", "=rt,%ra,%rb",		ALU1 (AND), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"xor", "=rt,%ra,%rb",		ALU1 (XOR), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"or", "=rt,%ra,%rb",			ALU1 (OR), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"nor", "=rt,%ra,%rb",		ALU1 (NOR), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"slt", "=rt,%ra,%rb",		ALU1 (SLT), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"slts", "=rt,%ra,%rb",		ALU1 (SLTS), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"slli", "=rt,%ra,%ib5u",		ALU1 (SLLI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"srli", "=rt,%ra,%ib5u",		ALU1 (SRLI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"srai", "=rt,%ra,%ib5u",		ALU1 (SRAI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"rotri", "=rt,%ra,%ib5u",		ALU1 (ROTRI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"sll", "=rt,%ra,%rb",		ALU1 (SLL), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"srl", "=rt,%ra,%rb",		ALU1 (SRL), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"sra", "=rt,%ra,%rb",		ALU1 (SRA), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"rotr", "=rt,%ra,%rb",		ALU1 (ROTR), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"seb", "=rt,%ra",			ALU1 (SEB), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"seh", "=rt,%ra",			ALU1 (SEH), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"bitc", "=rt,%ra,%rb",		ALU1 (BITC), 4, ATTR_V3, 0, NULL, 0, NULL},
+  {"zeh", "=rt,%ra",			ALU1 (ZEH), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"wsbh", "=rt,%ra",			ALU1 (WSBH), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"divsr", "=rt,=rd,%ra,%rb",		ALU1 (DIVSR), 4, ATTR (DIV) | ATTR_V2UP, 0, NULL, 0, NULL},
+  {"divr", "=rt,=rd,%ra,%rb",		ALU1 (DIVR), 4, ATTR (DIV) | ATTR_V2UP, 0, NULL, 0, NULL},
+  {"sva", "=rt,%ra,%rb",		ALU1 (SVA), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"svs", "=rt,%ra,%rb",		ALU1 (SVS), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"cmovz", "=rt,%ra,%rb",		ALU1 (CMOVZ), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"cmovn", "=rt,%ra,%rb",		ALU1 (CMOVN), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"add_slli", "=rt,%ra,%rb,%sh",	ALU1 (ADD), 4, ATTR_V3, 0, NULL, 0, NULL},
+  {"sub_slli", "=rt,%ra,%rb,%sh",	ALU1 (SUB), 4, ATTR_V3, 0, NULL, 0, NULL},
+  {"and_slli", "=rt,%ra,%rb,%sh",	ALU1 (AND), 4, ATTR_V3, 0, NULL, 0, NULL},
+  {"xor_slli", "=rt,%ra,%rb,%sh",	ALU1 (XOR), 4, ATTR_V3, 0, NULL, 0, NULL},
+  {"or_slli", "=rt,%ra,%rb,%sh",	ALU1 (OR), 4, ATTR_V3, 0, NULL, 0, NULL},
+  {"or_srli", "=rt,%ra,%rb,%sh",	ALU1 (OR_SRLI), 4, ATTR_V3, 0, NULL, 0, NULL},
+  {"add_srli", "=rt,%ra,%rb,%sh",	ALU1 (ADD_SRLI), 4, ATTR_V3, 0, NULL, 0, NULL},
+  {"sub_srli", "=rt,%ra,%rb,%sh",	ALU1 (SUB_SRLI), 4, ATTR_V3, 0, NULL, 0, NULL},
+  {"and_srli", "=rt,%ra,%rb,%sh",	ALU1 (AND_SRLI), 4, ATTR_V3, 0, NULL, 0, NULL},
+  {"xor_srli", "=rt,%ra,%rb,%sh",	ALU1 (XOR_SRLI), 4, ATTR_V3, 0, NULL, 0, NULL},
+
+  /* ALU2 */
+  #define ALU2(sub)	(OP6 (ALU2) | N32_ALU2_ ## sub)
+  {"max", "=rt,%ra,%rb",	ALU2 (MAX), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
+  {"min", "=rt,%ra,%rb",	ALU2 (MIN), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
+  {"ave", "=rt,%ra,%rb",	ALU2 (AVE), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
+  {"abs", "=rt,%ra",		ALU2 (ABS), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
+  {"clips", "=rt,%ra,%ib5s",	ALU2 (CLIPS), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
+  {"clip", "=rt,%ra,%ib5u",	ALU2 (CLIP), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
+  {"clo", "=rt,%ra",		ALU2 (CLO), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
+  {"clz", "=rt,%ra",		ALU2 (CLZ), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
+  {"bset", "=rt,%ra,%ib5u",	ALU2 (BSET), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
+  {"bclr", "=rt,%ra,%ib5u",	ALU2 (BCLR), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
+  {"btgl", "=rt,%ra,%ib5u",	ALU2 (BTGL), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
+  {"btst", "=rt,%ra,%ib5u",	ALU2 (BTST), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL},
+  {"bse", "=rt,%ra,=rb",	ALU2 (BSE), 4, ATTR (PERF2_EXT), 0, NULL, 0, NULL},
+  {"bsp", "=rt,%ra,=rb",	ALU2 (BSP), 4, ATTR (PERF2_EXT), 0, NULL, 0, NULL},
+  {"ffb", "=rt,%ra,%rb",	ALU2 (FFB), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
+  {"ffmism", "=rt,%ra,%rb",	ALU2 (FFMISM), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
+  {"ffzmism", "=rt,%ra,%rb",	ALU2 (FFZMISM), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
+  {"mfusr", "=rt,%usr",		ALU2 (MFUSR), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
+  {"mtusr", "%rt,%usr",		ALU2 (MTUSR), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
+  {"mfusr", "=rt,%ridx",	ALU2 (MFUSR), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
+  {"mtusr", "%rt,%ridx",	ALU2 (MTUSR), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
+  {"mul", "=rt,%ra,%rb",	ALU2 (MUL), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"mults64", "=dt,%ra,%rb",	ALU2 (MULTS64), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"mult64", "=dt,%ra,%rb",	ALU2 (MULT64), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"madds64", "=dt,%ra,%rb",	ALU2 (MADDS64), 4, ATTR (MAC) | ATTR_ALL, 0, NULL, 0, NULL},
+  {"madd64", "=dt,%ra,%rb",	ALU2 (MADD64), 4, ATTR (MAC) | ATTR_ALL, 0, NULL, 0, NULL},
+  {"msubs64", "=dt,%ra,%rb",	ALU2 (MSUBS64), 4, ATTR (MAC) | ATTR_ALL, 0, NULL, 0, NULL},
+  {"msub64", "=dt,%ra,%rb",	ALU2 (MSUB64), 4, ATTR (MAC) | ATTR_ALL, 0, NULL, 0, NULL},
+  {"divs", "=dt,%ra,%rb",	ALU2 (DIVS), 4, ATTR (DIV) | ATTR (DXREG), 0, NULL, 0, NULL},
+  {"div", "=dt,%ra,%rb",	ALU2 (DIV), 4, ATTR (DIV) | ATTR (DXREG), 0, NULL, 0, NULL},
+  {"mult32", "=dt,%ra,%rb",	ALU2 (MULT32), 4, ATTR (DXREG) | ATTR_ALL, 0, NULL, 0, NULL},
+  {"madd32", "=dt,%ra,%rb",	ALU2 (MADD32), 4, ATTR (MAC) | ATTR (DXREG) | ATTR_ALL, 0, NULL, 0, NULL},
+  {"msub32", "=dt,%ra,%rb",	ALU2 (MSUB32), 4, ATTR (MAC) | ATTR (DXREG) | ATTR_ALL, 0, NULL, 0, NULL},
+  {"ffbi", "=rt,%ra,%ib5u",	ALU2 (FFBI) | __BIT (6), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
+  {"flmism", "=rt,%ra,%rb",	ALU2 (FLMISM) | __BIT (6), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
+  {"mulsr64", "=rt,%ra,%rb",	ALU2 (MULSR64)| __BIT (6), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
+  {"mulr64", "=rt,%ra,%rb",	ALU2 (MULR64) | __BIT (6), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
+  {"maddr32", "=rt,%ra,%rb",	ALU2 (MADDR32) | __BIT (6), 4, ATTR (MAC) | ATTR_V2UP, 0, NULL, 0, NULL},
+  {"msubr32", "=rt,%ra,%rb",	ALU2 (MSUBR32) | __BIT (6), 4, ATTR (MAC) | ATTR_V2UP, 0, NULL, 0, NULL},
+
+  /* MISC */
+  #define MISC(sub)	(OP6 (MISC) | N32_MISC_ ## sub)
+  {"standby", "%stdby_st",	MISC (STANDBY), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"cctl", "%ra,%cctl_st0",	MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
+  {"cctl", "%ra,%cctl_st1{,%cctl_lv}", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
+  {"cctl", "=rt,%ra,%cctl_st2",	MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
+  {"cctl", "%rt,%ra,%cctl_st3",	MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
+  {"cctl", "%cctl_st4",		MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
+  {"cctl", "%cctl_st5{,%cctl_lv}", MISC (CCTL), 4, ATTR_V3, 0, NULL, 0, NULL},
+  {"cctl", "=rt,%ra,%cctl_stx,%cctl_lv", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
+  {"mfsr", "=rt,%sr",		MISC (MFSR), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"mtsr", "%rt,%sr",		MISC (MTSR), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"mfsr", "=rt,%ridx",		MISC (MFSR), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"mtsr", "%rt,%ridx",		MISC (MTSR), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"iret", "",			MISC (IRET), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"trap", "%swid",		MISC (TRAP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
+  {"trap", "",			MISC (TRAP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
+  {"teqz", "%rt,%swid",		MISC (TEQZ), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
+  {"tnez", "%rt,%swid",		MISC (TNEZ), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
+  {"dsb", "",			MISC (DSB), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"isb", "",			MISC (ISB), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"break", "%swid",		MISC (BREAK), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"break", "",			MISC (BREAK), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"syscall", "%swid",		MISC (SYSCALL), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"msync", "%msync_st",	MISC (MSYNC), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"msync", "%msync_stx",	MISC (MSYNC), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"isync", "%rt",		MISC (ISYNC), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"tlbop", "%ra,%tlbop_st",	MISC (TLBOP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
+  {"tlbop", "%ra,%tlbop_stx",	MISC (TLBOP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
+  {"tlbop", "%rt,%ra,pb",	MISC (TLBOP) | (5 << 5), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
+  {"tlbop", "flua",		MISC (TLBOP) | (7 << 5), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
+
+  {"setend.l", "",		MISC (MTSR)
+				| (SRIDX (1, 0, 0) << 10) | __BIT (5), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"setend.b", "",		MISC (MTSR)
+				| (SRIDX (1, 0, 0) << 10) | __BIT (5) | __BIT (20), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"setgie.d", "",		MISC (MTSR)
+				| (SRIDX (1, 0, 0) << 10) | __BIT (6), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"setgie.e", "",		MISC (MTSR)
+				| (SRIDX (1, 0, 0) << 10) | __BIT (6) | __BIT (20), 4, ATTR_ALL, 0, NULL, 0, NULL},
+
+  /* JI */
+  {"jal", "%i24s1",		OP6 (JI) | __BIT (24), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
+  {"j", "%i24s1",		OP6 (JI), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
+
+  /* BR1 */
+  {"beq", "%rt,%ra,%i14s1",	OP6 (BR1), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
+  {"bne", "%rt,%ra,%i14s1",	OP6 (BR1) | __BIT (14), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
+
+  /* BR2 */
+  #define BR2(sub)	(OP6 (BR2) | (N32_BR2_ ## sub << 16))
+  {"beqz", "%rt,%i16s1",	BR2 (BEQZ), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
+  {"bnez", "%rt,%i16s1",	BR2 (BNEZ), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
+  {"bgez", "%rt,%i16s1",	BR2 (BGEZ), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
+  {"bltz", "%rt,%i16s1",	BR2 (BLTZ), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
+  {"bgtz", "%rt,%i16s1",	BR2 (BGTZ), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
+  {"blez", "%rt,%i16s1",	BR2 (BLEZ), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
+  {"bgezal", "%rt,%i16s1",	BR2 (BGEZAL), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
+  {"bltzal", "%rt,%i16s1",	BR2 (BLTZAL), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
+
+  /* BR3 */
+  {"beqc", "%rt,%i11br3,%i8s1",	OP6 (BR3), 4, ATTR_PCREL | ATTR_V3MUP, 0, NULL, 0, NULL},
+  {"bnec", "%rt,%i11br3,%i8s1",	OP6 (BR3) | __BIT (19), 4, ATTR_PCREL | ATTR_V3MUP, 0, NULL, 0, NULL},
+
+  #define JREG(sub)	(OP6 (JREG) | N32_JREG_ ## sub)
+  /* JREG */
+  {"jr", "%rb",			JREG (JR), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL},
+  {"jral", "%rt,%rb",		JREG (JRAL), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL},
+  {"jral", "%rb",		JREG (JRAL) | RT (30), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL},
+  {"jrnez", "%rb",		JREG (JRNEZ), 4, ATTR (BRANCH) | ATTR_V3, 0, NULL, 0, NULL},
+  {"jralnez", "%rt,%rb",	JREG (JRALNEZ), 4, ATTR (BRANCH) | ATTR_V3, 0, NULL, 0, NULL},
+  {"jralnez", "%rb",		JREG (JRALNEZ) | RT (30), 4, ATTR (BRANCH) | ATTR_V3, 0, NULL, 0, NULL},
+
+  #define JREG_RET	(1 << 5)
+  #define JREG_IFC	(1 << 6)
+  {"ret", "%rb",		JREG (JR) | JREG_RET, 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL},
+  {"ret", "",			JREG (JR) | JREG_RET | RB (30), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL},
+  {"jral", "%dtiton %rt,%rb",	JREG (JRAL), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL},
+  {"jral", "%dtiton %rb",	JREG (JRAL) | RT (30), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL},
+  {"jr", "%dtitoff %rb",	JREG (JR), 4, ATTR (BRANCH) | ATTR_V3MEX_V1, 0, NULL, 0, NULL},
+  {"ret", "%dtitoff %rb",	JREG (JR) | JREG_RET, 4, ATTR (BRANCH) | ATTR_V3MEX_V1, 0, NULL, 0, NULL},
+  {"ifret", "",			JREG (JR) | JREG_IFC | JREG_RET, 4, ATTR (BRANCH) | ATTR (IFC_EXT), 0, NULL, 0, NULL},
+
+  /* MEM */
+  #define MEM(sub)	(OP6 (MEM) | N32_MEM_ ## sub)
+  {"lb", "=rt,[%ra+(%rb<<%sv)]",                MEM (LB), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"lb", "=rt,[%ra+%rb{<<%sv}]",		MEM (LB), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"lh", "=rt,[%ra+(%rb<<%sv)]",                MEM (LH), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"lh", "=rt,[%ra+%rb{<<%sv}]",		MEM (LH), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"lw", "=rt,[%ra+(%rb<<%sv)]",                MEM (LW), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"lw", "=rt,[%ra+%rb{<<%sv}]",		MEM (LW), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"sb", "=rt,[%ra+(%rb<<%sv)]",                MEM (SB), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"sb", "%rt,[%ra+%rb{<<%sv}]",		MEM (SB), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"sh", "=rt,[%ra+(%rb<<%sv)]",                MEM (SH), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"sh", "%rt,[%ra+%rb{<<%sv}]",		MEM (SH), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"sw", "=rt,[%ra+(%rb<<%sv)]",                MEM (SW), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"sw", "%rt,[%ra+%rb{<<%sv}]",		MEM (SW), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"lb.bi", "=rt,[%ra],(%rb<<%sv)",		MEM (LB_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"lb.bi", "=rt,[%ra],%rb{<<%sv}",		MEM (LB_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"lh.bi", "=rt,[%ra],(%rb<<%sv)",		MEM (LH_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"lh.bi", "=rt,[%ra],%rb{<<%sv}",		MEM (LH_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"lw.bi", "=rt,[%ra],(%rb<<%sv)",		MEM (LW_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"lw.bi", "=rt,[%ra],%rb{<<%sv}",		MEM (LW_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"sb.bi", "=rt,[%ra],(%rb<<%sv)",		MEM (SB_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"sb.bi", "%rt,[%ra],%rb{<<%sv}",		MEM (SB_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"sh.bi", "=rt,[%ra],(%rb<<%sv)",		MEM (SH_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"sh.bi", "%rt,[%ra],%rb{<<%sv}",		MEM (SH_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"sw.bi", "=rt,[%ra],(%rb<<%sv)",		MEM (SW_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"sw.bi", "%rt,[%ra],%rb{<<%sv}",		MEM (SW_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"lbs", "=rt,[%ra+(%rb<<%sv)]",		MEM (LBS), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"lbs", "=rt,[%ra+%rb{<<%sv}]",		MEM (LBS), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"lhs", "=rt,[%ra+(%rb<<%sv)]",		MEM (LHS), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"lhs", "=rt,[%ra+%rb{<<%sv}]",		MEM (LHS), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"lbs.bi", "=rt,[%ra],(%rb<<%sv)",		MEM (LBS_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"lbs.bi", "=rt,[%ra],%rb{<<%sv}",		MEM (LBS_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"lhs.bi", "=rt,[%ra],(%rb<<%sv)",		MEM (LHS_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"lhs.bi", "=rt,[%ra],%rb{<<%sv}",		MEM (LHS_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"llw", "=rt,[%ra+(%rb<<%sv)]",		MEM (LLW), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
+  {"llw", "=rt,[%ra+%rb{<<%sv}]",		MEM (LLW), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
+  {"scw", "%rt,[%ra+(%rb<<%sv)]",		MEM (SCW), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
+  {"scw", "%rt,[%ra+%rb{<<%sv}]",		MEM (SCW), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
+  {"lbup", "=rt,[%ra+(%rb<<%sv)]",		MEM (LBUP), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
+  {"lbup", "=rt,[%ra+%rb{<<%sv}]",		MEM (LBUP), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
+  {"lwup", "=rt,[%ra+(%rb<<%sv)]",		MEM (LWUP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
+  {"lwup", "=rt,[%ra+%rb{<<%sv}]",		MEM (LWUP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
+  {"sbup", "%rt,[%ra+(%rb<<%sv)]",		MEM (SBUP), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
+  {"sbup", "%rt,[%ra+%rb{<<%sv}]",		MEM (SBUP), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
+  {"swup", "%rt,[%ra+(%rb<<%sv)]",		MEM (SWUP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
+  {"swup", "%rt,[%ra+%rb{<<%sv}]",		MEM (SWUP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
+  {"dpref", "%dpref_st,[%ra+(%rb<<%sv)]",	MEM (DPREF), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
+  {"dpref", "%dpref_st,[%ra+%rb{<<%sv}]",	MEM (DPREF), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
+
+  /* LBGP */
+  {"lbi.gp", "=rt,[+%i19s]",	OP6 (LBGP), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
+  {"lbsi.gp", "=rt,[+%i19s]",	OP6 (LBGP) | __BIT (19), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
+
+  /* SBGP */
+  {"sbi.gp", "%rt,[+%i19s]",	OP6 (SBGP), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
+  {"addi.gp", "=rt,%i19s",	OP6 (SBGP) | __BIT (19), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
+
+  /* HWGP */
+  {"lhi.gp", "=rt,[+%i18s1]",	OP6 (HWGP), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
+  {"lhsi.gp", "=rt,[+%i18s1]",	OP6 (HWGP) | (2 << 17), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
+  {"shi.gp", "%rt,[+%i18s1]",	OP6 (HWGP) | (4 << 17), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
+  {"lwi.gp", "=rt,[+%i17s2]",	OP6 (HWGP) | (6 << 17), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
+  {"swi.gp", "%rt,[+%i17s2]",	OP6 (HWGP) | (7 << 17), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
+
+  #define LSMW(sub)	(OP6 (LSMW) | N32_LSMW_ ## sub)
+  {"lmw", "%abdim %rt,[%ra],%rb{,%enb4}",		LSMW (LSMW), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"smw", "%abdim %rt,[%ra],%rb{,%enb4}",		LSMW (LSMW) | __BIT (5), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"lmwa", "%abdim %rt,[%ra],%rb{,%enb4}",	LSMW (LSMWA), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
+  {"smwa", "%abdim %rt,[%ra],%rb{,%enb4}",	LSMW (LSMWA) | __BIT (5), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
+  {"lmwzb", "%abm %rt,[%ra],%rb{,%enb4}",	LSMW (LSMWZB), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
+  {"smwzb", "%abm %rt,[%ra],%rb{,%enb4}",	LSMW (LSMWZB) | __BIT (5), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
+
+
+  #define SIMD(sub)	(OP6 (SIMD) | N32_SIMD_ ## sub)
+  {"pbsad", "%rt,%rb,%ra",	SIMD (PBSAD), 4, ATTR (PERF2_EXT), 0, NULL, 0, NULL},
+  {"pbsada", "%rt,%rb,%ra",	SIMD (PBSADA), 4, ATTR (PERF2_EXT), 0, NULL, 0, NULL},
+
+  /* COP */
+#if 0
+  {"cpe1", 0, 0, NULL, 0, NULL},
+  {"mfcp", 0, 0, NULL, 0, NULL},
+  {"cplw", 0, 0, NULL, 0, NULL},
+  {"cplw.bi", 0, 0, NULL, 0, NULL},
+  {"cpld", 0, 0, NULL, 0, NULL},
+  {"cpld.bi", 0, 0, NULL, 0, NULL},
+  {"cpe2", 0, 0, NULL, 0, NULL},
+
+  {"cpe3", 0, 0, NULL, 0, NULL},
+  {"mtcp", 0, 0, NULL, 0, NULL},
+  {"cpsw", 0, 0, NULL, 0, NULL},
+  {"cpsw.bi", 0, 0, NULL, 0, NULL},
+  {"cpsd", 0, 0, NULL, 0, NULL},
+  {"cpsd.bi", 0, 0, NULL, 0, NULL},
+  {"cpe4", 0, 0, NULL, 0, NULL},
+#endif
+
+  /* FPU */
+  #define FS1(sub)	(OP6 (COP) | N32_FPU_FS1 | (N32_FPU_FS1_ ## sub << 6))
+  {"fadds",   "=fst,%fsa,%fsb",	FS1 (FADDS),	4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
+  {"fsubs",   "=fst,%fsa,%fsb",	FS1 (FSUBS),	4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
+  {"fcpynss", "=fst,%fsa,%fsb",	FS1 (FCPYNSS),	4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
+  {"fcpyss",  "=fst,%fsa,%fsb",	FS1 (FCPYSS),	4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
+  {"fmadds",  "=fst,%fsa,%fsb", FS1 (FMADDS),   4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
+  {"fmsubs",  "=fst,%fsa,%fsb", FS1 (FMSUBS),   4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
+  {"fcmovns", "=fst,%fsa,%fsb", FS1 (FCMOVNS),  4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
+  {"fcmovzs", "=fst,%fsa,%fsb", FS1 (FCMOVZS),  4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
+  {"fnmadds", "=fst,%fsa,%fsb", FS1 (FNMADDS),  4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
+  {"fnmsubs", "=fst,%fsa,%fsb", FS1 (FNMSUBS),  4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
+  {"fmuls",   "=fst,%fsa,%fsb", FS1 (FMULS),	4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
+  {"fdivs",   "=fst,%fsa,%fsb", FS1 (FDIVS),	4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
+
+  #define FS1_F2OP(sub)	(OP6 (COP) | N32_FPU_FS1 | (N32_FPU_FS1_F2OP << 6) \
+			 | (N32_FPU_FS1_F2OP_ ## sub << 10))
+  {"fs2d",    "=fdt,%fsa",	FS1_F2OP (FS2D),    4, ATTR (FPU) | ATTR (FPU_SP_EXT) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
+  {"fsqrts",  "=fst,%fsa",	FS1_F2OP (FSQRTS),  4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
+  {"fabss",   "=fst,%fsa",	FS1_F2OP (FABSS),   4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
+  {"fui2s",   "=fst,%fsa",	FS1_F2OP (FUI2S),   4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
+  {"fsi2s",   "=fst,%fsa",	FS1_F2OP (FSI2S),   4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
+  {"fs2ui",   "=fst,%fsa",	FS1_F2OP (FS2UI),   4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
+  {"fs2ui.z", "=fst,%fsa",	FS1_F2OP (FS2UI_Z), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
+  {"fs2si",   "=fst,%fsa",	FS1_F2OP (FS2SI),   4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
+  {"fs2si.z", "=fst,%fsa",	FS1_F2OP (FS2SI_Z), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
+
+  #define FS2(sub)	(OP6 (COP) | N32_FPU_FS2 | (N32_FPU_FS2_ ## sub << 6))
+  {"fcmpeqs",   "=fst,%fsa,%fsb", FS2 (FCMPEQS),   4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
+  {"fcmplts",   "=fst,%fsa,%fsb", FS2 (FCMPLTS),   4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
+  {"fcmples",   "=fst,%fsa,%fsb", FS2 (FCMPLES),   4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
+  {"fcmpuns",   "=fst,%fsa,%fsb", FS2 (FCMPUNS),   4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
+  {"fcmpeqs.e", "=fst,%fsa,%fsb", FS2 (FCMPEQS_E), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
+  {"fcmplts.e", "=fst,%fsa,%fsb", FS2 (FCMPLTS_E), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
+  {"fcmples.e", "=fst,%fsa,%fsb", FS2 (FCMPLES_E), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
+  {"fcmpuns.e", "=fst,%fsa,%fsb", FS2 (FCMPUNS_E), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL},
+
+  #define FD1(sub)	(OP6 (COP) | N32_FPU_FD1 | (N32_FPU_FD1_ ## sub << 6))
+  {"faddd",   "=fdt,%fda,%fdb", FD1 (FADDD),    4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
+  {"fsubd",   "=fdt,%fda,%fdb", FD1 (FSUBD),    4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
+  {"fcpynsd", "=fdt,%fda,%fdb", FD1 (FCPYNSD),  4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
+  {"fcpysd",  "=fdt,%fda,%fdb", FD1 (FCPYSD),   4, ATTR (FPU), 0, NULL, 0, NULL},
+  {"fmaddd",  "=fdt,%fda,%fdb", FD1 (FMADDD),   4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
+  {"fmsubd",  "=fdt,%fda,%fdb", FD1 (FMSUBD),   4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
+  {"fcmovnd", "=fdt,%fda,%fsb", FD1 (FCMOVND),  4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
+  {"fcmovzd", "=fdt,%fda,%fsb", FD1 (FCMOVZD),  4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
+  {"fnmaddd", "=fdt,%fda,%fdb", FD1 (FNMADDD),  4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
+  {"fnmsubd", "=fdt,%fda,%fdb", FD1 (FNMSUBD),  4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
+  {"fmuld",   "=fdt,%fda,%fdb", FD1 (FMULD),    4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
+  {"fdivd",   "=fdt,%fda,%fdb", FD1 (FDIVD),    4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
+
+  #define FD1_F2OP(sub)	(OP6 (COP) | N32_FPU_FD1 | (N32_FPU_FD1_F2OP << 6) \
+			 | (N32_FPU_FD1_F2OP_ ## sub << 10))
+  {"fd2s",    "=fst,%fda",	FD1_F2OP (FD2S),    4, ATTR (FPU) | ATTR (FPU_SP_EXT) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
+  {"fsqrtd",  "=fdt,%fda",	FD1_F2OP (FSQRTD),  4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
+  {"fabsd",   "=fdt,%fda",	FD1_F2OP (FABSD),   4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
+  {"fui2d",   "=fdt,%fsa",	FD1_F2OP (FUI2D),   4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
+  {"fsi2d",   "=fdt,%fsa",	FD1_F2OP (FSI2D),   4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
+  {"fd2ui",   "=fst,%fda",	FD1_F2OP (FD2UI),   4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
+  {"fd2ui.z", "=fst,%fda",	FD1_F2OP (FD2UI_Z), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
+  {"fd2si",   "=fst,%fda",	FD1_F2OP (FD2SI),   4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
+  {"fd2si.z", "=fst,%fda",	FD1_F2OP (FD2SI_Z), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
+
+  #define FD2(sub)	(OP6 (COP) | N32_FPU_FD2 | (N32_FPU_FD2_ ## sub << 6))
+  {"fcmpeqd",   "=fst,%fda,%fdb", FD2 (FCMPEQD),   4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
+  {"fcmpltd",   "=fst,%fda,%fdb", FD2 (FCMPLTD),   4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
+  {"fcmpled",   "=fst,%fda,%fdb", FD2 (FCMPLED),   4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
+  {"fcmpund",   "=fst,%fda,%fdb", FD2 (FCMPUND),   4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
+  {"fcmpeqd.e", "=fst,%fda,%fdb", FD2 (FCMPEQD_E), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
+  {"fcmpltd.e", "=fst,%fda,%fdb", FD2 (FCMPLTD_E), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
+  {"fcmpled.e", "=fst,%fda,%fdb", FD2 (FCMPLED_E), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
+  {"fcmpund.e", "=fst,%fda,%fdb", FD2 (FCMPUND_E), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL},
+
+  #define MFCP(sub)	(OP6 (COP) | N32_FPU_MFCP | (N32_FPU_MFCP_ ## sub << 6))
+  {"fmfsr",   "=rt,%fsa", MFCP (FMFSR),   4, ATTR (FPU), 0, NULL, 0, NULL},
+  {"fmfdr",   "=rt,%fda", MFCP (FMFDR),   4, ATTR (FPU), 0, NULL, 0, NULL},
+
+  #define MFCP_XR(sub)	(OP6 (COP) | N32_FPU_MFCP | (N32_FPU_MFCP_XR << 6) \
+			 | (N32_FPU_MFCP_XR_ ## sub << 10))
+  {"fmfcfg", "=rt"	, MFCP_XR(FMFCFG), 4, ATTR (FPU), 0, NULL, 0, NULL},
+  {"fmfcsr", "=rt"	, MFCP_XR(FMFCSR), 4, ATTR (FPU), 0, NULL, 0, NULL},
+
+  #define MTCP(sub)	(OP6 (COP) | N32_FPU_MTCP | (N32_FPU_MTCP_ ## sub << 6))
+  {"fmtsr",   "%rt,=fsa", MTCP (FMTSR),   4, ATTR (FPU), 0, NULL, 0, NULL},
+  {"fmtdr",   "%rt,=fda", MTCP (FMTDR),   4, ATTR (FPU), 0, NULL, 0, NULL},
+
+  #define MTCP_XR(sub)	(OP6 (COP) | N32_FPU_MTCP | (N32_FPU_MTCP_XR << 6) \
+			 | (N32_FPU_MTCP_XR_ ## sub << 10))
+  {"fmtcsr", "%rt"	, MTCP_XR(FMTCSR), 4, ATTR (FPU), 0, NULL, 0, NULL},
+
+  #define FPU_MEM(sub)		(OP6 (COP) | N32_FPU_ ## sub)
+  #define FPU_MEMBI(sub)	(OP6 (COP) | N32_FPU_ ## sub | 0x2 << 6)
+  #define FPU_RA_IMMBI(sub)	(OP6 (sub) | __BIT (12))
+  {"fls",     "=fst,[%ra+(%rb<<%sv)]", FPU_MEM(FLS),	  4, ATTR (FPU), 0, NULL, 0, NULL},
+  {"fls",     "=fst,[%ra+%rb{<<%sv}]", FPU_MEM(FLS),	  4, ATTR (FPU), 0, NULL, 0, NULL},
+  {"fls.bi",  "=fst,[%ra],(%rb<<%sv)", FPU_MEMBI(FLS),	  4, ATTR (FPU), 0, NULL, 0, NULL},
+  {"fls.bi",  "=fst,[%ra],%rb{<<%sv}", FPU_MEMBI(FLS),	  4, ATTR (FPU), 0, NULL, 0, NULL},
+  {"fss",     "=fst,[%ra+(%rb<<%sv)]", FPU_MEM(FSS),	  4, ATTR (FPU), 0, NULL, 0, NULL},
+  {"fss",     "=fst,[%ra+%rb{<<%sv}]", FPU_MEM(FSS),	  4, ATTR (FPU), 0, NULL, 0, NULL},
+  {"fss.bi",  "=fst,[%ra],(%rb<<%sv)", FPU_MEMBI(FSS),	  4, ATTR (FPU), 0, NULL, 0, NULL},
+  {"fss.bi",  "=fst,[%ra],%rb{<<%sv}", FPU_MEMBI(FSS),	  4, ATTR (FPU), 0, NULL, 0, NULL},
+  {"fld",     "=fdt,[%ra+(%rb<<%sv)]", FPU_MEM(FLD),	  4, ATTR (FPU), 0, NULL, 0, NULL},
+  {"fld",     "=fdt,[%ra+%rb{<<%sv}]", FPU_MEM(FLD),	  4, ATTR (FPU), 0, NULL, 0, NULL},
+  {"fld.bi",  "=fdt,[%ra],(%rb<<%sv)", FPU_MEMBI(FLD),	  4, ATTR (FPU), 0, NULL, 0, NULL},
+  {"fld.bi",  "=fdt,[%ra],%rb{<<%sv}", FPU_MEMBI(FLD),	  4, ATTR (FPU), 0, NULL, 0, NULL},
+  {"fsd",     "=fdt,[%ra+(%rb<<%sv)]", FPU_MEM(FSD),	  4, ATTR (FPU), 0, NULL, 0, NULL},
+  {"fsd",     "=fdt,[%ra+%rb{<<%sv}]", FPU_MEM(FSD),	  4, ATTR (FPU), 0, NULL, 0, NULL},
+  {"fsd.bi",  "=fdt,[%ra],(%rb<<%sv)", FPU_MEMBI(FSD),	  4, ATTR (FPU), 0, NULL, 0, NULL},
+  {"fsd.bi",  "=fdt,[%ra],%rb{<<%sv}", FPU_MEMBI(FSD),	  4, ATTR (FPU), 0, NULL, 0, NULL},
+  {"flsi",    "=fst,[%ra{+%i12s2}]",   OP6(LWC),	  4, ATTR (FPU), 0, NULL, 0, NULL},
+  {"flsi.bi", "=fst,[%ra],%i12s2",     FPU_RA_IMMBI(LWC), 4, ATTR (FPU), 0, NULL, 0, NULL},
+  {"fssi",    "=fst,[%ra{+%i12s2}]",   OP6(SWC),	  4, ATTR (FPU), 0, NULL, 0, NULL},
+  {"fssi.bi", "=fst,[%ra],%i12s2",     FPU_RA_IMMBI(SWC), 4, ATTR (FPU), 0, NULL, 0, NULL},
+  {"fldi",    "=fdt,[%ra{+%i12s2}]",   OP6(LDC),	  4, ATTR (FPU), 0, NULL, 0, NULL},
+  {"fldi.bi", "=fdt,[%ra],%i12s2",     FPU_RA_IMMBI(LDC), 4, ATTR (FPU), 0, NULL, 0, NULL},
+  {"fsdi",    "=fdt,[%ra{+%i12s2}]",   OP6(SDC),	  4, ATTR (FPU), 0, NULL, 0, NULL},
+  {"fsdi.bi", "=fdt,[%ra],%i12s2",     FPU_RA_IMMBI(SDC), 4, ATTR (FPU), 0, NULL, 0, NULL},
+
+  /* AEXT */
+
+  {"lbi", "=rt,[%ra{+%i15s}]",			OP6 (LBI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"lhi", "=rt,[%ra{+%i15s1}]",			OP6 (LHI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"lwi", "=rt,[%ra{+%i15s2}]",			OP6 (LWI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"lbi.bi", "=rt,[%ra],%i15s",			OP6 (LBI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"lhi.bi", "=rt,[%ra],%i15s1",		OP6 (LHI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"lwi.bi", "=rt,[%ra],%i15s2",		OP6 (LWI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"sbi", "%rt,[%ra{+%i15s}]",			OP6 (SBI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"shi", "%rt,[%ra{+%i15s1}]",			OP6 (SHI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"swi", "%rt,[%ra{+%i15s2}]",			OP6 (SWI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"sbi.bi", "%rt,[%ra],%i15s",			OP6 (SBI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"shi.bi", "%rt,[%ra],%i15s1",		OP6 (SHI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"swi.bi", "%rt,[%ra],%i15s2",		OP6 (SWI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"lbsi", "=rt,[%ra{+%i15s}]",			OP6 (LBSI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"lhsi", "=rt,[%ra{+%i15s1}]",		OP6 (LHSI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"lwsi", "=rt,[%ra{+%i15s2}]",		OP6 (LWSI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"lbsi.bi", "=rt,[%ra],%i15s",		OP6 (LBSI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"lhsi.bi", "=rt,[%ra],%i15s1",		OP6 (LHSI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"lwsi.bi", "=rt,[%ra],%i15s2",		OP6 (LWSI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"cplwi", "%cp,=cprt,[%ra{+%i12s2}]",		OP6 (LWC), 4, 0, 0, NULL, 0, NULL},
+  {"cpswi", "%cp,=cprt,[%ra{+%i12s2}]",		OP6 (SWC), 4, 0, 0, NULL, 0, NULL},
+  {"cpldi", "%cp,%cprt,[%ra{+%i12s2}]",		OP6 (LDC), 4, 0, 0, NULL, 0, NULL},
+  {"cpsdi", "%cp,%cprt,[%ra{+%i12s2}]",		OP6 (SDC), 4, 0, 0, NULL, 0, NULL},
+  {"cplwi.bi", "%cp,=cprt,[%ra],%i12s2",	OP6 (LWC) | __BIT (12), 4, 0, 0, NULL, 0, NULL},
+  {"cpswi.bi", "%cp,=cprt,[%ra],%i12s2",	OP6 (SWC) | __BIT (12), 4, 0, 0, NULL, 0, NULL},
+  {"cpldi.bi", "%cp,%cprt,[%ra],%i12s2",	OP6 (LDC) | __BIT (12), 4, 0, 0, NULL, 0, NULL},
+  {"cpsdi.bi", "%cp,%cprt,[%ra],%i12s2",	OP6 (SDC) | __BIT (12), 4, 0, 0, NULL, 0, NULL},
+  {"movi", "=rt,%i20s",				OP6 (MOVI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"sethi", "=rt,%i20u",			OP6 (SETHI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"addi", "=rt,%ra,%i15s",			OP6 (ADDI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"subri", "=rt,%ra,%i15s",			OP6 (SUBRI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"andi", "=rt,%ra,%i15u",			OP6 (ANDI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"xori", "=rt,%ra,%i15u",			OP6 (XORI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"ori", "=rt,%ra,%i15u",			OP6 (ORI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"slti", "=rt,%ra,%i15s",			OP6 (SLTI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"sltsi", "=rt,%ra,%i15s",			OP6 (SLTSI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"bitci", "=rt,%ra,%i15u",			OP6 (BITCI), 4, ATTR_V3, 0, NULL, 0, NULL},
+  {"dprefi.w", "%dpref_st,[%ra{+%i15s2]}",	OP6 (DPREFI), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
+  {"dprefi.d", "%dpref_st,[%ra{+%i15s3]}",	OP6 (DPREFI) | __BIT (24), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
+
+  /* 16-bit instructions.  */
+  {"mov55", "=rt5,%ra5",		0x8000, 2, ATTR_ALL, 0, NULL, 0, NULL},	/* mov55, $sp, $sp == ifret */
+  {"ifret16", "",			0x83ff, 2, ATTR (IFC_EXT), 0, NULL, 0, NULL},
+  {"movi55", "=rt5,%i5s",		0x8400, 2, ATTR_ALL, 0, NULL, 0, NULL},
+  {"add45", "=rt4,%ra5",		0x8800, 2, ATTR_ALL, 0, NULL, 0, NULL},
+  {"sub45", "=rt4,%ra5",		0x8a00, 2, ATTR_ALL, 0, NULL, 0, NULL},
+  {"addi45", "=rt4,%i5u",		0x8c00, 2, ATTR_ALL, 0, NULL, 0, NULL},
+  {"subi45", "=rt4,%i5u",		0x8e00, 2, ATTR_ALL, 0, NULL, 0, NULL},
+  {"srai45", "=rt4,%i5u",		0x9000, 2, ATTR_ALL, 0, NULL, 0, NULL},
+  {"srli45", "=rt4,%i5u",		0x9200, 2, ATTR_ALL, 0, NULL, 0, NULL},
+  {"slli333", "=rt3,%ra3,%i3u",		0x9400, 2, ATTR_ALL, 0, NULL, 0, NULL},
+  {"zeb33", "=rt3,%ra3",		0x9600, 2, ATTR_ALL, 0, NULL, 0, NULL},
+  {"zeh33", "=rt3,%ra3",		0x9601, 2, ATTR_ALL, 0, NULL, 0, NULL},
+  {"seb33", "=rt3,%ra3",		0x9602, 2, ATTR_ALL, 0, NULL, 0, NULL},
+  {"seh33", "=rt3,%ra3",		0x9603, 2, ATTR_ALL, 0, NULL, 0, NULL},
+  {"xlsb33", "=rt3,%ra3",		0x9604, 2, ATTR_ALL, 0, NULL, 0, NULL},
+  {"x11b33", "=rt3,%ra3",		0x9605, 2, ATTR_ALL, 0, NULL, 0, NULL},
+  {"bmski33", "=rt3,%ia3u",		0x9606, 2, ATTR_V3MUP, 0, NULL, 0, NULL},
+  {"fexti33", "=rt3,%ia3u",		0x9607, 2, ATTR_V3MUP, 0, NULL, 0, NULL},
+  {"add333", "=rt3,%ra3,%rb3",		0x9800, 2, ATTR_ALL, 0, NULL, 0, NULL},
+  {"sub333", "=rt3,%ra3,%rb3",		0x9a00, 2, ATTR_ALL, 0, NULL, 0, NULL},
+  {"addi333", "=rt3,%ra3,%i3u",		0x9c00, 2, ATTR_ALL, 0, NULL, 0, NULL},
+  {"subi333", "=rt3,%ra3,%i3u",		0x9e00, 2, ATTR_ALL, 0, NULL, 0, NULL},
+  {"lwi333", "=rt3,[%ra3{+%i3u2}]",	0xa000, 2, ATTR_ALL, 0, NULL, 0, NULL},
+  {"lwi333.bi", "=rt3,[%ra3],%i3u2",	0xa200, 2, ATTR_ALL, 0, NULL, 0, NULL},
+  {"lhi333", "=rt3,[%ra3{+%i3u1}]",	0xa400, 2, ATTR_ALL, 0, NULL, 0, NULL},
+  {"lbi333", "=rt3,[%ra3{+%i3u}]",	0xa600, 2, ATTR_ALL, 0, NULL, 0, NULL},
+  {"swi333", "%rt3,[%ra3{+%i3u2}]",	0xa800, 2, ATTR_ALL, 0, NULL, 0, NULL},
+  {"swi333.bi", "%rt3,[%ra3],%i3u2",	0xaa00, 2, ATTR_ALL, 0, NULL, 0, NULL},
+  {"shi333", "%rt3,[%ra3{+%i3u1}]",	0xac00, 2, ATTR_ALL, 0, NULL, 0, NULL},
+  {"sbi333", "%rt3,[%ra3{+%i3u}]",	0xae00, 2, ATTR_ALL, 0, NULL, 0, NULL},
+  {"addri36.sp", "%rt3,%i6u2",		0xb000, 2, ATTR_V3MUP, USE_REG (31), NULL, 0, NULL},
+  {"lwi45.fe", "=rt4,%fe5",		0xb200, 2, ATTR_V3MUP, USE_REG (8), NULL, 0, NULL},
+  {"lwi450", "=rt4,[%ra5]",		0xb400, 2, ATTR_ALL, 0, NULL, 0, NULL},
+  {"swi450", "%rt4,[%ra5]",		0xb600, 2, ATTR_ALL, 0, NULL, 0, NULL},
+  {"lwi37", "=rt38,[$fp{+%i7u2}]",	0xb800, 2, ATTR_ALL, USE_REG (28), NULL, 0, NULL},
+  {"swi37", "%rt38,[$fp{+%i7u2}]",	0xb880, 2, ATTR_ALL, USE_REG (28), NULL, 0, NULL},
+  {"beqz38", "%rt38,%i8s1",		0xc000, 2, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
+  {"bnez38", "%rt38,%i8s1",		0xc800, 2, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
+  {"beqs38", "%rt38,%i8s1",		0xd000, 2, ATTR_PCREL | ATTR_ALL, USE_REG (5), NULL, 0, NULL},
+  {"j8", "%i8s1",			0xd500, 2, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
+  {"bnes38", "%rt38,%i8s1",		0xd800, 2, ATTR_PCREL | ATTR_ALL, USE_REG (5), NULL, 0, NULL},
+  {"jr5", "%ra5",			0xdd00, 2, ATTR_ALL, 0, NULL, 0, NULL},
+  {"ex9.it", "%i5u",			0xdd40, 2, ATTR (EX9_EXT), 0, NULL, 0, NULL},
+  {"ret5", "%ra5",			0xdd80, 2, ATTR_ALL, 0, NULL, 0, NULL},
+  {"ret5", "",				0xdd80 | RA5 (30), 2, ATTR_ALL, 0, NULL, 0, NULL},
+  {"jral5", "%ra5",			0xdd20, 2, ATTR_ALL, 0, NULL, 0, NULL},
+  {"add5.pc", "%ra5",			0xdda0, 2, ATTR_V3, 0, NULL, 0, NULL},
+  {"slts45", "%rt4,%ra5",		0xe000, 2, ATTR_ALL, DEF_REG (15), NULL, 0, NULL},
+  {"slt45", "%rt4,%ra5",		0xe200, 2, ATTR_ALL, DEF_REG (15), NULL, 0, NULL},
+  {"sltsi45", "%rt4,%i5u",		0xe400, 2, ATTR_ALL, DEF_REG (15), NULL, 0, NULL},
+  {"slti45", "%rt4,%i5u",		0xe600, 2, ATTR_ALL, DEF_REG (15), NULL, 0, NULL},
+  {"beqzs8", "%i8s1",			0xe800, 2, ATTR_PCREL | ATTR_ALL, USE_REG (5), NULL, 0, NULL},
+  {"bnezs8", "%i8s1",			0xe900, 2, ATTR_PCREL | ATTR_ALL, USE_REG (5), NULL, 0, NULL},
+  {"ex9.it", "%i9u",			0xea00, 2, ATTR (EX9_EXT), 0, NULL, 0, NULL},
+  {"break16", "%i9u",			0xea00, 2, ATTR_ALL, 0, NULL, 0, NULL},
+  {"addi10.sp", "%i10s",		0xec00, 2, ATTR_V2UP, USE_REG (31) | DEF_REG (31), NULL, 0, NULL},
+  {"lwi37.sp", "=rt38,[+%i7u2]",	0xf000, 2, ATTR_V2UP, USE_REG (31), NULL, 0, NULL},
+  {"swi37.sp", "%rt38,[+%i7u2]",	0xf080, 2, ATTR_V2UP, USE_REG (31), NULL, 0, NULL},
+  {"ifcall9", "%i9u1",			0xf800, 2, ATTR (IFC_EXT), 0, NULL, 0, NULL},
+  {"movpi45", "=rt4,%pi5",		0xfa00, 2, ATTR_V3MUP, 0, NULL, 0, NULL},
+  {"push25", "%re2,%i5u3",		0xfc00, 2, ATTR_V3MUP, USE_REG (31) | DEF_REG (31), NULL, 0, NULL},
+  {"pop25", "%re2,%i5u3",		0xfc80, 2, ATTR_V3MUP, USE_REG (31) | DEF_REG (31), NULL, 0, NULL},
+  {"movd44", "=rt5e,%ra5e",		0xfd00, 2, ATTR_V3MUP, 0, NULL, 0, NULL},
+  {"neg33", "=rt3,%ra3",		0xfe02, 2, ATTR_V3MUP, 0, NULL, 0, NULL},
+  {"not33", "=rt3,%ra3",		0xfe03, 2, ATTR_V3MUP, 0, NULL, 0, NULL},
+  {"mul33", "=rt3,%ra3",		0xfe04, 2, ATTR_V3MUP, 0, NULL, 0, NULL},
+  {"xor33", "=rt3,%ra3",		0xfe05, 2, ATTR_V3MUP, 0, NULL, 0, NULL},
+  {"and33", "=rt3,%ra3",		0xfe06, 2, ATTR_V3MUP, 0, NULL, 0, NULL},
+  {"or33", "=rt3,%ra3",			0xfe07, 2, ATTR_V3MUP, 0, NULL, 0, NULL},
+
+  /* Alias instructions.  */
+  {"neg", "=rt,%ra",			OP6 (SUBRI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"zeb", "=rt,%ra",			OP6 (ANDI) | 0xff, 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"nop", "",				ALU1 (SRLI), 4, ATTR_ALL, 0, NULL, 0, NULL},
+  {"nop16", "",				0x9200, 2, ATTR_ALL, 0, NULL, 0, NULL},
+
+  /* TODO: For some instruction, an operand may refer to a pair of
+	   register, e.g., mulsr64 or movd44.
+
+     Some instruction need special constrain, e.g., movpi45,
+	  break16, ex9.it. */
+};
+
+static const keyword_t keyword_gpr[] =
+{
+  {"r0", 0, ATTR (RDREG)}, {"r1", 1, ATTR (RDREG)}, {"r2", 2, ATTR (RDREG)},
+  {"r3", 3, ATTR (RDREG)}, {"r4", 4, ATTR (RDREG)}, {"r5", 5, ATTR (RDREG)},
+  {"r6", 6, ATTR (RDREG)}, {"r7", 7, ATTR (RDREG)}, {"r8", 8, ATTR (RDREG)},
+  {"r9", 9, ATTR (RDREG)}, {"r10", 10, ATTR (RDREG)},
+  {"r11", 11, 0}, {"r12", 12, 0}, {"r13", 13, 0}, {"r14", 14, 0},
+  {"r15", 15, ATTR (RDREG)},
+  {"r16", 16, 0}, {"r17", 17, 0}, {"r18", 18, 0}, {"r19", 19, 0}, {"r20", 20, 0},
+  {"r21", 21, 0}, {"r22", 22, 0}, {"r23", 23, 0}, {"r24", 24, 0}, {"r25", 25, 0},
+  {"r26", 26, 0}, {"r27", 27, 0},
+  {"r28", 28, ATTR (RDREG)}, {"r29", 29, ATTR (RDREG)},
+  {"r30", 30, ATTR (RDREG)}, {"r31", 31, ATTR (RDREG)},
+
+  {"ta", 15, ATTR (RDREG)}, {"p0", 26, 0}, {"p1", 27, 0},
+  {"fp", 28, ATTR (RDREG)}, {"gp", 29, ATTR (RDREG)},
+  {"lp", 30, ATTR (RDREG)}, {"sp", 31, ATTR (RDREG)},
+
+  {NULL, 0, 0}
+};
+
+static const keyword_t keyword_usr[] =
+{
+  {"d0.lo", USRIDX (0, 0), 0},
+  {"d0.hi", USRIDX (0, 1), 0},
+  {"d1.lo", USRIDX (0, 2), 0},
+  {"d1.hi", USRIDX (0, 3), 0},
+  {"itb", USRIDX (0, 28), 0},
+  {"ifc_lp", USRIDX (0, 29), 0},
+  {"pc", USRIDX (0, 31), 0},
+
+  {"dma_cfg", USRIDX (1, 0), 0},
+  {"dma_gcsw", USRIDX (1, 1), 0},
+  {"dma_chnsel", USRIDX (1, 2), 0},
+  {"dma_act", USRIDX (1, 3), 0},
+  {"dma_setup", USRIDX (1, 4), 0},
+  {"dma_isaddr", USRIDX (1, 5), 0},
+  {"dma_esaddr", USRIDX (1, 6), 0},
+  {"dma_tcnt", USRIDX (1, 7), 0},
+  {"dma_status", USRIDX (1, 8), 0},
+  {"dma_2dset", USRIDX (1, 9), 0},
+  {"dma_rcnt", USRIDX (1, 23), 0},
+  {"dma_hstatus", USRIDX (1, 24), 0},
+  {"dma_2dsctl", USRIDX (1, 25), 0},
+
+  {"pfmc0", USRIDX (2, 0), 0},
+  {"pfmc1", USRIDX (2, 1), 0},
+  {"pfmc2", USRIDX (2, 2), 0},
+  {"pfm_ctl", USRIDX (2, 4), 0},
+
+  {NULL, 0, 0}
+};
+
+static const keyword_t keyword_dxr[] =
+{
+  {"d0", 0, 0}, {"d1", 1, 0}, {NULL, 0, 0}
+};
+
+static const keyword_t keyword_sr[] =
+{
+  {"cr0", SRIDX (0, 0, 0), 0}, {"cpu_ver", SRIDX (0, 0, 0), 0},
+  {"cr1", SRIDX (0, 1, 0), 0}, {"icm_cfg", SRIDX (0, 1, 0), 0},
+  {"cr2", SRIDX (0, 2, 0), 0}, {"dcm_cfg", SRIDX (0, 2, 0), 0},
+  {"cr3", SRIDX (0, 3, 0), 0}, {"mmu_cfg", SRIDX (0, 3, 0), 0},
+  {"cr4", SRIDX (0, 4, 0), 0}, {"msc_cfg", SRIDX (0, 4, 0), 0},
+  {"cr5", SRIDX (0, 0, 1), 0}, {"core_id", SRIDX (0, 0, 1), 0},
+  {"cr6", SRIDX (0, 5, 0), 0}, {"fucop_exist", SRIDX (0, 5, 0), 0},
+
+  {"ir0", SRIDX (1, 0, 0), 0}, {"psw", SRIDX (1, 0, 0), 0},
+  {"ir1", SRIDX (1, 0, 1), 0}, {"ipsw", SRIDX (1, 0, 1), 0},
+  {"ir2", SRIDX (1, 0, 2), 0}, {"p_ipsw", SRIDX (1, 0, 2), 0},
+  {"ir3", SRIDX (1, 1, 1), 0}, {"ivb", SRIDX (1, 1, 1), 0},
+  {"ir4", SRIDX (1, 2, 1), 0}, {"p_eva", SRIDX (1, 2, 2), 0},
+  {"ir5", SRIDX (1, 2, 2), 0}, {"eva", SRIDX (1, 2, 1), 0},
+  {"ir6", SRIDX (1, 3, 1), 0}, {"itype", SRIDX (1, 3, 1), 0},
+  {"ir7", SRIDX (1, 3, 2), 0}, {"p_itype", SRIDX (1, 3, 2), 0},
+  {"ir8", SRIDX (1, 4, 1), 0}, {"merr", SRIDX (1, 4, 1), 0},
+  {"ir9", SRIDX (1, 5, 1), 0}, {"ipc", SRIDX (1, 5, 1), 0},
+  {"ir10", SRIDX (1, 5, 2), 0}, {"p_ipc", SRIDX (1, 5, 2), 0},
+  {"ir11", SRIDX (1, 5, 3), 0}, {"oipc", SRIDX (1, 5, 3), 0},
+  {"ir12", SRIDX (1, 6, 2), 0}, {"p_p0", SRIDX (1, 6, 2), 0},
+  {"ir13", SRIDX (1, 7, 2), 0}, {"p_p1", SRIDX (1, 7, 2), 0},
+  {"ir14", SRIDX (1, 8, 0), 0}, {"int_mask", SRIDX (1, 8, 0), 0},
+  {"ir15", SRIDX (1, 9, 0), 0}, {"int_pend", SRIDX (1, 9, 0), 0},
+  {"ir16", SRIDX (1, 10, 0), 0}, {"sp_usr", SRIDX (1, 10, 0), 0},
+  {"ir17", SRIDX (1, 10, 1), 0}, {"sp_priv", SRIDX (1, 10, 1), 0},
+  {"ir18", SRIDX (1, 11, 0), 0}, {"int_pri", SRIDX (1, 11, 0), 0},
+  {"ir19", SRIDX (1, 1, 2), 0}, {"int_ctrl", SRIDX (1, 1, 2), 0},
+  {"ir20", SRIDX (1, 10, 2), 0}, {"sp_usr1", SRIDX (1, 10, 2), 0},
+  {"ir21", SRIDX (1, 10, 3), 0}, {"sp_priv1", SRIDX (1, 10, 3), 0},
+  {"ir22", SRIDX (1, 10, 4), 0}, {"sp_usr2", SRIDX (1, 10, 4), 0},
+  {"ir23", SRIDX (1, 10, 5), 0}, {"sp_priv2", SRIDX (1, 10, 5), 0},
+  {"ir24", SRIDX (1, 10, 6), 0}, {"sp_usr3", SRIDX (1, 10, 6), 0},
+  {"ir25", SRIDX (1, 10, 7), 0}, {"sp_priv3", SRIDX (1, 10, 7), 0},
+  {"ir26", SRIDX (1, 8, 1), 0}, {"int_mask2", SRIDX (1, 8, 1), 0},
+  {"ir27", SRIDX (1, 9, 1), 0}, {"int_pend2", SRIDX (1, 9, 1), 0},
+  {"ir28", SRIDX (1, 11, 1), 0}, {"int_pri2", SRIDX (1, 11, 1), 0},
+  {"ir29", SRIDX (1, 9, 4), 0}, {"int_trigger", SRIDX (1, 9, 4), 0},
+  {"ir30", SRIDX (1, 1, 3), 0},
+
+  {"mr0", SRIDX (2, 0, 0), 0}, {"mmu_ctl", SRIDX (2, 0, 0), 0},
+  {"mr1", SRIDX (2, 1, 0), 0}, {"l1_pptb", SRIDX (2, 1, 0), 0},
+  {"mr2", SRIDX (2, 2, 0), 0}, {"tlb_vpn", SRIDX (2, 2, 0), 0},
+  {"mr3", SRIDX (2, 3, 0), 0}, {"tlb_data", SRIDX (2, 3, 0), 0},
+  {"mr4", SRIDX (2, 4, 0), 0}, {"tlb_misc", SRIDX (2, 4, 0), 0},
+  {"mr5", SRIDX (2, 5, 0), 0}, {"vlpt_idx", SRIDX (2, 5, 0), 0},
+  {"mr6", SRIDX (2, 6, 0), 0}, {"ilmb", SRIDX (2, 6, 0), 0},
+  {"mr7", SRIDX (2, 7, 0), 0}, {"dlmb", SRIDX (2, 7, 0), 0},
+  {"mr8", SRIDX (2, 8, 0), 0}, {"cache_ctl", SRIDX (2, 8, 0), 0},
+  {"mr9", SRIDX (2, 9, 0), 0}, {"hsmp_saddr", SRIDX (2, 9, 0), 0},
+  {"mr10", SRIDX (2, 9, 1), 0}, {"hsmp_eaddr", SRIDX (2, 9, 1), 0},
+  {"mr11", SRIDX (2, 0, 1), 0}, {"bg_region", SRIDX (2, 0, 1), 0},
+
+  {"pfr0", SRIDX (4, 0, 0), 0}, {"pfmc0", SRIDX (4, 0, 0), 0},
+  {"pfr1", SRIDX (4, 0, 1), 0}, {"pfmc1", SRIDX (4, 0, 1), 0},
+  {"pfr2", SRIDX (4, 0, 2), 0}, {"pfmc2", SRIDX (4, 0, 2), 0},
+  {"pfr3", SRIDX (4, 1, 0), 0}, {"pfm_ctl", SRIDX (4, 1, 0), 0},
+
+  {"dmar0", SRIDX (5, 0, 0), 0}, {"dma_cfg", SRIDX (5, 0, 0), 0},
+  {"dmar1", SRIDX (5, 1, 0), 0}, {"dma_gcsw", SRIDX (5, 1, 0), 0},
+  {"dmar2", SRIDX (5, 2, 0), 0}, {"dma_chnsel", SRIDX (5, 2, 0), 0},
+  {"dmar3", SRIDX (5, 3, 0), 0}, {"dma_act", SRIDX (5, 3, 0), 0},
+  {"dmar4", SRIDX (5, 4, 0), 0}, {"dma_setup", SRIDX (5, 4, 0), 0},
+  {"dmar5", SRIDX (5, 5, 0), 0}, {"dma_isaddr", SRIDX (5, 5, 0), 0},
+  {"dmar6", SRIDX (5, 6, 0), 0}, {"dma_esaddr", SRIDX (5, 6, 0), 0},
+  {"dmar7", SRIDX (5, 7, 0), 0}, {"dma_tcnt", SRIDX (5, 7, 0), 0},
+  {"dmar8", SRIDX (5, 8, 0), 0}, {"dma_status", SRIDX (5, 8, 0), 0},
+  {"dmar9", SRIDX (5, 9, 0), 0}, {"dma_2dset", SRIDX (5, 9, 0), 0},
+  {"dmar10", SRIDX (5, 9, 1), 0}, {"dma_2dsctl", SRIDX (5, 9, 1), 0},
+  {"dmar11", SRIDX (5, 7, 1), 0}, {"dma_rcnt", SRIDX (5, 7, 1), 0},
+  {"dmar12", SRIDX (5, 8, 1), 0}, {"dma_hstatus", SRIDX (5, 8, 1), 0},
+
+  {"idr0", SRIDX (2, 15, 0), 0}, {"sdz_ctl", SRIDX (2, 15, 0), 0},
+  {"idr1", SRIDX (2, 15, 1), 0}, {"n12misc_ctl", SRIDX (2, 15, 1), 0},
+			      {"misc_ctl", SRIDX (2, 15, 1), 0},
+
+  {"secur0", SRIDX (6, 0, 0), 0}, {"sfcr", SRIDX (6, 0, 0), 0},
+
+  {"prusr_acc_ctl", SRIDX (4, 4, 0), 0},
+  {"fucpr", SRIDX (4, 5, 0), 0}, {"fucop_ctl", SRIDX (4, 5, 0), 0},
+
+  {NULL,0 ,0}
+};
+
+static const keyword_t keyword_cp[] =
+{
+  {"cp0", 0, 0}, {"cp1", 1, 0}, {"cp2", 2, 0}, {"cp3", 3, 0}, {NULL, 0, 0}
+};
+
+static const keyword_t keyword_cpr[] =
+{
+  {"cpr0", 0, 0}, {"cpr1", 1, 0}, {"cpr2", 2, 0}, {"cpr3", 3, 0}, {"cpr4", 4, 0},
+  {"cpr5", 5, 0}, {"cpr6", 6, 0}, {"cpr7", 7, 0}, {"cpr8", 8, 0}, {"cpr9", 9, 0},
+  {"cpr10", 10, 0}, {"cpr11", 11, 0}, {"cpr12", 12, 0}, {"cpr13", 13, 0},
+  {"cpr14", 14, 0}, {"cpr15", 15, 0}, {"cpr16", 16, 0}, {"cpr17", 17, 0},
+  {"cpr18", 18, 0}, {"cpr19", 19, 0}, {"cpr20", 20, 0}, {"cpr21", 21, 0},
+  {"cpr22", 22, 0}, {"cpr23", 23, 0}, {"cpr24", 24, 0}, {"cpr25", 25, 0},
+  {"cpr26", 26, 0}, {"cpr27", 27, 0}, {"cpr28", 28, 0}, {"cpr29", 29, 0},
+  {"cpr30", 30, 0}, {"cpr31", 31, 0}, {NULL, 0, 0}
+};
+
+static const keyword_t keyword_fsr[] =
+{
+  {"fs0", 0, 0}, {"fs1", 1, 0}, {"fs2", 2, 0}, {"fs3", 3, 0}, {"fs4", 4, 0},
+  {"fs5", 5, 0}, {"fs6", 6, 0}, {"fs7", 7, 0}, {"fs8", 8, 0}, {"fs9", 9, 0},
+  {"fs10", 10, 0}, {"fs11", 11, 0}, {"fs12", 12, 0}, {"fs13", 13, 0},
+  {"fs14", 14, 0}, {"fs15", 15, 0}, {"fs16", 16, 0}, {"fs17", 17, 0},
+  {"fs18", 18, 0}, {"fs19", 19, 0}, {"fs20", 20, 0}, {"fs21", 21, 0},
+  {"fs22", 22, 0}, {"fs23", 23, 0}, {"fs24", 24, 0}, {"fs25", 25, 0},
+  {"fs26", 26, 0}, {"fs27", 27, 0}, {"fs28", 28, 0}, {"fs29", 29, 0},
+  {"fs30", 30, 0}, {"fs31", 31, 0}, {NULL, 0 ,0}
+};
+
+static const keyword_t keyword_fdr[] =
+{
+  {"fd0", 0, 0}, {"fd1", 1, 0}, {"fd2", 2, 0}, {"fd3", 3, 0}, {"fd4", 4, 0},
+  {"fd5", 5, 0}, {"fd6", 6, 0}, {"fd7", 7, 0}, {"fd8", 8, 0}, {"fd9", 9, 0},
+  {"fd10", 10, 0}, {"fd11", 11, 0}, {"fd12", 12, 0}, {"fd13", 13, 0},
+  {"fd14", 14, 0}, {"fd15", 15, 0}, {"fd16", 16, 0}, {"fd17", 17, 0},
+  {"fd18", 18, 0}, {"fd19", 19, 0}, {"fd20", 20, 0}, {"fd21", 21, 0},
+  {"fd22", 22, 0}, {"fd23", 23, 0}, {"fd24", 24, 0}, {"fd25", 25, 0},
+  {"fd26", 26, 0}, {"fd27", 27, 0}, {"fd28", 28, 0}, {"fd29", 29, 0},
+  {"fd30", 30, 0}, {"fd31", 31, 0}, {NULL, 0, 0}
+};
+
+static const keyword_t keyword_abdim[] =
+{
+  {"bi", 0, 0}, {"bim", 1, 0}, {"bd", 2, 0}, {"bdm", 3, 0},
+  {"ai", 4, 0}, {"aim", 5, 0}, {"ad", 6, 0}, {"adm", 7, 0},
+  {NULL, 0, 0}
+};
+
+static const keyword_t keyword_abm[] =
+{
+  {"b", 0, 0}, {"bm", 1, 0}, {"a", 4, 0}, {"am", 5, 0}, {NULL, 0, 0}
+};
+
+static const keyword_t keyword_dtiton[] =
+{
+  {"iton", 1, 0}, {"ton", 3, 0}, {NULL, 0, 0}
+};
+
+static const keyword_t keyword_dtitoff[] =
+{
+  {"itoff", 1, 0}, {"toff", 3, 0}, {NULL, 0, 0}
+};
+
+static const keyword_t keyword_dpref_st[] =
+{
+  {"srd", 0, 0}, {"mrd", 1, 0}, {"swr", 2, 0}, {"mwr", 3, 0},
+  {"pte", 4, 0}, {"clwr", 5, 0}, {NULL, 0, 0}
+};
+
+/* CCTL Ra, SubType */
+static const keyword_t keyword_cctl_st0[] =
+{
+  {"l1d_ix_inval", 0X0, 0}, {"l1d_ix_wb", 0X1, 0}, {"l1d_ix_wbinval", 0X2, 0},
+  {"l1d_va_fillck", 0XB, 0}, {"l1d_va_ulck", 0XC, 0}, {"l1i_ix_inval", 0X10, 0},
+  {"l1i_va_fillck", 0X1B, 0}, {"l1i_va_ulck", 0X1C, 0},
+  {NULL, 0, 0}
+};
+
+/* CCTL Ra, SubType, level */
+static const keyword_t keyword_cctl_st1[] =
+{
+  {"l1d_va_inval", 0X8, 0}, {"l1d_va_wb", 0X9, 0},
+  {"l1d_va_wbinval", 0XA, 0}, {"l1i_va_inval", 0X18, 0},
+  {NULL, 0, 0}
+};
+
+/* CCTL Rt, Ra, SubType */
+static const keyword_t keyword_cctl_st2[] =
+{
+  {"l1d_ix_rtag", 0X3, 0}, {"l1d_ix_rwd", 0X4, 0},
+  {"l1i_ix_rtag", 0X13, 0}, {"l1i_ix_rwd", 0X14, 0},
+  {NULL, 0, 0}
+};
+
+/* CCTL Rb, Ra, SubType */
+static const keyword_t keyword_cctl_st3[] =
+{
+  {"l1d_ix_wtag", 0X5, 0}, {"l1d_ix_wwd", 0X6, 0},
+  {"l1i_ix_wtag", 0X15, 0}, {"l1i_ix_wwd", 0X16, 0},
+  {NULL, 0, 0}
+};
+
+/* CCTL L1D_INVALALL */
+static const keyword_t keyword_cctl_st4[] =
+{
+  {"l1d_invalall", 0x7, 0}, {NULL, 0, 0}
+};
+
+/* CCTL L1D_WBALL, level */
+static const keyword_t keyword_cctl_st5[] =
+{
+  {"l1d_wball", 0xf, 0}, {NULL, 0, 0}
+};
+
+static const keyword_t keyword_cctl_lv[] =
+{
+  {"1level", 0, 0}, {"alevel", 1, 0}, {"0", 0, 0}, {"1", 1, 0},
+  {NULL, 0, 0},
+};
+
+static const keyword_t keyword_tlbop_st[] =
+{
+  {"trd", 0, 0}, {"targetread", 0, 0},
+  {"twr", 1, 0}, {"targetwrite", 1, 0},
+  {"rwr", 2, 0}, {"rwrite", 2, 0},
+  {"rwlk", 3, 0}, {"rwritelock", 3, 0},
+  {"unlk", 4, 0}, {"unlock", 4, 0},
+  {"inv", 6, 0}, {"invalidate", 6, 0},
+  {NULL, 0, 0},
+  /* "pb" requries two operand and "flua" requires none.  */
+  /* {"pb", 5, 0}, {"probe", 5, 0},
+     {"flua", 7, 0}, {"flushall", 0}, */
+};
+
+static const keyword_t keyword_standby_st[] =
+{
+  {"no_wake_grant", 0, 0},
+  {"wake_grant", 1, 0},
+  {"wait_done", 2, 0},
+  {"0", 0, 0},
+  {"1", 1, 0},
+  {"2", 2, 0},
+  {"3", 3, 0},
+  {NULL, 0, 0},
+};
+
+static const keyword_t keyword_msync_st[] =
+{
+  {"all", 0, 0}, {"store", 1, 0},
+  {NULL, 0, 0}
+};
+
+
+/* Hash table for syntax lex.   */
+static htab_t field_htab;
+/* Hash table for opcodes.  */
+static htab_t opcode_htab;
+/* Hash table for hardware resources.  */
+static htab_t hw_ktabs[_HW_LAST];
+
+static hashval_t
+htab_hash_hash (const void *p)
+{
+  struct nds32_hash_entry *h = (struct nds32_hash_entry *) p;
+
+  return htab_hash_string (h->name);
+}
+
+static int
+htab_hash_eq (const void *p, const void *q)
+{
+  struct nds32_hash_entry *h = (struct nds32_hash_entry *) p;
+  const char *name = (const char *) q;
+
+  return strcmp (name, h->name) == 0;
+}
+
+
+/* Build a hash table for array BASE.  Each element is in size of SIZE,
+   and it's first element is a pointer to the key of string.
+   It stops inserting elements until reach an NULL key.  */
+
+static htab_t
+build_hash_table (const void *base, size_t size)
+{
+  htab_t htab;
+  hashval_t hash;
+  const char *p;
+
+  htab = htab_create_alloc (128, htab_hash_hash, htab_hash_eq,
+			    NULL, xcalloc, free);
+
+  p = base;
+  while (1)
+    {
+      struct nds32_hash_entry **slot;
+      struct nds32_hash_entry *h;
+
+      h = (struct nds32_hash_entry *) p;
+
+      if (h->name == NULL)
+	break;
+
+      hash = htab_hash_string (h->name);
+      slot = (struct nds32_hash_entry **)
+	htab_find_slot_with_hash (htab, h->name, hash, INSERT);
+
+      assert (slot != NULL && *slot == NULL);
+
+      *slot = h;
+
+      p = p + size;
+    }
+
+  return htab;
+}
+
+/* Build the syntax for a given opcode OPC.  It parses the string
+   pointed by INSTRUCTION and store the result on SYNTAX, so
+   when we assemble an instruction, we don't have to parse the syntax
+   again.  */
+
+static void
+build_opcode_syntax (struct nds32_opcode *opc)
+{
+  char odstr[MAX_LEX_LEN];
+  const char *str;
+  const char *end;
+  lex_t *plex;
+  int len;
+  hashval_t hash;
+  field_t *fd;
+  int opt = 0;
+
+  /* Check whether it has been initialized.  */
+  if (opc->syntax)
+    return;
+
+  opc->syntax = xmalloc (MAX_LEX_NUM * sizeof (lex_t));
+
+  str = opc->instruction;
+  plex = opc->syntax;
+  while (*str)
+    {
+      int fidx;
+
+      switch (*str)
+	{
+	case '%': *plex = SYN_INPUT; break;
+	case '=': *plex = SYN_OUTPUT; break;
+	case '&': *plex = SYN_INPUT | SYN_OUTPUT; break;
+	case '{':
+	  *plex++ = SYN_LOPT;
+	  opt++;
+	  str++;
+	  continue;
+	case '}':
+	  *plex++ = SYN_ROPT;
+	  str++;
+	  continue;
+	default:
+	  *plex++ = *str++;
+	  continue;
+	}
+      str++;
+
+      /* Extract operand.  */
+      end = str;
+      while (ISALNUM (*end) || *end == '_')
+	end++;
+      len = end - str;
+      memcpy (odstr, str, len);
+      odstr[len] = '\0';
+
+      hash = htab_hash_string (odstr);
+      fd = (field_t *) htab_find_with_hash (field_htab, odstr, hash);
+      fidx = fd - operand_fields;
+
+      if (fd == NULL)
+	{
+	  fprintf (stderr, "Internal error: Unknown operand, %s\n", str);
+	}
+      assert (fd && fidx >= 0 && fidx < (int) ARRAY_SIZE (operand_fields));
+      *plex |= LEX_SET_FIELD (fidx);
+
+      str += len;
+      plex++;
+    }
+
+  *plex = 0;
+  opc->variant = opt;
+  return;
+
+  fprintf (stderr, "Unknown lex in assembly syntax, %s.\n", str);
+  abort ();
+}
+
+/* Initialize the assembler.  It must be called before assembling.  */
+
+void
+nds32_asm_init (nds32_asm_desc_t *pdesc, int flags)
+{
+  int i;
+  hashval_t hash;
+  const keyword_t *keywords[_HW_LAST] =
+  {
+    keyword_gpr, keyword_usr, keyword_dxr, keyword_sr, keyword_fsr,
+    keyword_fdr, keyword_cp, keyword_cpr, keyword_abdim, keyword_abm,
+    keyword_dtiton, keyword_dtitoff, keyword_dpref_st,
+    keyword_cctl_st0, keyword_cctl_st1, keyword_cctl_st2,
+    keyword_cctl_st3, keyword_cctl_st4, keyword_cctl_st5,
+    keyword_cctl_lv, keyword_tlbop_st, keyword_standby_st,
+    keyword_msync_st,
+  };
+
+  pdesc->flags = flags;
+  pdesc->mach = flags & NASM_OPEN_ARCH_MASK;
+
+  /* Build keyword tables.  */
+  field_htab = build_hash_table (operand_fields,
+				 sizeof (operand_fields[0]));
+
+  for (i = 0; i < _HW_LAST; i++)
+    hw_ktabs[i] = build_hash_table (keywords[i], sizeof (keyword_t));
+
+  /* Build opcode table.  */
+  opcode_htab = htab_create_alloc (128, htab_hash_hash, htab_hash_eq,
+				   NULL, xcalloc, free);
+
+  for (i = 0; i < (int) ARRAY_SIZE (nds32_opcodes); i++)
+    {
+      struct nds32_opcode **slot;
+      struct nds32_opcode *opc;
+
+      opc = &nds32_opcodes[i];
+
+      hash = htab_hash_string (opc->opcode);
+      slot = (struct nds32_opcode **)
+	htab_find_slot_with_hash (opcode_htab, opc->opcode, hash, INSERT);
+
+#define NDS32_PREINIT_SYNTAX
+#if defined (NDS32_PREINIT_SYNTAX)
+      /* Initial SYNTAX when build opcode table, so bug in syntax can be
+	 found when initialized rather than used.  */
+      build_opcode_syntax (opc);
+#endif
+
+      if (*slot == NULL)
+	{
+	  /* This is the new one.  */
+	  *slot = opc;
+	}
+      else
+	{
+	  /* Already exists.  Append to the list.  */
+	  opc = *slot;
+	  while (opc->next)
+	    opc = opc->next;
+	  opc->next = &nds32_opcodes[i];
+	}
+    }
+}
+
+/* Parse the input and store operand keyword string in ODSTR.
+   This function is only used for parsing keywords,
+   HW_INT/HW_UINT are parsed parse_operand callback handler.  */
+
+static char *
+parse_to_delimiter (char *str, char odstr[MAX_KEYWORD_LEN])
+{
+  char *outp = odstr;
+
+  while (ISALNUM (*str) || *str == '.' || *str == '_')
+    *outp++ = TOLOWER (*str++);
+
+  *outp = '\0';
+  return str;
+}
+
+/* Parse the operand of push25/pop25.  */
+
+static int
+parse_re2 (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED,
+	   struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED,
+	   char **pstr, int64_t *value)
+{
+  char *end = *pstr;
+  char odstr[MAX_KEYWORD_LEN];
+  keyword_t *k;
+  hashval_t hash;
+
+  if (*end == '$')
+    end++;
+  end = parse_to_delimiter (end, odstr);
+
+  hash = htab_hash_string (odstr);
+  k = htab_find_with_hash (hw_ktabs[HW_GPR], odstr, hash);
+
+  if (k == NULL)
+    return NASM_ERR_OPERAND;
+
+  if (k->value == 6)
+    *value = 0;
+  else if (k->value == 8)
+    *value = 1;
+  else if (k->value == 10)
+    *value = 2;
+  else if (k->value == 14)
+    *value = 3;
+  else
+    return NASM_ERR_OPERAND;
+
+  *pstr = end;
+  return NASM_R_CONST;
+}
+
+/* Parse the operand of lwi45.fe.  */
+
+static int
+parse_fe5 (struct nds32_asm_desc *pdesc, struct nds32_asm_insn *pinsn,
+	   char **pstr, int64_t *value)
+{
+  int r;
+
+  r = pdesc->parse_operand (pdesc, pinsn, pstr, value);
+  if (r != NASM_R_CONST)
+    return r;
+
+  /* 128 == 32 << 2.  Leave the shift to parse_opreand,
+     so it can check whether it is a multiple of 4.  */
+  *value = 128 + *value;
+  return r;
+}
+
+/* Parse the operand of movpi45.  */
+
+static int
+parse_pi5 (struct nds32_asm_desc *pdesc, struct nds32_asm_insn *pinsn,
+	   char **pstr, int64_t *value)
+{
+  int r;
+
+  r = pdesc->parse_operand (pdesc, pinsn, pstr, value);
+  if (r != NASM_R_CONST)
+    return r;
+
+  *value -= 16;
+  return r;
+}
+
+/* Generic operand parse base on the information provided by the field.  */
+
+static int
+parse_operand (nds32_asm_desc_t *pdesc, nds32_asm_insn_t *pinsn,
+	       char **str, int syn)
+{
+  char odstr[MAX_KEYWORD_LEN];
+  char *end;
+  hashval_t hash;
+  const field_t *fld = &LEX_GET_FIELD (syn);
+  keyword_t *k;
+  int64_t value = 0x100000000;	/* Big enough to overflow.  */
+  int r;
+  uint64_t modifier = 0;
+
+  end = *str;
+
+  if (fld->parse)
+    {
+      r = fld->parse (pdesc, pinsn, &end, &value);
+      goto done;
+    }
+
+  if (fld->hw_res < _HW_LAST)
+    {
+      /* Parse the operand in assembly code.  */
+      if (*end == '$')
+	end++;
+      end = parse_to_delimiter (end, odstr);
+
+      hash = htab_hash_string (odstr);
+      k = htab_find_with_hash (hw_ktabs[fld->hw_res], odstr, hash);
+
+      if (k == NULL)
+	{
+	  pdesc->result = NASM_ERR_OPERAND;
+	  return 0;
+	}
+
+      if (fld->hw_res == HW_GPR && (pdesc->flags & NASM_OPEN_REDUCED_REG)
+	  && (k->attr & ATTR (RDREG)) == 0)
+	{
+	  /* Register not allowed in reduced register.  */
+	  pdesc->result = NASM_ERR_REG_REDUCED;
+	  return 0;
+	}
+
+      if (fld->hw_res == HW_GPR)
+	{
+	  if (syn & SYN_INPUT)
+	    pinsn->defuse |= USE_REG (k->value);
+	  if (syn & SYN_OUTPUT)
+	    pinsn->defuse |= DEF_REG (k->value);
+	}
+
+      value = k->value;
+      if (fld->hw_res == HW_GPR && (fld->bitsize + fld->shift) == 4)
+	value = nds32_r54map[value];
+    }
+  else if (fld->hw_res == HW_INT || fld->hw_res == HW_UINT)
+    {
+      if (*end == '#')
+	end++;
+
+      /* Handle modifiers.  Do we need to make a table for modifiers?
+	 Do we need to check unknown modifier?  */
+      if (strncasecmp (end, "hi20(", 5) == 0)
+	{
+	  modifier |= NASM_ATTR_HI20;
+	  end += 5;
+	}
+      else if (strncasecmp (end, "lo12(", 5) == 0)
+	{
+	  modifier |= NASM_ATTR_LO12;
+	  end += 5;
+	}
+      else if (strncasecmp (end, "lo20(", 5) == 0)
+	{
+	  /* e.g., movi */
+	  modifier |= NASM_ATTR_LO20;
+	  end += 5;
+	}
+
+      r = pdesc->parse_operand (pdesc, pinsn, &end, &value);
+      if (modifier)
+	{
+	  /* Consume the ')' of modifier.  */
+	  end++;
+	  pinsn->attr |= modifier;
+	}
+
+      switch (r)
+	{
+	case NASM_R_ILLEGAL:
+	  pdesc->result = NASM_ERR_OPERAND;
+	  return 0;
+	case NASM_R_SYMBOL:
+	  /* This field needs special fix-up.  */
+	  pinsn->field = fld;
+	  break;
+	case NASM_R_CONST:
+	  if (modifier & NASM_ATTR_HI20)
+	    value = (value >> 12) & 0xfffff;
+	  else if (modifier & NASM_ATTR_LO12)
+	    value = value & 0xfff;
+	  else if (modifier & NASM_ATTR_LO20)
+	    value = value & 0xfffff;
+	  break;
+	default:
+	  fprintf (stderr, "Internal error: Don't know how to handle "
+			   "parsing results.\n");
+	  abort ();
+	}
+    }
+  else
+    {
+      fprintf (stderr, "Internal error: Unknown hardware resource.\n");
+      abort ();
+    }
+
+done:
+  /* Don't silently discarding bits.  */
+  if (value & __MASK (fld->shift))
+    {
+      pdesc->result = NASM_ERR_OUT_OF_RANGE;
+      return 0;
+    }
+
+  /* Check the range of signed or unsigned result.  */
+  if (fld->hw_res != HW_INT && (value >> (fld->bitsize + fld->shift)))
+    {
+      pdesc->result = NASM_ERR_OUT_OF_RANGE;
+      return 0;
+    }
+  else if (fld->hw_res == HW_INT)
+    {
+      /* Sign-ext the value.  */
+      if (((value >> 32) == 0) && (value & 0x80000000))
+	value |= (int64_t) -1 << 31;
+
+
+      /* Shift the value to positive domain.  */
+      if ((value + (1 << (fld->bitsize + fld->shift - 1)))
+	  >> (fld->bitsize + fld->shift))
+	{
+	  pdesc->result = NASM_ERR_OUT_OF_RANGE;
+	  return 0;
+	}
+    }
+
+  pinsn->insn |= (((value >> fld->shift) & __MASK (fld->bitsize)) << fld->bitpos);
+  *str = end;
+  return 1;
+}
+
+/* Try to parse an instruction string based on opcode syntax.  */
+
+static int
+parse_insn (nds32_asm_desc_t *pdesc, nds32_asm_insn_t *pinsn,
+	    char *str, struct nds32_opcode *opc)
+{
+  int variant = 0;
+  char *p = NULL;
+
+  /* A syntax may has optional operands, so we have to try each possible
+     combination to see if the input is accepted.  In order to do so,
+     bit-N represent whether optional-operand-N is used in this combination.
+     That is, if bit-N is set, optional-operand-N is not used.
+
+     For example, there are 2 optional operands in this syntax,
+
+	"a{,b}{,c}"
+
+     we can try it 4 times (i.e., 1 << 2)
+
+	0 (b00): "a,b,c"
+	1 (b01): "a,c"
+	2 (b10): "a,b"
+	3 (b11): "a"
+    */
+
+  /* The outer do-while loop is used to try each possible optional
+     operand combination, and VARIANT is the bit mask.  The inner loop
+     iterates each lexeme in the syntax.  */
+
+  do
+    {
+      /* OPT is the number of optional operands we've seen.  */
+      int opt = 0;
+      lex_t *plex;
+
+      /* PLEX is the syntax iterator and P is the iterator for input
+	 string.  */
+      plex = opc->syntax;
+      p = str;
+      /* Initial the base value.  */
+      pinsn->insn = opc->value;
+
+      while (*plex)
+	{
+	  if (IS_LEX_CHAR (*plex))
+	    {
+	      /* If it's a plain char, just compare it.  */
+	      if (LEX_CHAR (*plex) != *p)
+		{
+		  pdesc->result = NASM_ERR_SYNTAX;
+		  goto reject;
+		}
+	      p++;
+	    }
+	  else if (*plex & SYN_LOPT)
+	    {
+	      /* If it's '{' and it's not used in this iteration,
+		 just skip the whole optional operand.  */
+	      if ((1 << (opt++)) & variant)
+		{
+		  while ((*plex & SYN_ROPT) == 0)
+		    plex++;
+		}
+	    }
+	  else if (*plex & SYN_ROPT)
+	    {
+	      /* ignore */
+	    }
+	  else
+	    {
+	      /* If it's a operand, parse the input operand from input.  */
+	      if (!parse_operand (pdesc, pinsn, &p, *plex))
+		goto reject;
+	    }
+	  plex++;
+	}
+
+      /* Check whether this syntax is accepted.  */
+      if (*plex == 0 && (*p == '\0' || *p == '!' || *p == '#'))
+	return 1;
+
+reject:
+      /* If not accepted, try another combination.  */
+      variant++;
+    }
+  while (variant < (1 << opc->variant));
+
+  return 0;
+}
+
+void
+nds32_assemble (nds32_asm_desc_t *pdesc, nds32_asm_insn_t *pinsn,
+		char *str)
+{
+  struct nds32_opcode *opc;
+  char *s;
+  char *mnemoic;
+  char *dot;
+  hashval_t hash;
+
+  /* Duplicate the string, so we can modify it for convenience.  */
+  s = strdup (str);
+  mnemoic = s;
+  str = s;
+
+  /* Find opcode mnemoic.  */
+  while (*s != ' ' && *s != '\t' && *s != '\0')
+    s++;
+  if (*s != '\0')
+    *s++ = '\0';
+  dot = strchr (mnemoic, '.');
+
+retry_dot:
+  /* Lookup the opcode syntax.  */
+  hash = htab_hash_string (mnemoic);
+  opc = (struct nds32_opcode *)
+    htab_find_with_hash (opcode_htab, mnemoic, hash);
+
+  /* If we cannot find a match syntax, try it again without `.'.
+     For example, try "lmw.adm" first and then try "lmw" again.  */
+  if (opc == NULL && dot != NULL)
+    {
+      *dot = '\0';
+      s[-1] = ' ';
+      s = dot + 1;
+      dot = NULL;
+      goto retry_dot;
+    }
+  else if (opc == NULL)
+    {
+      pdesc->result = NASM_ERR_UNKNOWN_OP;
+      goto out;
+    }
+
+  /* There may be multiple syntaxes for a given opcode.
+     Try each one until a match is found.  */
+  for (; opc; opc = opc->next)
+    {
+      /* Build opcode syntax, if it's not been initialized yet.  */
+      if (opc->syntax == NULL)
+	build_opcode_syntax (opc);
+
+      /* Reset status before assemble.  */
+      pinsn->defuse = opc->defuse;
+      pinsn->insn = 0;
+      pinsn->field = NULL;
+      /* Use opcode attributes to initial instruction attributes.  */
+      pinsn->attr = opc->attr;
+      if (parse_insn (pdesc, pinsn, s, opc))
+	break;
+    }
+
+  pinsn->opcode = opc;
+  if (opc == NULL)
+    {
+      pdesc->result = NASM_ERR_SYNTAX;
+      goto out;
+    }
+
+  /* A matched opcode is found.  Write the result to instruction buffer.  */
+  pdesc->result = NASM_OK;
+
+out:
+  free (str);
+}
diff --git a/opcodes/nds32-asm.h b/opcodes/nds32-asm.h
new file mode 100644
index 0000000..ec91d07
--- /dev/null
+++ b/opcodes/nds32-asm.h
@@ -0,0 +1,191 @@
+/* NDS32-specific support for 32-bit ELF.
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.*/
+
+
+#ifndef NDS32_ASM_H
+#define NDS32_ASM_H
+
+/* Constant values for assembler.  */
+enum
+{
+  /* Error code for assembling an instruction.  */
+  NASM_OK = 0,
+  NASM_ERR_UNKNOWN_OP,
+  NASM_ERR_SYNTAX,
+  NASM_ERR_OPERAND,
+  NASM_ERR_OUT_OF_RANGE,
+  NASM_ERR_REG_REDUCED,
+  NASM_ERR_JUNK_EOL,
+
+  /* Results of parse_operand.  */
+  NASM_R_CONST,
+  NASM_R_SYMBOL,
+  NASM_R_ILLEGAL,
+
+  /* Flags for open description.  */
+  NASM_OPEN_ARCH_V1		= 0x0,
+  NASM_OPEN_ARCH_V2		= 0x1,
+  NASM_OPEN_ARCH_V3		= 0x2,
+  NASM_OPEN_ARCH_V3M		= 0x3,
+  NASM_OPEN_ARCH_MASK		= 0xf,
+  NASM_OPEN_REDUCED_REG		= 0x10,
+
+  /* Common attributes.  */
+  NASM_ATTR_ISA_V1		= 0x01,
+  NASM_ATTR_ISA_V2		= 0x02,
+  NASM_ATTR_ISA_V3		= 0x04,
+  NASM_ATTR_ISA_V3M		= 0x08,
+  NASM_ATTR_ISA_ALL		= 0x0f,
+
+  /* Attributes for instructions.  */
+  NASM_ATTR_MAC			= 0x0000100,
+  NASM_ATTR_DIV			= 0x0000200,
+  NASM_ATTR_FPU			= 0x0000400,
+  NASM_ATTR_FPU_SP_EXT		= 0x0000800,
+  NASM_ATTR_FPU_DP_EXT		= 0x0001000,
+  NASM_ATTR_STR_EXT		= 0x0002000,
+  NASM_ATTR_PERF_EXT		= 0x0004000,
+  NASM_ATTR_PERF2_EXT		= 0x0008000,
+  NASM_ATTR_AUDIO_ISAEXT	= 0x0010000,
+  NASM_ATTR_IFC_EXT		= 0x0020000,
+  NASM_ATTR_EX9_EXT		= 0x0040000,
+  NASM_ATTR_FPU_FMA		= 0x0080000,
+  NASM_ATTR_DXREG		= 0x0100000,
+  NASM_ATTR_BRANCH		= 0x0200000,
+  NASM_ATTR_RELAXABLE		= 0x0400000,
+  NASM_ATTR_PCREL		= 0x0800000,
+  NASM_ATTR_GPREL		= 0x1000000,
+
+  /* Attributes for relocations.  */
+  NASM_ATTR_HI20		= 0x10000000,
+  NASM_ATTR_LO12		= 0x20000000,
+  NASM_ATTR_LO20		= 0x40000000,
+
+  /* Attributes for registers.  */
+  NASM_ATTR_RDREG		= 0x000100
+};
+
+/* Macro for instruction attribute.  */
+#define ATTR(attr)		NASM_ATTR_ ## attr
+#define ATTR_NONE		0
+#define ATTR_PCREL		(ATTR (PCREL) | ATTR (BRANCH))
+
+#define ATTR_ALL		(ATTR (ISA_ALL))
+#define ATTR_V2UP		(ATTR_ALL & ~(ATTR (ISA_V1)))
+#define ATTR_V3MUP		(ATTR (ISA_V3) | ATTR (ISA_V3M))
+#define ATTR_V3			(ATTR (ISA_V3))
+#define ATTR_V3MEX_V1		(ATTR_ALL & ~(ATTR (ISA_V3M)))
+#define ATTR_V3MEX_V2		(ATTR_V2UP & ~(ATTR (ISA_V3M)))
+
+/* Lexical element in parsed syntax.  */
+typedef int lex_t;
+
+/* Common header for hash entries.  */
+struct nds32_hash_entry
+{
+  const char *name;
+};
+
+typedef struct nds32_keyword
+{
+  const char *name;
+  int value;
+  uint64_t attr;
+} keyword_t;
+
+typedef struct nds32_opcode
+{
+  /* Opcode for the instruction.  */
+  const char *opcode;
+  /* Human readable string of this instruction.  */
+  const char *instruction;
+  /* Base value of this instruction.  */
+  uint32_t value;
+  /* The byte-size of the instruction.  */
+  int isize;
+  /* Attributes of this instruction.  */
+  uint64_t attr;
+  /* Implicit define/use.  */
+  uint64_t defuse;
+  /* Parsed string for assembling.  */
+  lex_t *syntax;
+  /* Number of variant.  */
+  int variant;
+  /* Next form of the same mnemonic.  */
+  struct nds32_opcode *next;
+  /* TODO: Extra constrains and verification.
+	   For example, `mov55 $sp, $sp' is not allowed in v3.  */
+} opcode_t;
+
+typedef struct nds32_asm_insn
+{
+  /* Assembled instruction bytes.  */
+  uint32_t insn;
+  /* The opcode structure for this instruction.  */
+  struct nds32_opcode *opcode;
+  /* The field need special fix-up, used for relocation.  */
+  const struct nds32_field *field;
+  /* Attributes for relocation.  */
+  uint64_t attr;
+  /* Application-dependent data, e.g., expression.  */
+  void *info;
+  /* Input/output registers.  */
+  uint64_t defuse;
+} nds32_asm_insn_t;
+
+typedef struct nds32_asm_desc
+{
+  /* The callback provided by assembler user for parse an operand,
+     e.g., parse integer.  */
+  int (*parse_operand) (struct nds32_asm_desc *desc,
+			struct nds32_asm_insn *insn,
+			char **str, int64_t *value);
+
+  /* Result of assembling.  */
+  int result;
+
+  /* The mach for this assembling.  */
+  int mach;
+
+  int flags;
+} nds32_asm_desc_t;
+
+/* The field information for an operand.  */
+typedef struct nds32_field
+{
+  /* Name of the field.  */
+  const char *name;
+
+  int bitpos;
+  int bitsize;
+  int shift;
+  int hw_res;
+
+  int (*parse) (struct nds32_asm_desc *desc,
+		struct nds32_asm_insn *insn,
+		char **str, int64_t *value);
+} field_t;
+
+void nds32_assemble (nds32_asm_desc_t *pdesc, nds32_asm_insn_t *pinsn,
+		     char *str);
+void nds32_asm_init (nds32_asm_desc_t *pdesc, int flags);
+
+#endif
diff --git a/opcodes/nds32-dis.c b/opcodes/nds32-dis.c
new file mode 100644
index 0000000..a1db843
--- /dev/null
+++ b/opcodes/nds32-dis.c
@@ -0,0 +1,1171 @@
+/* NDS32-specific support for 32-bit ELF.
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.*/
+
+
+#include "sysdep.h"
+#include <stdio.h>
+#include "ansidecl.h"
+#include "dis-asm.h"
+#include "bfd.h"
+#include "symcat.h"
+#include "libiberty.h"
+#include "opintl.h"
+#include "bfd_stdint.h"
+
+#define __MF(v, off, bs)	((v & ((1 << (bs)) - 1)) << (off))
+#define __GF(v, off, bs)	((v >> (off)) & ((1 << (bs)) - 1))
+#define __PF(v, off, bs, val)	do { v = __put_field (v, off, bs, val); } while (0)
+/* #define __SEXT(v, bs)	((v ^ (1 << (bs - 1))) - (1 << (bs - 1))) */
+#define __SEXT(v, bs)		(((v & ((1 << bs) - 1)) ^ (1 << (bs - 1))) - (1 << (bs - 1)))
+#define __BIT(n)		(1 << n)
+
+/* Get fields */
+#define OP6(insn)	((insn >> 25) & 0x3F)
+#define RT5(insn)	((insn >> 20) & 0x1F)
+#define RA5(insn)	((insn >> 15) & 0x1F)
+#define RB5(insn)	((insn >> 10) & 0x1F)
+#define RD5(insn)	((insn >> 5) & 0x1F)
+#define SUB5(insn)	((insn >> 0) & 0x1F)
+#define SUB10(insn)	((insn >> 0) & 0x3FF)
+#define IMMU(insn, bs)	(insn & ((1 << bs) - 1))
+#define IMMS(insn, bs)	__SEXT((insn & ((1 << bs) - 1)), bs)
+#define IMM1U(insn)	IMMU((insn >> 10), 5)
+#define IMM1S(insn)	IMMS((insn >> 10), 5)
+#define IMM2U(insn)	IMMU((insn >> 5), 5)
+#define IMM2S(insn)	IMMS((insn >> 5), 5)
+
+/* Default text to print if an instruction isn't recognized.  */
+#define UNKNOWN_INSN_MSG _("*unknown*")
+
+static const char *mnemonic_op6[] =
+{
+  "lbi",  "lhi",   "lwi",  "ldi",    "lbi.bi",  "lhi.bi",  "lwi.bi",  "ldi.bi",
+  "sbi",  "shi",   "swi",  "sdi",    "sbi.bi",  "shi.bi",  "swi.bi",  "sdi.bi",
+  "lbsi", "lhsi",  "lwsi", "dprefi", "lbsi.bi", "lhsi.bi", "lwsi.bi", "lbgp",
+  "lwc",  "swc",   "ldc",  "sdc",    "mem",     "lsmw",    "hwgp",    "sbgp",
+  "alu1", "alu2",  "movi", "sethi",  "ji",      "jreg",    "br1",     "br2",
+  "addi", "subri", "andi", "xori",   "ori",     "br3",     "slti",    "sltsi",
+  "aext", "cext",  "misc", "bitci",  "op_64",   "cop"
+};
+
+static const char *mnemonic_mem[] =
+{
+  "lb",   "lh",  "lw",   "ld",    "lb.bi",  "lh.bi",  "lw.bi",  "ld.bi",
+  "sb",   "sh",  "sw",   "sd",    "sb.bi",  "sh.bi",  "sw.bi",  "sd.bi",
+  "lbs",  "lhs", "lws",  "dpref", "lbs.bi", "lhs.bi", "lws.bi", "27",
+  "llw",  "scw", "32",   "33",    "34",     "35",     "36",     "37",
+  "lbup", "41",  "lwup", "43",    "44",     "45",     "46",     "47",
+  "sbup", "51",  "swup"
+};
+
+static const char *mnemonic_alu1[] =
+{
+  "add",  "sub",  "and",   "xor",   "or",       "nor",      "slt",      "slts",
+  "slli", "srli", "srai",  "rotri", "sll",      "srl",      "sra",      "rotr",
+  "seb",  "seh",  "bitc",  "zeh",   "wsbh",     "or_srli",  "divsr",    "divr",
+  "sva",  "svs",  "cmovz", "cmovn", "add_srli", "sub_srli", "and_srli", "xor_srli"
+};
+
+
+static const char *mnemonic_alu20[] =
+{
+  "max",     "min",    "ave",     "abs",    "clips",   "clip",   "clo",    "clz",
+  "bset",    "bclr",   "btgl",    "btst",   "bse",     "bsp",    "ffb",    "ffmism",
+  "add.sc",  "sub.sc", "add.wc",  "sub.wc", "24",      "25",     "26",     "ffzmism",
+  "qadd",    "qsub",   "32",      "33",     "34",      "35",     "36",     "37",
+  "mfusr",   "mtusr",  "42",      "43",     "mul",     "45",     "46",     "47",
+  "mults64", "mult64", "madds64", "madd64", "msubs64", "msub64", "divs", "div",
+  "60",      "mult32", "62",      "madd32", "64",      "msub32", "65",   "66",
+  "dmadd",   "dmaddc", "dmsub",   "dmsubc", "rmfhi",   "qmflo"
+};
+
+static const char *mnemonic_alu21[] =
+{
+  "00",      "01",     "02", "03",      "04", "05",      "06",   "07",
+  "10",      "11",     "12", "13",      "14", "15",      "ffbi", "flmism",
+  "20",      "21",     "22", "23",      "24", "25",      "26",   "27",
+  "30",      "31",     "32", "33",      "34", "35",      "36",   "37",
+  "40",      "41",     "42", "43",      "44", "45",      "46",   "47",
+  "mulsr64", "mulr64", "52", "53",      "54", "55",      "56",   "57",
+  "60",      "61",     "62", "maddr32", "64", "msubr32", "66",   "67",
+  "70",      "71",     "72", "73",      "74", "75",      "76",   "77"
+};
+
+static const char *mnemonic_br2[] =
+{
+  "ifcall", "01", "beqz", "bnez", "bgez",   "bltz",   "bgtz", "blez",
+  "10",     "11", "12",   "13",   "bgezal", "bltzal"
+};
+
+static const char *mnemonic_misc[] =
+{
+  "standby", "cctl", "mfsr",  "mtsr",    "iret",  "trap",  "teqz", "tnez",
+  "dsb",     "isb",  "break", "syscall", "msync", "isync", "tlbop"
+};
+
+static const char *mnemonic_hwgp[] =
+{
+  "lhi.gp", "lhi.gp", "lhsi.gp", "lhsi.gp",
+  "shi.gp", "shi.gp", "lwi.gp", "swi.gp"
+};
+
+static const char *keyword_dpref[] =
+{
+  "SRD", "MRD", "SWR", "MWR", "PTE", "CLWR", "6",  "7",
+  "8",   "9",   "10",  "11",  "12",  "13",   "14", "15"
+};
+
+static const char *mnemonic_alu[] =
+{
+  "fadds",   "fsubs",   "fcpynss", "fcpyss",  "fmadds",
+  "fmsubs",  "fcmovns", "fcmovzs", "fnmadds", "fnmsubs",
+  "10",      "11",      "fmuls",   "fdivs",   "faddd",
+  "fsubd",   "fcpynsd", "fcpysd",  "fmaddd",  "fmsubd",
+  "fcmovnd", "fcmovzd", "fnmaddd", "fnmsubd", "24",
+  "25",      "fmuld",   "fdivd"
+};
+
+static const char *mnemonic_fpu_2op[] =
+{
+  "fs2d",  "fsqrts",  "2",     "3",  "4",       "fabss",  "6",      "7",
+  "fui2s", "9",       "10",    "11", "fsi2s",   "13",     "14",     "15",
+  "fs2ui", "17",      "18",    "19", "fs2ui.z", "21",     "22",     "23",
+  "fs2si", "25",      "26",    "27", "fs2si.z", "fd2s",   "fsqrtd", "31",
+  "32",    "33",      "fabsd", "35", "36",      "fui2d",  "38",     "39",
+  "40",    "fsi2d",   "42",    "43", "44",      "fd2ui",  "46",     "47",
+  "48",    "fd2ui.z", "50",    "51", "52",      "fd2si",  "54",     "55",
+  "56",    "fd2si.z"
+};
+
+static const char *mnemonic_fs2_cmp[] =
+{
+  "fcmpeqs", "fcmpeqs.e", "fcmplts", "fcmplts.e",
+  "fcmples", "fcmples.e", "fcmpuns", "fcmpuns.e"
+};
+
+static const char *mnemonic_fd2_cmp[] =
+{
+  "fcmpeqd", "fcmpeqd.e", "fcmpltd", "fcmpltd.e",
+  "fcmpled", "fcmpled.e", "fcmpund", "fcmpund.e"
+};
+
+static const char *gpr_map[] =
+{
+  "$r0", "$r1", "$r2", "$r3", "$r4", "$r5", "$r6", "$r7",
+  "$r8", "$r9", "$r10", "$r11", "$r12", "$r13", "$r14", "$r15",
+  "$r16", "$r17", "$r18", "$r19", "$r20", "$r21", "$r22", "$r23",
+  "$r24", "$r25", "$r26", "$r27", "$fp", "$gp", "$lp", "$sp"
+};
+
+static const char *usr_map[][32] =
+{
+  {
+    "d0,lo", "d0.hi", "d1,lo", "d1,hi", "4",  "5",  "6",  "7",
+    "8",     "9",     "10",    "11",    "12", "13", "14", "15",
+    "16",    "17",    "18",    "19",    "20", "21", "22", "23",
+    "24",    "25",    "26",    "27",    "28", "29", "30", "pc"
+  },
+  {
+    "DMA_CFG",     "DMA_GCSW",    "DMA_CHNSEL", "DMA_ACT",    "DMA_SETUP",
+    "DMA_ISADDR",  "DMA_ESADDR",  "DMA_TCNT",   "DMA_STATUS", "DMA_2DSET",
+    "10",          "11",          "12",         "13",         "14",
+    "15",          "16,",         "17",         "18",         "19",
+    "20",          "21",          "22",         "23",         "24,",
+    "DMA_2DSCTL"
+  },
+  {
+    "PFMC0", "PFMC1", "PFMC2", "3", "PFMCTL"
+  }
+};
+
+static void
+print_insn16 (bfd_vma pc, disassemble_info *info, uint32_t insn)
+{
+  static char r4map[] = {
+      0, 1, 2, 3, 4, 5, 6, 7,
+      8, 9, 10, 11, 16, 17, 18, 19
+  };
+  const int rt5 = __GF (insn, 5, 5);
+  const int ra5 = __GF (insn, 0, 5);
+  const int rt4 = r4map[__GF (insn, 5, 4)];
+  const int imm5u = IMMU (insn, 5);
+  const int imm9u = IMMU (insn, 9);
+  const int rt3 = __GF (insn, 6, 3);
+  const int ra3 = __GF (insn, 3, 3);
+  const int rb3 = __GF (insn, 0, 3);
+  const int rt38 = __GF (insn, 8, 3);
+  const int imm3u = rb3;
+  fprintf_ftype func = info->fprintf_func;
+  void *stream = info->stream;
+
+  static const char *mnemonic_96[] = {
+    "0x1",        "0x1",       "0x2",     "0x3",
+    "add45",      "sub45",     "addi45",  "subi45",
+    "srai45",     "srli45",    "slli333", "0xb",
+    "add333",     "sub333",    "addi333", "subi333",
+    "lwi333",     "lwi333.bi", "lhi333",  "lbi333",
+    "swi333",     "swi333.bi", "shi333",  "sbi333",
+    "addri36.sp", "lwi45.fe",  "lwi450",  "swi450",
+    "0x1c",       "0x1d",      "0x1e",    "0x1f",
+    "0x20",       "0x21",      "0x22",    "0x23",
+    "0x24",       "0x25",      "0x26",    "0x27,"
+    "0x28",       "0x29",      "0x2a",    "0x2b",
+    "0x2c",       "0x2d",      "0x2e",    "0x2f,"
+    "slts45",     "slt45",     "sltsi45", "slti45",
+    "0x34",       "0x35",      "0x36",    "0x37",
+    "0x38",       "0x39",      "0x3a",    "0x3b",
+    "ifcall9",    "movpi45"
+  };
+
+  static const char *mnemonic_misc33[] = {
+      "misc33_0", "misc33_1", "neg33", "not33", "mul33", "xor33", "and33", "or33",
+  };
+
+  static const char *mnemonic_0xb[] = {
+      "zeb33", "zeh33", "seb33", "seh33", "xlsb33", "x11b33", "bmski33", "fexti33"
+  };
+
+  static const char *mnemonic_bnes38[] = {
+      "jr5", "jral5", "ex9.it", "?", "ret5", "add5.pc"
+  };
+
+  switch (__GF (insn, 7, 8))
+    {
+    case 0xf8:			/* push25 */
+    case 0xf9:			/* pop25 */
+      {
+	uint32_t res[] = { 6, 8, 10, 14 };
+	uint32_t re = res[__GF (insn, 5, 2)];
+
+	func (stream, "%s\t%s, %d", (insn & __BIT (7)) ? "pop25" : "push25",
+	      gpr_map[re], imm5u << 3);
+      }
+      return;
+    }
+
+  if (__GF (insn, 8, 7) == 0x7d)	/* movd44 */
+    {
+      int rt5e = __GF (insn, 4, 4) << 1;
+      int ra5e = IMMU (insn, 4) << 1;
+
+      func (stream, "movd44\t%s, %d", gpr_map[rt5e], ra5e);
+      return;
+    }
+
+  switch (__GF (insn, 9, 6))
+    {
+    case 0x4:			/* add45 */
+    case 0x5:			/* sub45 */
+    case 0x30:			/* slts45 */
+    case 0x31:			/* slt45 */
+      func (stream, "%s\t%s, %s", mnemonic_96[__GF (insn, 9, 6)],
+	    gpr_map[rt4], gpr_map[ra5]);
+      return;
+    case 0x6:			/* addi45 */
+    case 0x7:			/* subi45 */
+    case 0x8:			/* srai45 */
+    case 0x9:			/* srli45 */
+    case 0x32:			/* sltsi45 */
+    case 0x33:			/* slti45 */
+      func (stream, "%s\t%s, %d", mnemonic_96[__GF (insn, 9, 6)],
+	    gpr_map[rt4], ra5);
+      return;
+    case 0xc:			/* add333 */
+    case 0xd:			/* sub333 */
+      func (stream, "%s\t%s, %s, %s", mnemonic_96[__GF (insn, 9, 6)],
+	    gpr_map[rt3], gpr_map[ra3], gpr_map[rb3]);
+      return;
+    case 0xa:			/* slli333 */
+    case 0xe:			/* addi333 */
+    case 0xf:			/* subi333 */
+      func (stream, "%s\t%s, %s, %d", mnemonic_96[__GF (insn, 9, 6)],
+	    gpr_map[rt3], gpr_map[ra3], imm3u);
+      return;
+    case 0x10:			/* lwi333 */
+    case 0x14:			/* swi333 */
+      func (stream, "%s\t%s, [%s + %d]", mnemonic_96[__GF (insn, 9, 6)],
+	    gpr_map[rt3], gpr_map[ra3], imm3u << 2);
+      return;
+    case 0x12:			/* lhi333 */
+    case 0x16:			/* shi333 */
+      func (stream, "%s\t%s, [%s + %d]", mnemonic_96[__GF (insn, 9, 6)],
+	    gpr_map[rt3], gpr_map[ra3], imm3u << 1);
+      return;
+    case 0x13:			/* lbi333 */
+    case 0x17:			/* sbi333 */
+      func (stream, "%s\t%s, [%s + %d]", mnemonic_96[__GF (insn, 9, 6)],
+	    gpr_map[rt3], gpr_map[ra3], imm3u);
+      return;
+    case 0x11:			/* lwi333.bi */
+    case 0x15:			/* swi333.bi */
+      func (stream, "%s\t%s, [%s], %d", mnemonic_96[__GF (insn, 9, 6)],
+	    gpr_map[rt3], gpr_map[ra3], imm3u << 2);
+      return;
+    case 0x18:			/* addri36.sp */
+      func (stream, "%s\t%s, %d", mnemonic_96[__GF (insn, 9, 6)],
+	    gpr_map[rt3], IMMU (insn, 6) << 2);
+      return;
+    case 0x19:			/* lwi45.fe */
+      func (stream, "%s\t%s, %d", mnemonic_96[__GF (insn, 9, 6)],
+	    gpr_map[rt4], -((32 - imm5u) << 2));
+      return;
+    case 0x1a:			/* lwi450 */
+    case 0x1b:			/* swi450 */
+      func (stream, "%s\t%s, [%s]", mnemonic_96[__GF (insn, 9, 6)],
+	    gpr_map[rt4], gpr_map[ra5]);
+      return;
+    case 0x34:			/* beqzs8, bnezs8 */
+      func (stream, "%s\t", ((insn & __BIT (8)) ? "bnezs8" : "beqzs8"));
+      info->print_address_func ((IMMS (insn, 8) << 1) + pc, info);
+      return;
+    case 0x35:			/* break16, ex9.it */
+      /* FIXME: Check bfd_mach.  */
+      if (imm9u < 32)		/* break16 */
+        func (stream, "break16\t%d", imm9u);
+      else
+        func (stream, "ex9.it\t%d", imm9u);
+      return;
+    case 0x3c:			/* ifcall9 */
+      func (stream, "%s\t", mnemonic_96[__GF (insn, 9, 6)]);
+      info->print_address_func ((IMMU (insn, 9) << 1) + pc, info);
+      return;
+    case 0x3d:			/* movpi45 */
+      func (stream, "%s\t%s, %d", mnemonic_96[__GF (insn, 9, 6)],
+	    gpr_map[rt4], ra5 + 16);
+      return;
+    case 0x3f:			/* MISC33 */
+      func (stream, "%s\t%s, %s", mnemonic_misc33[rb3],
+	    gpr_map[rt3], gpr_map[ra3]);
+      return;
+    case 0xb:			/* ... */
+      func (stream, "%s\t%s, %s", mnemonic_0xb[rb3],
+	   gpr_map[rt3], gpr_map[ra3]);
+      return;
+    }
+
+  switch (__GF (insn, 10, 5))
+    {
+    case 0x0:			/* mov55 or ifret16 */
+      /* FIXME: Check bfd_mach.  */
+      if (rt5 == ra5 && rt5 == 31)
+        func (stream, "ifret16");
+      else
+        func (stream, "mov55\t%s, %s", gpr_map[rt5], gpr_map[ra5]);
+      return;
+    case 0x1:			/* movi55 */
+      func (stream, "movi55\t%s, %d", gpr_map[rt5], IMMS (insn, 5));
+      return;
+    case 0x1b:			/* addi10s (V2) */
+      func (stream, "addi10s\t%d", IMMS (insn, 10));
+      return;
+    }
+
+  switch (__GF (insn, 11, 4))
+    {
+    case 0x7:			/* lwi37.fp/swi37.fp */
+      func (stream, "%s\t%s, [$fp + 0x%x]",
+	    ((insn & __BIT (7)) ? "swi37" : "lwi37"),
+	    gpr_map[rt38], IMMU (insn, 7) << 2);
+      return;
+    case 0x8:			/* beqz38 */
+    case 0x9:			/* bnez38 */
+      func (stream, "%s\t%s, ",
+	    ((__GF(insn, 11, 4) & 1) ? "bnez38" : "beqz38"), gpr_map[rt38]);
+      info->print_address_func ((IMMS (insn, 8) << 1) + pc, info);
+      return;
+    case 0xa:			/* beqs38/j8, implied r5 */
+      if (rt38 == 5)
+	{
+	  func (stream, "j8\t");
+	  info->print_address_func ((IMMS (insn, 8) << 1) + pc, info);
+	}
+     else
+	{
+	  func (stream, "beqs38\t%s, ", gpr_map[rt38]);
+	  info->print_address_func ((IMMS (insn, 8) << 1) + pc, info);
+	}
+      return;
+    case 0xb:			/* bnes38 and others */
+      if (rt38 == 5)
+	{
+	  switch (__GF (insn, 5, 3))
+	    {
+	    case 0:		/* jr5 */
+	    case 1:		/* jral5 */
+	    case 4:		/* ret5 */
+	      func (stream, "%s\t%s", mnemonic_bnes38[__GF (insn, 5, 3)], gpr_map[ra5]);
+	      return;
+	    case 2:		/* ex9.it imm5 */
+	    case 5:		/* add5.pc */
+	      func (stream, "%s\t%d", mnemonic_bnes38[__GF (insn, 5, 3)], ra5);
+	      return;
+	    default:
+	      func (stream, UNKNOWN_INSN_MSG);
+	      return;
+	    }
+	}
+      else
+	{
+	  func (stream, "bnes38\t%s", gpr_map[rt3]);
+	  info->print_address_func ((IMMS (insn, 8) << 1) + pc, info);
+	}
+      return;
+    case 0xe:			/* lwi37/swi37 */
+      func (stream, "%s\t%s, [+ 0x%x]",
+	    ((insn & __BIT (7)) ? "swi37.sp" : "lwi37.sp"),
+	    gpr_map[rt38], IMMU (insn, 7) << 2);
+      return;
+    }
+}
+
+
+static void
+print_insn32_mem (bfd_vma pc ATTRIBUTE_UNUSED, disassemble_info *info,
+		  uint32_t insn)
+{
+  const int rt = RT5 (insn);
+  const int ra = RA5 (insn);
+  const int rb = RB5 (insn);
+  const int sv = __GF (insn, 8, 2);
+  const int op = insn & 0xFF;
+  fprintf_ftype func = info->fprintf_func;
+  void *stream = info->stream;
+
+  switch (op)
+    {
+    case 0x0:			/* lb */
+    case 0x1:			/* lh */
+    case 0x2:			/* lw */
+    case 0x3:			/* ld */
+    case 0x8:			/* sb */
+    case 0x9:			/* sh */
+    case 0xa:			/* sw */
+    case 0xb:			/* sd */
+    case 0x10:			/* lbs */
+    case 0x11:			/* lhs */
+    case 0x12:			/* lws */
+    case 0x18:			/* llw */
+    case 0x19:			/* scw */
+    case 0x20:			/* lbup */
+    case 0x22:			/* lwup */
+    case 0x28:			/* sbup */
+    case 0x2a:			/* swup */
+      func (stream, "%s\t%s, [%s + (%s << %d)]",
+	    mnemonic_mem[op], gpr_map[rt], gpr_map[ra], gpr_map[rb], sv);
+      break;
+    case 0x4:			/* lb.bi */
+    case 0x5:			/* lh.bi */
+    case 0x6:			/* lw.bi */
+    case 0x7:			/* ld.bi */
+    case 0xc:			/* sb.bi */
+    case 0xd:			/* sh.bi */
+    case 0xe:			/* sw.bi */
+    case 0xf:			/* sd.bi */
+    case 0x14:			/* lbs.bi */
+    case 0x15:			/* lhs.bi */
+    case 0x16:			/* lws.bi */
+      func (stream, "%s\t%s, [%s], (%s << %d)",
+	    mnemonic_mem[op], gpr_map[rt], gpr_map[ra], gpr_map[rb], sv);
+      break;
+    case 0x13:			/* dpref */
+      {
+	const char *subtype = "???";
+
+	if ((rt & 0xf) < ARRAY_SIZE (keyword_dpref))
+	  subtype = keyword_dpref[rt & 0xf];
+
+	func (stream, "%s\t%s, [%s + (%s << %d)]",
+	      "dpref", subtype, gpr_map[ra], gpr_map[rb], sv);
+      }
+      break;
+    default:
+      func (stream, UNKNOWN_INSN_MSG);
+      return;
+    }
+}
+
+static void
+print_insn32_alu1 (bfd_vma pc ATTRIBUTE_UNUSED, disassemble_info *info, uint32_t insn)
+{
+  int op = insn & 0x1f;
+  const int rt = RT5 (insn);
+  const int ra = RA5 (insn);
+  const int rb = RB5 (insn);
+  const int rd = RD5 (insn);
+  fprintf_ftype func = info->fprintf_func;
+  void *stream = info->stream;
+
+  switch (op)
+    {
+    case 0x0:			/* add, add_slli */
+    case 0x1:			/* sub, sub_slli */
+    case 0x2:			/* and, add_slli */
+    case 0x3:			/* xor, xor_slli */
+    case 0x4:			/* or, or_slli */
+      if (rd != 0)
+	{
+	  func (stream, "%s_slli\t%s, %s, %s, #%d",
+	        mnemonic_alu1[op], gpr_map[rt], gpr_map[ra], gpr_map[rb], rd);
+	}
+      else
+	{
+	  func (stream, "%s\t%s, %s, %s",
+	        mnemonic_alu1[op], gpr_map[rt], gpr_map[ra], gpr_map[rb]);
+	}
+      return;
+    case 0x1c:			/* add_srli */
+    case 0x1d:			/* sub_srli */
+    case 0x1e:			/* and_srli */
+    case 0x1f:			/* xor_srli */
+    case 0x15:			/* or_srli */
+      func (stream, "%s\t%s, %s, %s, #%d",
+	    mnemonic_alu1[op], gpr_map[rt], gpr_map[ra], gpr_map[rb], rd);
+      return;
+    case 0x5:			/* nor */
+    case 0x6:			/* slt */
+    case 0x7:			/* slts */
+    case 0xc:			/* sll */
+    case 0xd:			/* srl */
+    case 0xe:			/* sra */
+    case 0xf:			/* rotr */
+    case 0x12:			/* bitc */
+    case 0x18:			/* sva */
+    case 0x19:			/* svs */
+    case 0x1a:			/* cmovz */
+    case 0x1b:			/* cmovn */
+      func (stream, "%s\t%s, %s, %s",
+	    mnemonic_alu1[op], gpr_map[rt], gpr_map[ra], gpr_map[rb]);
+      return;
+    case 0x9:			/* srli */
+      if (ra ==0 && rb == 0 && rb==0)
+	{
+	  func (stream, "nop");
+	  return;
+	}
+    case 0x8:			/* slli */
+    case 0xa:			/* srai */
+    case 0xb:			/* rotri */
+      func (stream, "%s\t%s, %s, #%d",
+	    mnemonic_alu1[op], gpr_map[rt], gpr_map[ra], rb);
+      return;
+    case 0x10:			/* seb */
+    case 0x11:			/* seh */
+    case 0x13:			/* zeh */
+    case 0x14:			/* wsbh */
+      func (stream, "%s\t%s, %s",
+	    mnemonic_alu1[op], gpr_map[rt], gpr_map[ra]);
+      return;
+    case 0x16:			/* divsr */
+    case 0x17:			/* divr */
+      func (stream, "%s\t%s, %s, %s, %s",
+	    mnemonic_alu1[op], gpr_map[rt], gpr_map[rd], gpr_map[ra], gpr_map[rb]);
+      return;
+    default:
+      func (stream, UNKNOWN_INSN_MSG);
+      return;
+    }
+
+  return;
+}
+
+static void
+print_insn32_alu2 (bfd_vma pc ATTRIBUTE_UNUSED, disassemble_info *info, uint32_t insn)
+{
+  int op = insn & 0x3ff;
+  const int rt = RT5 (insn);
+  const int ra = RA5 (insn);
+  const int rb = RB5 (insn);
+  fprintf_ftype func = info->fprintf_func;
+  void *stream = info->stream;
+
+  if ((insn & 0x7f) == 0x4e)	/* ffbi */
+    {
+      func (stream, "ffbi\t%s, %s, #0x%x",
+	    gpr_map[rt], gpr_map[ra], __GF (insn, 7, 8));
+      return;
+    }
+
+  switch (op)
+    {
+    case 0x0:			/* max */
+    case 0x1:			/* min */
+    case 0x2:			/* ave */
+    case 0xc:			/* bse */
+    case 0xd:			/* bsp */
+    case 0xe:			/* ffb */
+    case 0xf:			/* ffmism */
+    case 0x17:			/* ffzmism */
+    case 0x24:			/* mul */
+      func (stream, "%s\t%s, %s, %s", mnemonic_alu20[op], gpr_map[rt], gpr_map[ra], gpr_map[rb]);
+      return;
+
+    case 0x3:			/* abs */
+    case 0x6:			/* clo */
+    case 0x7:			/* clz */
+      func (stream, "%s\t%s, %s", mnemonic_alu20[op], gpr_map[rt], gpr_map[ra]);
+      return;
+
+    case 0x4:			/* clips */
+    case 0x5:			/* clip */
+    case 0x8:			/* bset */
+    case 0x9:			/* bclr */
+    case 0xa:			/* btgl */
+    case 0xb:			/* btst */
+      func (stream, "%s\t%s, %s, #%d", mnemonic_alu20[op],
+	    gpr_map[rt], gpr_map[ra], IMM1U (insn));
+      return;
+
+    case 0x20:			/* mfusr */
+    case 0x21:			/* mtusr */
+      func (stream, "%s\t%s, $%s", mnemonic_alu20[op],
+	    gpr_map[rt], usr_map[__GF (insn, 10, 5)][__GF (insn, 15, 5)]);
+      return;
+    case 0x28:			/* mults64 */
+    case 0x29:			/* mult64 */
+    case 0x2a:			/* madds64 */
+    case 0x2b:			/* madd64 */
+    case 0x2c:			/* msubs64 */
+    case 0x2d:			/* msub64 */
+    case 0x2e:			/* divs */
+    case 0x2f:			/* div */
+    case 0x31:			/* mult32 */
+    case 0x33:			/* madd32 */
+    case 0x35:			/* msub32 */
+      func (stream, "%s\t$d%d, %s, %s", mnemonic_alu20[op],
+	    rt >> 1, gpr_map[ra], gpr_map[rb]);
+      return;
+
+    case 0x4f:			/* flmism */
+    case 0x68:			/* mulsr64 */
+    case 0x69:			/* mulr64 */
+    case 0x73:			/* maddr32 */
+    case 0x75:			/* msubr32 */
+      op = insn & 0x3f;
+      func (stream, "%s\t%s, %s, %s", mnemonic_alu21[op], gpr_map[rt], gpr_map[ra], gpr_map[rb]);
+      return;
+    default:
+      func (stream, UNKNOWN_INSN_MSG);
+      return;
+    }
+}
+
+static void
+print_insn32_jreg (bfd_vma pc ATTRIBUTE_UNUSED, disassemble_info *info, uint32_t insn)
+{
+  int op = insn & 0xff;
+  const int rt = RT5 (insn);
+  const int rb = RB5 (insn);
+  const char *dtit_on[] = { "", ".iton", ".dton", ".ton" };
+  const char *dtit_off[] = { "", ".itoff", ".dtoff", ".toff" };
+  const char *mnemonic_jreg[] = { "jr", "jral", "jrnez", "jralnez" };
+  const char *mnemonic_ret[] = { "jr", "ret", NULL, "ifret" };
+  const int dtit = __GF (insn, 8, 2);
+  fprintf_ftype func = info->fprintf_func;
+  void *stream = info->stream;
+
+  switch (op)
+    {
+    case 0:		/* jr */
+      func (stream, "%s%s\t%s", mnemonic_ret[op >> 5], dtit_on[dtit], gpr_map[rb]);
+      return;
+
+    case 0x20:		/* ret */
+      func (stream, "%s%s\t%s", mnemonic_ret[op >> 5], dtit_off[dtit], gpr_map[rb]);
+      return;
+    case 0x60:		/* ifret */
+      break;
+    case 1:		/* jral */
+    case 2:		/* jrnez */
+    case 3:		/* jralnez */
+      func (stream, "%s%s\t%s, %s", mnemonic_jreg[op], dtit_on[dtit], gpr_map[rt], gpr_map[rb]);
+      return;
+    default:		/* unknown */
+      func (stream, UNKNOWN_INSN_MSG);
+      break;
+    }
+}
+
+static void
+print_insn32_misc (bfd_vma pc ATTRIBUTE_UNUSED, disassemble_info *info,
+		   uint32_t insn)
+{
+  int op = insn & 0x1f;
+  int rt = RT5 (insn);
+  unsigned int id;
+  fprintf_ftype func = info->fprintf_func;
+  void *stream = info->stream;
+
+  static const char *keyword_standby[] = {
+      "no_wake_grant", "wake_grant", "wait_done",
+  };
+  static const char *keyword_tlbop[] = {
+      "TRD", "TWR", "RWR", "RWLK", "UNLK", "PB", "INV", "FLUA"
+  };
+
+  switch (op)
+    {
+    case 0x0:			/* standby */
+      id = __GF (insn, 5, 20);
+      if (id < ARRAY_SIZE (keyword_standby))
+	func (stream, "standby\t%s", keyword_standby[id]);
+      else
+	func (stream, "standby\t%d", id);
+      return;
+    case 0x1:			/* cctl */
+      func (stream, "cctl\t!FIXME");
+      return;
+    case 0x8:			/* dsb */
+    case 0x9:			/* isb */
+    case 0xd:			/* isync */
+    case 0xc:			/* msync */
+    case 0x4:			/* iret */
+      func (stream, "%s", mnemonic_misc[op]);
+      return;
+    case 0x5:			/* trap */
+    case 0xa:			/* break */
+    case 0xb:			/* syscall */
+      id = __GF (insn, 5, 15);
+      func (stream, "%s\t%d", mnemonic_misc[op], id);
+      return;
+    case 0x2:			/* mfsr */
+    case 0x3:			/* mtsr */
+      /* FIXME: setend, setgie.  */
+      id = __GF (insn, 10, 10);
+      func (stream, "%s\t%s, %d", mnemonic_misc[op], gpr_map[rt], id);
+      return;
+    case 0x6:			/* teqz */
+    case 0x7:			/* tnez */
+      id = __GF (insn, 5, 15);
+      func (stream, "%s\t%s, %d", mnemonic_misc[op], gpr_map[rt], id);
+      return;
+    case 0xe:			/* tlbop */
+      id = __GF (insn, 5, 5);
+      if (id < ARRAY_SIZE (keyword_tlbop))
+	func (stream, "tlbop\t%s", keyword_tlbop[id]);
+      else
+	func (stream, "tlbop\t%d", id);
+      return;
+    }
+}
+
+static void
+print_insn32_fpu (bfd_vma pc ATTRIBUTE_UNUSED, disassemble_info *info,
+		  uint32_t insn)
+{
+  int op = insn & 0xf;
+  int mask_sub_op = (insn & 0x3c0) >> 6;
+  int mask_bi = (insn & 0x80) >> 7;
+  int mask_cfg = (insn & 0x7c00) >> 10;
+  int mask_f2op = (insn & 0x7c00) >> 10;
+  int dp = 0;
+  int dp_insn = 0;
+  char wd = 's';
+  const int rt = RT5 (insn);
+  const int ra = RA5 (insn);
+  const int rb = RB5 (insn);
+  const int sv = __GF (insn, 8, 2);
+  fprintf_ftype func = info->fprintf_func;
+  void *stream = info->stream;
+
+  switch (op)
+    {
+    case 0x0:			/* fs1 */
+    case 0x8:			/* fd1 */
+      dp = (op & 0x8) ? 1 : 0;
+      if (dp)
+	{
+	  wd = 'd';
+	  dp_insn = 14;
+	}
+      else
+	{
+	  wd = 's';
+	  dp_insn = 0;
+	}
+      switch (mask_sub_op)
+	{
+	case 0x0:
+	case 0x1:
+	case 0x2:
+	case 0x3:
+	case 0x4:
+	case 0x5:
+	case 0x8:
+	case 0x9:
+	case 0xc:
+	case 0xd:
+	  func (stream, "%s\t$f%c%d, $f%c%d, $f%c%d",
+		mnemonic_alu[mask_sub_op + dp_insn],
+		wd, rt, wd, ra, wd, rb);
+	  return;
+	case 0x6:
+	case 0x7:
+	  func (stream, "%s\t$f%c%d, $f%c%d, $fs%d",
+		mnemonic_alu[mask_sub_op + dp_insn],
+		wd, rt, wd, ra, rb);
+	  return;
+	case 0xf:
+	  if (dp)
+	    {
+	      wd = 'd';
+	      dp_insn = 0x1d;
+	    }
+	  else
+	    {
+	      wd = 's';
+	      dp_insn = 0;
+	    }
+
+	  switch (mask_f2op)
+	    {
+	    case 0x0:
+	      if (dp)
+		func (stream, "%s\t$fs%d, $fd%d",
+		      mnemonic_fpu_2op[mask_f2op + dp_insn], rt, ra);
+	      else
+		func (stream, "%s\t$fd%d, $fs%d",
+		      mnemonic_fpu_2op[mask_f2op + dp_insn], rt, ra);
+	      return;
+	    case 0x1:
+	    case 0x5:
+	      func (stream, "%s\t$f%c%d, $f%c%d",
+		    mnemonic_fpu_2op[mask_f2op + dp_insn], wd, rt, wd, ra);
+	      return;
+	    case 0x8:
+	    case 0xc:
+	      func (stream, "%s\t$f%c%d, $fs%d",
+		    mnemonic_fpu_2op[mask_f2op + dp_insn], wd, rt, ra);
+	      return;
+	    case 0x10:
+	    case 0x14:
+	    case 0x18:
+	    case 0x1c:
+	      func (stream, "%s\t$fs%d, $f%c%d",
+		    mnemonic_fpu_2op[mask_f2op + dp_insn], rt, wd, ra);
+	      return;
+	    }
+	}
+    case 0x1:			/* mfcp */
+      switch (mask_sub_op)
+	{
+	case 0x0:
+	  func (stream, "fmfsr\t%s, $fs%d", gpr_map[rt], ra);
+	  return;
+	case 0x1:
+	  func (stream, "fmfdr\t%s, $fd%d", gpr_map[rt], ra);
+	  return;
+	case 0xc:
+	  if (mask_cfg)
+	    func (stream, "fmfcsr\t%s", gpr_map[rt]);
+	  else
+	    func (stream, "fmfcfg\t%s", gpr_map[rt]);
+	  return;
+	}
+    case 0x2:			/* fls */
+      if (mask_bi)
+	func (stream, "fls.bi\t$fs%d, [%s], (%s << %d)", rt, gpr_map[ra], gpr_map[rb], sv);
+      else
+	func (stream, "fls\t$fs%d, [%s + (%s << %d)]", rt, gpr_map[ra], gpr_map[rb], sv);
+      return;
+    case 0x3:			/* fld */
+      if (mask_bi)
+	func (stream, "fld.bi\t$fd%d, [%s], (%s << %d)", rt, gpr_map[ra], gpr_map[rb], sv);
+      else
+	func (stream, "fld\t$fd%d, [%s + (%s << %d)]", rt, gpr_map[ra], gpr_map[rb], sv);
+      return;
+    case 0x4:			/* fs2 */
+      func (stream, "%s\t$fs%d, $fs%d, $fs%d",
+	    mnemonic_fs2_cmp[mask_sub_op], rt, ra, rb);
+      return;
+    case 0x9:			/* mtcp */
+      switch (mask_sub_op)
+	{
+	case 0x0:
+	  func (stream, "fmtsr\t%s, $fs%d", gpr_map[rt], ra);
+	  return;
+	case 0x1:
+	  func (stream, "fmtdr\t%s, $fd%d", gpr_map[rt], ra);
+	  return;
+	case 0xc:
+	    func (stream, "fmtcsr\t%s", gpr_map[rt]);
+	  return;
+	}
+    case 0xa:			/* fss */
+      if (mask_bi)
+	func (stream, "fss.bi\t$fs%d, [%s], (%s << %d)", rt, gpr_map[ra], gpr_map[rb], sv);
+      else
+	func (stream, "fss\t$fs%d, [%s + (%s << %d)]", rt, gpr_map[ra], gpr_map[rb], sv);
+      return;
+    case 0xb:			/* fsd */
+      if (mask_bi)
+	func (stream, "fsd.bi\t$fd%d, [%s], (%s << %d)", rt, gpr_map[ra], gpr_map[rb], sv);
+      else
+	func (stream, "fsd\t$fd%d, [%s + (%s << %d)]", rt, gpr_map[ra], gpr_map[rb], sv);
+      return;
+    case 0xc:			/* fd2 */
+      func (stream, "%s\t$fs%d, $fd%d, $fd%d",
+	    mnemonic_fd2_cmp[mask_sub_op], rt, ra, rb);
+      return;
+    }
+}
+
+static void
+print_insn32 (bfd_vma pc, disassemble_info *info, uint32_t insn)
+{
+  int op = OP6 (insn);
+  const int rt = RT5 (insn);
+  const int ra = RA5 (insn);
+  const int rb = RB5 (insn);
+  const int imm15s = IMMS (insn, 15);
+  const int imm15u = IMMU (insn, 15);
+  uint32_t shift;
+  fprintf_ftype func = info->fprintf_func;
+  void *stream = info->stream;
+
+  switch (op)
+    {
+    case 0x0:			/* lbi */
+    case 0x1:			/* lhi */
+    case 0x2:			/* lwi */
+    case 0x3:			/* ldi */
+    case 0x8:			/* sbi */
+    case 0x9:			/* shi */
+    case 0xa:			/* swi */
+    case 0xb:			/* sdi */
+    case 0x10:			/* lbsi */
+    case 0x11:			/* lhsi */
+    case 0x12:			/* lwsi */
+      shift = op & 0x3;
+      func (stream, "%s\t%s, [%s + #%d]",
+	    mnemonic_op6[op], gpr_map[rt], gpr_map[ra], imm15s << shift);
+      return;
+    case 0x4:			/* lbi.bi */
+    case 0x5:			/* lhi.bi */
+    case 0x6:			/* lwi.bi */
+    case 0x7:			/* ldi.bi */
+    case 0xc:			/* sbi.bi */
+    case 0xd:			/* shi.bi */
+    case 0xe:			/* swi.bi */
+    case 0xf:			/* sdi.bi */
+    case 0x14:			/* lbsi.bi */
+    case 0x15:			/* lhsi.bi */
+    case 0x16:			/* lwsi.bi */
+      shift = op & 0x3;
+      func (stream, "%s\t%s, [%s], #%d",
+	    mnemonic_op6[op], gpr_map[rt], gpr_map[ra], imm15s << shift);
+      return;
+    case 0x13:			/* dprefi */
+      {
+	const char *subtype = "???";
+	char wd = 'w';
+
+	shift = 2;
+
+	/* d-bit */
+	if (rt & 0x10)
+	  {
+	    wd = 'd';
+	    shift = 3;
+	  }
+
+	if ((rt & 0xf) < ARRAY_SIZE (keyword_dpref))
+	  subtype = keyword_dpref[rt & 0xf];
+
+	func (stream, "%s.%c\t%s, [%s + #%d]",
+	      mnemonic_op6[op], wd, subtype, gpr_map[ra], imm15s << shift);
+      }
+      return;
+    case 0x17:			/* LBGP */
+      func (stream, "%s\t%s, [+ %d]",
+	    ((insn & __BIT (19)) ? "lbsi.gp" : "lbi.gp"), gpr_map[rt], IMMS (insn, 19));
+      return;
+    case 0x18:			/* LWC */
+    case 0x19:			/* SWC */
+    case 0x1a:			/* LDC */
+    case 0x1b:			/* SDC */
+      if (__GF (insn, 13, 2) == 0)
+	{
+	  char ls = (op & 1) ? 's' : 'l';
+	  char wd = (op & 2) ? 'd' : 's';
+
+	  if (insn & __BIT (12))
+	    {
+	      func (stream, "f%c%ci.bi\t$f%c%d, [%s], %d", ls, wd,
+		    wd, rt, gpr_map[ra], IMMS (insn, 12) << 2);
+	    }
+	  else
+	    {
+	      func (stream, "f%c%ci\t$f%c%d, [%s + %d]", ls, wd,
+		    wd, rt, gpr_map[ra], IMMS (insn, 12) << 2);
+	    }
+	}
+      else
+	{
+	  char ls = (op & 1) ? 's' : 'l';
+	  char wd = (op & 2) ? 'd' : 'w';
+	  int cp = __GF (insn, 13, 2);
+
+	  if (insn & __BIT (12))
+	    {
+	      func (stream, "cp%c%ci\tcp%d, $cpr%d, [%s], %d", ls, wd,
+		    cp, rt, gpr_map[ra], IMMS (insn, 12) << 2);
+	    }
+	  else
+	    {
+	      func (stream, "cp%c%ci\tcp%d, $cpr%d, [%s + %d]", ls, wd,
+		    cp, rt, gpr_map[ra], IMMS (insn, 12) << 2);
+	    }
+	}
+      return;
+    case 0x1c:			/* MEM */
+      print_insn32_mem (pc, info, insn);
+      return;
+    case 0x1d:			/* LSMW */
+      {
+	int enb4 = __GF (insn, 6, 4);
+	char ls = (insn & __BIT (5)) ? 's' : 'l';
+	char ab = (insn & __BIT (4)) ? 'a' : 'b';
+	char *di = (insn & __BIT (3)) ? "d" : "i";
+	char *m = (insn & __BIT (2)) ? "m" : "";
+	static const char *s[] = {"", "a", "zb", "?"};
+
+	/* lsmwzb only always increase.  */
+	if ((insn & 0x3) == 2)
+	  di = "";
+
+	func (stream, "%cmw%s.%c%s%s\t%s, [%s], %s, 0x%x",
+	      ls, s[insn & 0x3], ab, di, m, gpr_map[rt], gpr_map[ra], gpr_map[rb], enb4);
+      }
+      return;
+    case 0x1e:			/* HWGP */
+      op = __GF (insn, 17, 3);
+      switch (op)
+	{
+	case 0: case 1:		/* lhi.gp */
+	case 2: case 3:		/* lhsi.gp */
+	case 4: case 5:		/* shi.gp */
+	  func (stream, "%s\t%s, [+ %d]",
+		mnemonic_hwgp[op], gpr_map[rt], IMMS (insn, 18) << 1);
+	  return;
+	case 6:			/* lwi.gp */
+	case 7:			/* swi.gp */
+	  func (stream, "%s\t%s, [+ %d]",
+		mnemonic_hwgp[op], gpr_map[rt], IMMS (insn, 17) << 2);
+	  return;
+	}
+      return;
+    case 0x1f:			/* SBGP */
+      if (insn & __BIT (19))
+	func (stream, "addi.gp\t%s, %d",
+	      gpr_map[rt], IMMS (insn, 19));
+      else
+	func (stream, "sbi.gp\t%s, [+ %d]",
+	      gpr_map[rt], IMMS (insn, 19));
+      return;
+    case 0x20:			/* ALU_1 */
+      print_insn32_alu1 (pc, info, insn);
+      return;
+    case 0x21:			/* ALU_2 */
+      print_insn32_alu2 (pc, info, insn);
+      return;
+    case 0x22:			/* movi */
+      func (stream, "movi\t%s, %d", gpr_map[rt], IMMS (insn, 20));
+      return;
+    case 0x23:			/* sethi */
+      func (stream, "sethi\t%s, 0x%x", gpr_map[rt], IMMU (insn, 20));
+      return;
+    case 0x24:			/* ji, jal */
+      /* FIXME: Handle relocation.  */
+      if (info->flags & INSN_HAS_RELOC)
+	pc = 0;
+      func (stream, "%s\t", ((insn & __BIT (24)) ? "jal" : "j"));
+      info->print_address_func ((IMMS (insn, 24) << 1) + pc, info);
+      return;
+    case 0x25:			/* jreg */
+      print_insn32_jreg (pc, info, insn);
+      return;
+    case 0x26:			/* br1 */
+      func (stream, "%s\t%s, %s, ", ((insn & __BIT (14)) ? "bne" : "beq"),
+	    gpr_map[rt], gpr_map[ra]);
+      info->print_address_func ((IMMS (insn, 14) << 1) + pc, info);
+      return;
+    case 0x27:			/* br2 */
+      func (stream, "%s\t%s, ", mnemonic_br2[__GF (insn, 16, 4)],
+	    gpr_map[rt]);
+      info->print_address_func ((IMMS (insn, 16) << 1) + pc, info);
+      return;
+    case 0x28:			/* addi */
+    case 0x2e:			/* slti */
+    case 0x2f:			/* sltsi */
+    case 0x29:			/* subri */
+      func (stream, "%s\t%s, %s, %d",
+	    mnemonic_op6[op], gpr_map[rt], gpr_map[ra], imm15s);
+      return;
+    case 0x2a:			/* andi */
+    case 0x2b:			/* xori */
+    case 0x2c:			/* ori */
+    case 0x33:			/* bitci */
+      func (stream, "%s\t%s, %s, %d",
+	    mnemonic_op6[op], gpr_map[rt], gpr_map[ra], imm15u);
+      return;
+    case 0x2d:			/* br3, beqc, bnec */
+      func (stream, "%s\t%s, %d, ", ((insn & __BIT (19)) ? "bnec" : "beqc"),
+	    gpr_map[rt], __SEXT (__GF (insn, 8, 11), 11));
+      info->print_address_func ((IMMS (insn, 8) << 1) + pc, info);
+      return;
+    case 0x32:			/* misc */
+      print_insn32_misc (pc, info, insn);
+      return;
+    case 0x35:			/* FPU */
+      print_insn32_fpu (pc, info, insn);
+      return;
+    }
+}
+
+int
+print_insn_nds32 (bfd_vma pc, disassemble_info *info)
+{
+  int status;
+  bfd_byte buf[4];
+  uint32_t insn;
+
+  status = info->read_memory_func (pc, (bfd_byte *) buf, 2, info);
+  if (status)
+    return -1;
+
+  /* 16-bit instruction.  */
+  if (buf[0] & 0x80)
+    {
+      insn = bfd_getb16 (buf);
+      print_insn16 (pc, info, insn);
+      return 2;
+    }
+
+  /* 32-bit instructions.  */
+  status = info->read_memory_func (pc + 2, (bfd_byte *) buf + 2, 2, info);
+  if (status)
+    return -1;
+
+  insn = bfd_getb32 (buf);
+  print_insn32 (pc, info, insn);
+
+  return 4;
+}
diff --git a/opcodes/nds32-opc.h b/opcodes/nds32-opc.h
new file mode 100644
index 0000000..4ab0d48
--- /dev/null
+++ b/opcodes/nds32-opc.h
@@ -0,0 +1,209 @@
+/* NDS32-specific support for 32-bit ELF.
+   Copyright (C) 2012-2013 Free Software Foundation, Inc.
+   Contributed by Andes Technology Corporation.
+
+   This file is part of BFD, the Binary File Descriptor library.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.*/
+
+
+#ifndef NDS32_OPC_H
+#define NDS32_OPC_H
+
+/* This was the enum used for 32/16 conversion.  */
+
+enum
+{
+  NDS32_INSN_INVALID, NDS32_INSN_MOVI, NDS32_INSN_SETHI, NDS32_INSN_ADDI,
+  NDS32_INSN_ADD, NDS32_INSN_SLTSI, NDS32_INSN_SLTS, NDS32_INSN_SLTI,
+  NDS32_INSN_SLT, NDS32_INSN_SUBRI, NDS32_INSN_SUB, NDS32_INSN_ANDI,
+  NDS32_INSN_AND, NDS32_INSN_XORI, NDS32_INSN_XOR, NDS32_INSN_ORI,
+  NDS32_INSN_OR, NDS32_INSN_NOR, NDS32_INSN_SVA, NDS32_INSN_SVS,
+  NDS32_INSN_SEB, NDS32_INSN_SEH, NDS32_INSN_ZEH, NDS32_INSN_WSBH,
+  NDS32_INSN_SLLI, NDS32_INSN_SLL, NDS32_INSN_SRAI, NDS32_INSN_SRA,
+  NDS32_INSN_ROTRI, NDS32_INSN_ROTR, NDS32_INSN_SRLI, NDS32_INSN_SRL,
+  NDS32_INSN_MUL, NDS32_INSN_MULTS64, NDS32_INSN_MULT64, NDS32_INSN_MADDS64,
+  NDS32_INSN_MADD64, NDS32_INSN_MSUBS64, NDS32_INSN_MSUB64,
+  NDS32_INSN_MULT32, NDS32_INSN_MADD32, NDS32_INSN_MSUB32, NDS32_INSN_MFUSR,
+  NDS32_INSN_MTUSR, NDS32_INSN_LBI, NDS32_INSN_LBI_BI, NDS32_INSN_LB,
+  NDS32_INSN_LB_BI, NDS32_INSN_LHI, NDS32_INSN_LHI_BI, NDS32_INSN_LH,
+  NDS32_INSN_LH_BI, NDS32_INSN_LWI, NDS32_INSN_LWI_BI, NDS32_INSN_LW,
+  NDS32_INSN_LW_BI, NDS32_INSN_LWUP, NDS32_INSN_SWUP, NDS32_INSN_LBSI,
+  NDS32_INSN_LBSI_BI, NDS32_INSN_LBS, NDS32_INSN_LBS_BI, NDS32_INSN_LHSI,
+  NDS32_INSN_LHSI_BI, NDS32_INSN_LHS, NDS32_INSN_LHS_BI, NDS32_INSN_SBI,
+  NDS32_INSN_SBI_BI, NDS32_INSN_SB, NDS32_INSN_SB_BI, NDS32_INSN_SHI,
+  NDS32_INSN_SHI_BI, NDS32_INSN_SH, NDS32_INSN_SH_BI, NDS32_INSN_SWI,
+  NDS32_INSN_SWI_BI, NDS32_INSN_SW, NDS32_INSN_SW_BI, NDS32_INSN_LMW_BI,
+  NDS32_INSN_LMW_BIM, NDS32_INSN_LMW_BD, NDS32_INSN_LMW_BDM,
+  NDS32_INSN_LMW_AI, NDS32_INSN_LMW_AIM, NDS32_INSN_LMW_AD,
+  NDS32_INSN_LMW_ADM, NDS32_INSN_SMW_BI, NDS32_INSN_SMW_BIM,
+  NDS32_INSN_SMW_BD, NDS32_INSN_SMW_BDM, NDS32_INSN_SMW_AI,
+  NDS32_INSN_SMW_AIM, NDS32_INSN_SMW_AD, NDS32_INSN_SMW_ADM, NDS32_INSN_LLW,
+  NDS32_INSN_SCW, NDS32_INSN_J, NDS32_INSN_JAL, NDS32_INSN_JR,
+  NDS32_INSN_RET, NDS32_INSN_JR_ITOFF, NDS32_INSN_JR_TOFF,
+  NDS32_INSN_RET_ITOFF, NDS32_INSN_RET_TOFF, NDS32_INSN_JRAL,
+  NDS32_INSN_JRAL_ITON, NDS32_INSN_JRAL_TON, NDS32_INSN_BEQ, NDS32_INSN_BNE,
+  NDS32_INSN_BEQZ, NDS32_INSN_BNEZ, NDS32_INSN_BGEZ, NDS32_INSN_BLTZ,
+  NDS32_INSN_BGTZ, NDS32_INSN_BLEZ, NDS32_INSN_BGEZAL, NDS32_INSN_BLTZAL,
+  NDS32_INSN_MFSR, NDS32_INSN_MTSR, NDS32_INSN_SETEND_L,
+  NDS32_INSN_SETEND_B, NDS32_INSN_SETGIE_D, NDS32_INSN_SETGIE_E,
+  NDS32_INSN_CMOVZ, NDS32_INSN_CMOVN, NDS32_INSN_DPREFI_D,
+  NDS32_INSN_DPREFI_W, NDS32_INSN_DPREF, NDS32_INSN_ISYNC, NDS32_INSN_MSYNC,
+  NDS32_INSN_ISB, NDS32_INSN_DSB, NDS32_INSN_STANDBY, NDS32_INSN_TRAP,
+  NDS32_INSN_TEQZ, NDS32_INSN_TNEZ, NDS32_INSN_BREAK, NDS32_INSN_SYSCALL,
+  NDS32_INSN_IRET, NDS32_INSN_TLBOP, NDS32_INSN_CCTL, NDS32_INSN_DIVS,
+  NDS32_INSN_DIV, NDS32_INSN_ABS, NDS32_INSN_AVE, NDS32_INSN_MIN,
+  NDS32_INSN_MAX, NDS32_INSN_BSET, NDS32_INSN_BTGL, NDS32_INSN_BCLR,
+  NDS32_INSN_BTST, NDS32_INSN_CLIPS, NDS32_INSN_CLIP, NDS32_INSN_CLZ,
+  NDS32_INSN_CLO, NDS32_INSN_BSE, NDS32_INSN_BSP, NDS32_INSN_PBSAD,
+  NDS32_INSN_PBSADA, NDS32_INSN_MOV55, NDS32_INSN_MOVI55, NDS32_INSN_ADDI45,
+  NDS32_INSN_ADD45, NDS32_INSN_SUBI45, NDS32_INSN_SUB45, NDS32_INSN_SRAI45,
+  NDS32_INSN_SRLI45, NDS32_INSN_SLLI333, NDS32_INSN_SEB33, NDS32_INSN_SEH33,
+  NDS32_INSN_ZEB33, NDS32_INSN_ZEH33, NDS32_INSN_XLSB33, NDS32_INSN_X11B33,
+  NDS32_INSN_ADDI333, NDS32_INSN_ADD333, NDS32_INSN_SUBI333,
+  NDS32_INSN_SUB333, NDS32_INSN_LWI333, NDS32_INSN_LWI333_BI,
+  NDS32_INSN_LHI333, NDS32_INSN_LBI333, NDS32_INSN_SWI333,
+  NDS32_INSN_SWI333_BI, NDS32_INSN_SHI333, NDS32_INSN_SBI333,
+  NDS32_INSN_LWI450, NDS32_INSN_SWI450, NDS32_INSN_LWI37, NDS32_INSN_SWI37,
+  NDS32_INSN_BEQZ38, NDS32_INSN_BNEZ38, NDS32_INSN_BEQS38,
+  NDS32_INSN_BNES38, NDS32_INSN_J8, NDS32_INSN_JR5, NDS32_INSN_RET5,
+  NDS32_INSN_JRAL5, NDS32_INSN_SLTI45, NDS32_INSN_SLTSI45, NDS32_INSN_SLT45,
+  NDS32_INSN_SLTS45, NDS32_INSN_BEQZS8, NDS32_INSN_BNEZS8,
+  NDS32_INSN_BREAK16, NDS32_INSN_ADDI10_SP, NDS32_INSN_LWI37_SP,
+  NDS32_INSN_SWI37_SP, NDS32_INSN_BMSKI33, NDS32_INSN_FEXTI33,
+  NDS32_INSN_ADDRI36_SP, NDS32_INSN_LWI45_FE, NDS32_INSN_NEG33,
+  NDS32_INSN_NOT33, NDS32_INSN_MUL33, NDS32_INSN_XOR33, NDS32_INSN_AND33,
+  NDS32_INSN_OR33, NDS32_INSN_MOVPI45, NDS32_INSN_PUSH25, NDS32_INSN_POP25,
+  NDS32_INSN_MOVD44, NDS32_INSN_ADD5_PC, NDS32_INSN_BREAK16V3,
+  NDS32_INSN_ADDI_GP, NDS32_INSN_MADDR32, NDS32_INSN_MSUBR32,
+  NDS32_INSN_MULR64, NDS32_INSN_MULSR64, NDS32_INSN_SBI_GP,
+  NDS32_INSN_SHI_GP, NDS32_INSN_SWI_GP, NDS32_INSN_LBI_GP,
+  NDS32_INSN_LBSI_GP, NDS32_INSN_LHI_GP, NDS32_INSN_LHSI_GP,
+  NDS32_INSN_LWI_GP, NDS32_INSN_DIVR, NDS32_INSN_DIVSR, NDS32_INSN_LMWA_BI,
+  NDS32_INSN_LMWA_BIM, NDS32_INSN_LMWA_BD, NDS32_INSN_LMWA_BDM,
+  NDS32_INSN_LMWA_AI, NDS32_INSN_LMWA_AIM, NDS32_INSN_LMWA_AD,
+  NDS32_INSN_LMWA_ADM, NDS32_INSN_SMWA_BI, NDS32_INSN_SMWA_BIM,
+  NDS32_INSN_SMWA_BD, NDS32_INSN_SMWA_BDM, NDS32_INSN_SMWA_AI,
+  NDS32_INSN_SMWA_AIM, NDS32_INSN_SMWA_AD, NDS32_INSN_SMWA_ADM,
+  NDS32_INSN_LBUP, NDS32_INSN_SBUP, NDS32_INSN_LMWZB_B, NDS32_INSN_LMWZB_BM,
+  NDS32_INSN_LMWZB_A, NDS32_INSN_LMWZB_AM, NDS32_INSN_SMWZB_B,
+  NDS32_INSN_SMWZB_BM, NDS32_INSN_SMWZB_A, NDS32_INSN_SMWZB_AM,
+  NDS32_INSN_BEQC, NDS32_INSN_BNEC, NDS32_INSN_JRALNEZ, NDS32_INSN_JRNEZ,
+  NDS32_INSN_ADD_SLLI, NDS32_INSN_ADD_SRLI, NDS32_INSN_SUB_SLLI,
+  NDS32_INSN_SUB_SRLI, NDS32_INSN_AND_SLLI, NDS32_INSN_AND_SRLI,
+  NDS32_INSN_OR_SLLI, NDS32_INSN_OR_SRLI, NDS32_INSN_XOR_SLLI,
+  NDS32_INSN_XOR_SRLI, NDS32_INSN_BITC, NDS32_INSN_BITCI, NDS32_INSN_AADDL,
+  NDS32_INSN_ASUBL, NDS32_INSN_ALA, NDS32_INSN_ALR, NDS32_INSN_ALR2,
+  NDS32_INSN_ASA, NDS32_INSN_ASR, NDS32_INSN_AUPI, NDS32_INSN_AMFAR,
+  NDS32_INSN_AMTAR, NDS32_INSN_AMTARI, NDS32_INSN_ASATS48, NDS32_INSN_AWEXT,
+  NDS32_INSN_AMADD, NDS32_INSN_AMADDL_S, NDS32_INSN_AMADDL2_S,
+  NDS32_INSN_AMADDL_L, NDS32_INSN_AMADDL2_L, NDS32_INSN_AMADDSA,
+  NDS32_INSN_AMSUB, NDS32_INSN_AMSUBL_S, NDS32_INSN_AMSUBL2_S,
+  NDS32_INSN_AMSUBL_L, NDS32_INSN_AMSUBL2_L, NDS32_INSN_AMSUBSA,
+  NDS32_INSN_AMADDS, NDS32_INSN_AMADDSL_S, NDS32_INSN_AMADDSL2_S,
+  NDS32_INSN_AMADDSL_L, NDS32_INSN_AMADDSL2_L, NDS32_INSN_AMADDSSA,
+  NDS32_INSN_AMSUBS, NDS32_INSN_AMSUBSL_S, NDS32_INSN_AMSUBSL2_S,
+  NDS32_INSN_AMSUBSL_L, NDS32_INSN_AMSUBSL2_L, NDS32_INSN_AMSUBSSA,
+  NDS32_INSN_AMNEGS, NDS32_INSN_AMNEGSL_S, NDS32_INSN_AMNEGSL2_S,
+  NDS32_INSN_AMNEGSL_L, NDS32_INSN_AMNEGSL2_L, NDS32_INSN_AMNEGSSA,
+  NDS32_INSN_AMULTS, NDS32_INSN_AMULTSL_S, NDS32_INSN_AMULTSL2_S,
+  NDS32_INSN_AMULTSL_L, NDS32_INSN_AMULTSL2_L, NDS32_INSN_AMULTSSA,
+  NDS32_INSN_AMULT, NDS32_INSN_AMULTL_S, NDS32_INSN_AMULTL2_S,
+  NDS32_INSN_AMULTL_L, NDS32_INSN_AMULTL2_L, NDS32_INSN_AMULTSA,
+  NDS32_INSN_AZOL, NDS32_INSN_AMABBS, NDS32_INSN_AMABTS, NDS32_INSN_AMATBS,
+  NDS32_INSN_AMATTS, NDS32_INSN_AMBBS, NDS32_INSN_AMBTS, NDS32_INSN_AMTBS,
+  NDS32_INSN_AMTTS, NDS32_INSN_AMABBSL_S, NDS32_INSN_AMABBSL_L,
+  NDS32_INSN_AMABBSL2_S, NDS32_INSN_AMABBSL2_L, NDS32_INSN_AMABBSSA,
+  NDS32_INSN_AMABTSL_S, NDS32_INSN_AMABTSL_L, NDS32_INSN_AMABTSL2_S,
+  NDS32_INSN_AMABTSL2_L, NDS32_INSN_AMABTSSA, NDS32_INSN_AMATBSL_S,
+  NDS32_INSN_AMATBSL_L, NDS32_INSN_AMATBSL2_S, NDS32_INSN_AMATBSL2_L,
+  NDS32_INSN_AMATBSSA, NDS32_INSN_AMATTSL_S, NDS32_INSN_AMATTSL_L,
+  NDS32_INSN_AMATTSL2_S, NDS32_INSN_AMATTSL2_L, NDS32_INSN_AMATTSSA,
+  NDS32_INSN_AMBBSL_S, NDS32_INSN_AMBBSL_L, NDS32_INSN_AMBBSL2_S,
+  NDS32_INSN_AMBBSL2_L, NDS32_INSN_AMBBSSA, NDS32_INSN_AMBTSL_S,
+  NDS32_INSN_AMBTSL_L, NDS32_INSN_AMBTSL2_S, NDS32_INSN_AMBTSL2_L,
+  NDS32_INSN_AMBTSSA, NDS32_INSN_AMTBSL_S, NDS32_INSN_AMTBSL_L,
+  NDS32_INSN_AMTBSL2_S, NDS32_INSN_AMTBSL2_L, NDS32_INSN_AMTBSSA,
+  NDS32_INSN_AMTTSL_S, NDS32_INSN_AMTTSL_L, NDS32_INSN_AMTTSL2_S,
+  NDS32_INSN_AMTTSL2_L, NDS32_INSN_AMTTSSA, NDS32_INSN_AMAWBS,
+  NDS32_INSN_AMAWTS, NDS32_INSN_AMWBS, NDS32_INSN_AMWTS,
+  NDS32_INSN_AMAWBSL_S, NDS32_INSN_AMAWBSL_L, NDS32_INSN_AMAWBSL2_S,
+  NDS32_INSN_AMAWBSL2_L, NDS32_INSN_AMAWBSSA, NDS32_INSN_AMAWTSL_S,
+  NDS32_INSN_AMAWTSL_L, NDS32_INSN_AMAWTSL2_S, NDS32_INSN_AMAWTSL2_L,
+  NDS32_INSN_AMAWTSSA, NDS32_INSN_AMWBSL_S, NDS32_INSN_AMWBSL_L,
+  NDS32_INSN_AMWBSL2_S, NDS32_INSN_AMWBSL2_L, NDS32_INSN_AMWBSSA,
+  NDS32_INSN_AMWTSL_S, NDS32_INSN_AMWTSL_L, NDS32_INSN_AMWTSL2_S,
+  NDS32_INSN_AMWTSL2_L, NDS32_INSN_AMWTSSA, NDS32_INSN_AMFAR2,
+  NDS32_INSN_AMTAR2, NDS32_INSN_FLS, NDS32_INSN_FLS_BI, NDS32_INSN_FLSI,
+  NDS32_INSN_FLSI_BI, NDS32_INSN_FMFCFG, NDS32_INSN_FMFCSR,
+  NDS32_INSN_FMTCSR, NDS32_INSN_FMFSR, NDS32_INSN_FMTSR, NDS32_INSN_FSS,
+  NDS32_INSN_FSS_BI, NDS32_INSN_FSSI, NDS32_INSN_FSSI_BI, NDS32_INSN_FS2D,
+  NDS32_INSN_FABSS, NDS32_INSN_FADDS, NDS32_INSN_FCMOVNS,
+  NDS32_INSN_FCMOVZS, NDS32_INSN_FCMPEQS, NDS32_INSN_FCMPEQS_E,
+  NDS32_INSN_FCMPLTS, NDS32_INSN_FCMPLTS_E, NDS32_INSN_FCMPLES,
+  NDS32_INSN_FCMPLES_E, NDS32_INSN_FCMPUNS, NDS32_INSN_FCMPUNS_E,
+  NDS32_INSN_FCPYNSS, NDS32_INSN_FCPYSS, NDS32_INSN_FDIVS,
+  NDS32_INSN_FMADDS, NDS32_INSN_FMULS, NDS32_INSN_FMSUBS,
+  NDS32_INSN_FNMADDS, NDS32_INSN_FNMSUBS, NDS32_INSN_FS2SI,
+  NDS32_INSN_FS2SI_Z, NDS32_INSN_FS2UI, NDS32_INSN_FS2UI_Z,
+  NDS32_INSN_FSI2S, NDS32_INSN_FSQRTS, NDS32_INSN_FSUBS, NDS32_INSN_FUI2S,
+  NDS32_INSN_FABSD, NDS32_INSN_FADDD, NDS32_INSN_FCMOVND,
+  NDS32_INSN_FCMOVZD, NDS32_INSN_FCMPEQD, NDS32_INSN_FCMPEQD_E,
+  NDS32_INSN_FCMPLTD, NDS32_INSN_FCMPLTD_E, NDS32_INSN_FCMPLED,
+  NDS32_INSN_FCMPLED_E, NDS32_INSN_FCMPUND, NDS32_INSN_FCMPUND_E,
+  NDS32_INSN_FCPYNSD, NDS32_INSN_FCPYSD, NDS32_INSN_FD2S, NDS32_INSN_FD2SI,
+  NDS32_INSN_FD2SI_Z, NDS32_INSN_FD2UI, NDS32_INSN_FD2UI_Z,
+  NDS32_INSN_FDIVD, NDS32_INSN_FLD, NDS32_INSN_FLD_BI, NDS32_INSN_FLDI,
+  NDS32_INSN_FLDI_BI, NDS32_INSN_FMADDD, NDS32_INSN_FMFDR,
+  NDS32_INSN_FMSUBD, NDS32_INSN_FMTDR, NDS32_INSN_FMULD, NDS32_INSN_FNMADDD,
+  NDS32_INSN_FNMSUBD, NDS32_INSN_FSD, NDS32_INSN_FSD_BI, NDS32_INSN_FSDI,
+  NDS32_INSN_FSDI_BI, NDS32_INSN_FSI2D, NDS32_INSN_FSQRTD, NDS32_INSN_FSUBD,
+  NDS32_INSN_FUI2D, NDS32_INSN_CPE1_CP1, NDS32_INSN_CPE1_CP2,
+  NDS32_INSN_CPE1_CP3, NDS32_INSN_CPE2_CP1, NDS32_INSN_CPE2_CP2,
+  NDS32_INSN_CPE2_CP3, NDS32_INSN_CPE3_CP1, NDS32_INSN_CPE3_CP2,
+  NDS32_INSN_CPE3_CP3, NDS32_INSN_CPE4_CP1, NDS32_INSN_CPE4_CP2,
+  NDS32_INSN_CPE4_CP3, NDS32_INSN_CPLD_CP1, NDS32_INSN_CPLD_BI_CP1,
+  NDS32_INSN_CPLDI_CP1, NDS32_INSN_CPLDI_BI_CP1, NDS32_INSN_CPLD_CP2,
+  NDS32_INSN_CPLD_BI_CP2, NDS32_INSN_CPLDI_CP2, NDS32_INSN_CPLDI_BI_CP2,
+  NDS32_INSN_CPLD_CP3, NDS32_INSN_CPLD_BI_CP3, NDS32_INSN_CPLDI_CP3,
+  NDS32_INSN_CPLDI_BI_CP3, NDS32_INSN_CPLW_CP1, NDS32_INSN_CPLW_BI_CP1,
+  NDS32_INSN_CPLWI_CP1, NDS32_INSN_CPLWI_BI_CP1, NDS32_INSN_CPLW_CP2,
+  NDS32_INSN_CPLW_BI_CP2, NDS32_INSN_CPLWI_CP2, NDS32_INSN_CPLWI_BI_CP2,
+  NDS32_INSN_CPLW_CP3, NDS32_INSN_CPLW_BI_CP3, NDS32_INSN_CPLWI_CP3,
+  NDS32_INSN_CPLWI_BI_CP3, NDS32_INSN_CPSD_CP1, NDS32_INSN_CPSD_BI_CP1,
+  NDS32_INSN_CPSDI_CP1, NDS32_INSN_CPSDI_BI_CP1, NDS32_INSN_CPSD_CP2,
+  NDS32_INSN_CPSD_BI_CP2, NDS32_INSN_CPSDI_CP2, NDS32_INSN_CPSDI_BI_CP2,
+  NDS32_INSN_CPSD_CP3, NDS32_INSN_CPSD_BI_CP3, NDS32_INSN_CPSDI_CP3,
+  NDS32_INSN_CPSDI_BI_CP3, NDS32_INSN_CPSW_CP1, NDS32_INSN_CPSW_BI_CP1,
+  NDS32_INSN_CPSWI_CP1, NDS32_INSN_CPSWI_BI_CP1, NDS32_INSN_CPSW_CP2,
+  NDS32_INSN_CPSW_BI_CP2, NDS32_INSN_CPSWI_CP2, NDS32_INSN_CPSWI_BI_CP2,
+  NDS32_INSN_CPSW_CP3, NDS32_INSN_CPSW_BI_CP3, NDS32_INSN_CPSWI_CP3,
+  NDS32_INSN_CPSWI_BI_CP3, NDS32_INSN_MFCPD_CP1, NDS32_INSN_MTCPD_CP1,
+  NDS32_INSN_MFCPD_CP2, NDS32_INSN_MTCPD_CP2, NDS32_INSN_MFCPD_CP3,
+  NDS32_INSN_MTCPD_CP3, NDS32_INSN_MFCPW_CP1, NDS32_INSN_MTCPW_CP1,
+  NDS32_INSN_MFCPW_CP2, NDS32_INSN_MTCPW_CP2, NDS32_INSN_MFCPW_CP3,
+  NDS32_INSN_MTCPW_CP3, NDS32_INSN_MFCPPW_CP1, NDS32_INSN_MTCPPW_CP1,
+  NDS32_INSN_MFCPPW_CP2, NDS32_INSN_MTCPPW_CP2, NDS32_INSN_MFCPPW_CP3,
+  NDS32_INSN_MTCPPW_CP3, NDS32_INSN_FFB, NDS32_INSN_FFBI, NDS32_INSN_FFMISM,
+  NDS32_INSN_FLMISM, NDS32_INSN_FFZMISM, NDS32_INSN_KADDW, NDS32_INSN_KSUBW,
+  NDS32_INSN_KSLRAW, NDS32_INSN_KADDH, NDS32_INSN_KSUBH, NDS32_INSN_KDMBB,
+  NDS32_INSN_KDMBT, NDS32_INSN_KDMTB, NDS32_INSN_KDMTT, NDS32_INSN_KHMBB,
+  NDS32_INSN_KHMBT, NDS32_INSN_KHMTB, NDS32_INSN_KHMTT, NDS32_INSN_RDOV,
+  NDS32_INSN_CLROV, NDS32_INSN_IFCALL9, NDS32_INSN_IFCALL, NDS32_INSN_IFRET,
+  NDS32_INSN_EX5_IT, NDS32_INSN_EX9_IT
+};
+
+#endif