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Re: [committed] Remove MIPS +D and +T operands
- From: Anders Montonen <Anders dot Montonen at iki dot fi>
- To: "Maciej W. Rozycki" <macro at codesourcery dot com>
- Cc: Richard Sandiford <rdsandiford at googlemail dot com>, <binutils at sourceware dot org>
- Date: Thu, 11 Jul 2013 20:52:35 +0300
- Subject: Re: [committed] Remove MIPS +D and +T operands
- References: <87txk65zy0 dot fsf at talisman dot default> <alpine dot DEB dot 1 dot 10 dot 1307081800580 dot 20590 at tp dot orcam dot me dot uk> <87wqp04yk1 dot fsf at talisman dot default> <alpine dot DEB dot 1 dot 10 dot 1307082150560 dot 20590 at tp dot orcam dot me dot uk>
On Jul 11, 2013, at 20:22, Maciej W. Rozycki wrote:
> As of the MIPS II ISA the opcodes LWC0 and SWC0 could use were taken for
> the LL and SC instruction respectively. Therefore to find out whether
> they really existed anywhere only the original MIPS I ISA can be
FWIW, the description of lwc1 in "See MIPS Run" (1st ed.) includes the remark "Instructions to load other coprocessors' registers are defined but have never been implemented." A similar notice is found in the description for swc1.