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Re: [committed] Remove MIPS +D and +T operands
- From: Richard Sandiford <rdsandiford at googlemail dot com>
- To: "Maciej W. Rozycki" <macro at codesourcery dot com>
- Cc: <binutils at sourceware dot org>
- Date: Mon, 08 Jul 2013 20:54:54 +0100
- Subject: Re: [committed] Remove MIPS +D and +T operands
- References: <87txk65zy0 dot fsf at talisman dot default> <alpine dot DEB dot 1 dot 10 dot 1307081800580 dot 20590 at tp dot orcam dot me dot uk>
"Maciej W. Rozycki" <email@example.com> writes:
> On Sun, 7 Jul 2013, Richard Sandiford wrote:
>> This patch removes the "+D" and "+T" entries and gets the disassembler to
>> look directly for ",H". It also uses a "0" at the end of the opcode
>> name to distinguish coprocessor 0 instructions; this showed that the
>> MIPS I LWC0 instruction wasn't being treated as coprocessor 0.
> But why do we support things like LWC0 or SWC0 in the first place?
> There are no such instructions.
No idea, sorry. Maybe a processor-specific extension?