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Hi Catherine,

"Moore, Catherine" <> writes:
> @@ -731,7 +738,7 @@ static const unsigned int mips_isa_table
>  #define INSN_OCTEON2		  0x00000100
>  /* Masks used for MIPS-defined ASEs.  */
> -#define INSN_ASE_MASK		  0x3c00f0d0
> +#define INSN_ASE_MASK		  0x3c00f0e0
>  /* DSP ASE */ 
>  #define INSN_DSP                  0x00001000
> @@ -784,7 +791,8 @@ static const unsigned int mips_isa_table
>  #define INSN_LOONGSON_3A          0x00000400
>  /* RMI Xlr instruction */
>  #define INSN_XLR              	  0x00000020
> -
> +/* MIPS32 Enhanced VA Scheme */
> +#define INSN_EVA                  0x00000040
>  /* MCU (MicroController) ASE */
>  #define INSN_MCU		  0x00000010

These don't match.  The INSN_ASE_MASK line removes 0x10 from the mask
(which isn't right; that's the INSN_MCU ASE bit) and adds 0x20 (which
is INSN_XLR, a processor mask).

0x40 is already in INSN_ASE_MASK and is used by INSN_VIRT64.  I'm afraid
there are no more bits left to claim, so we'll need to do something else.

One way would be to convert the ASE and/or the processor bits to enums,
like Maciej did with the ISA level, but you'd need to be careful about
cases where the same instruction is supported by several processor
extensions or (probably less likely) by several ASEs.  Perhaps a simpler
alternative would be to add a separate ASE field and move all current
ASEs to it.


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