This is the mail archive of the binutils@sourceware.org mailing list for the binutils project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: [Ping, PATCH, avr] Allow XCH, LAT, LAC and LAS instructions only for XMEGA devices that support them


Committed.

2013/5/29 Denis Chertykov <chertykov@gmail.com>:
> Thank you for your patch.
> I just havn't a time to apply it.
>
> Denis.
>
> 2013/5/28 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>:
>> Ping!
>>
>> Regards
>> Senthil
>>
>> On Tue, May 21, 2013 at 04:03:23PM +0530, Senthil Kumar Selvaraj wrote:
>>> This patch associates RMW instructions (XCH, LAC, LAT and LAS)
>>> with a new AVR_ISA_XMEGAU ISA, and removes the existing association
>>> with XMEGA ISA. It also changes the ISA for devices with RMW support to
>>> AVR_ISA_XMEGAU.
>>>
>>> This change allows the assembler to reject RMW instructions for
>>> XMEGA devices that don't support them.
>>>
>>> If ok, could someone commit please?
>>>
>>> Regards
>>> Senthil
>>>
>>> gas/ChangeLog
>>> 2013-05-08  George Thomas <george.thomas@atmel.com>
>>>
>>>       * gas/config/tc-avr.c: Change ISA for devices with USB support to
>>>     AVR_ISA_XMEGAU
>>>
>>> ChangeLog
>>>
>>>       * include/opcode/avr.h: Rename AVR_ISA_XCH to AVR_ISA_RMW. Remove
>>>       from AVR_ISA_XMEGA and add new AVR_ISA_XMEGAU
>>>
>>>
>>> diff --git gas/config/tc-avr.c gas/config/tc-avr.c
>>> index a673fe1..285aa7c 100644
>>> --- gas/config/tc-avr.c
>>> +++ gas/config/tc-avr.c
>>> @@ -268,18 +268,18 @@ static struct mcu_type_s mcu_types[] =
>>>    {"atxmega64a3", AVR_ISA_XMEGA,  bfd_mach_avrxmega4},
>>>    {"atxmega64d3", AVR_ISA_XMEGA,  bfd_mach_avrxmega4},
>>>    {"atxmega64a1", AVR_ISA_XMEGA,  bfd_mach_avrxmega5},
>>> -  {"atxmega64a1u",AVR_ISA_XMEGA,  bfd_mach_avrxmega5},
>>> +  {"atxmega64a1u",AVR_ISA_XMEGAU, bfd_mach_avrxmega5},
>>>    {"atxmega128a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
>>> -  {"atxmega128b1", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
>>> +  {"atxmega128b1", AVR_ISA_XMEGAU, bfd_mach_avrxmega6},
>>>    {"atxmega128d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
>>>    {"atxmega192a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
>>>    {"atxmega192d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
>>>    {"atxmega256a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
>>>    {"atxmega256a3b",AVR_ISA_XMEGA, bfd_mach_avrxmega6},
>>> -  {"atxmega256a3bu",AVR_ISA_XMEGA,bfd_mach_avrxmega6},
>>> +  {"atxmega256a3bu",AVR_ISA_XMEGAU, bfd_mach_avrxmega6},
>>>    {"atxmega256d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
>>>    {"atxmega128a1", AVR_ISA_XMEGA, bfd_mach_avrxmega7},
>>> -  {"atxmega128a1u", AVR_ISA_XMEGA, bfd_mach_avrxmega7},
>>> +  {"atxmega128a1u", AVR_ISA_XMEGAU, bfd_mach_avrxmega7},
>>>    {NULL, 0, 0}
>>>  };
>>>
>>> diff --git include/opcode/avr.h include/opcode/avr.h
>>> index 6e86c07..f1d73ad 100644
>>> --- include/opcode/avr.h
>>> +++ include/opcode/avr.h
>>> @@ -33,7 +33,7 @@
>>>  #define AVR_ISA_MOVW  0x1000 /* device has MOVW */
>>>  #define AVR_ISA_SPMX  0x2000 /* device has SPM Z[+] */
>>>  #define AVR_ISA_DES   0x4000 /* device has DES */
>>> -#define AVR_ISA_XCH   0x8000 /* device has XCH, LAC, LAS, LAT */
>>> +#define AVR_ISA_RMW   0x8000 /* device has RMW instructions XCH,LAC,LAS,LAT */
>>>
>>>  #define AVR_ISA_TINY1 (AVR_ISA_1200 | AVR_ISA_LPM)
>>>  #define AVR_ISA_2xxx  (AVR_ISA_TINY1 | AVR_ISA_SRAM)
>>> @@ -53,7 +53,8 @@
>>>  #define AVR_ISA_M323  (AVR_ISA_M161 | AVR_ISA_BRK)
>>>  #define AVR_ISA_M128  (AVR_ISA_M323 | AVR_ISA_ELPM | AVR_ISA_ELPMX)
>>>  #define AVR_ISA_M256  (AVR_ISA_M128 | AVR_ISA_EIND)
>>> -#define AVR_ISA_XMEGA (AVR_ISA_M256 | AVR_ISA_SPMX | AVR_ISA_DES | AVR_ISA_XCH)
>>> +#define AVR_ISA_XMEGA (AVR_ISA_M256 | AVR_ISA_SPMX | AVR_ISA_DES)
>>> +#define AVR_ISA_XMEGAU (AVR_ISA_XMEGA | AVR_ISA_RMW)
>>>
>>>  #define AVR_ISA_AVR1   AVR_ISA_TINY1
>>>  #define AVR_ISA_AVR2   AVR_ISA_2xxx
>>> @@ -266,10 +267,10 @@ AVR_INSN (ror,  "r",   "1001010rrrrr0111", 1, AVR_ISA_1200, 0x9407)
>>>  AVR_INSN (swap, "r",   "1001010rrrrr0010", 1, AVR_ISA_1200, 0x9402)
>>>
>>>     /* Atomic memory operations for XMEGA.  List before `sts'.  */
>>> -AVR_INSN (xch,  "z,r",   "1001001rrrrr0100", 1, AVR_ISA_XCH, 0x9204)
>>> -AVR_INSN (las,  "z,r",   "1001001rrrrr0101", 1, AVR_ISA_XCH, 0x9205)
>>> -AVR_INSN (lac,  "z,r",   "1001001rrrrr0110", 1, AVR_ISA_XCH, 0x9206)
>>> -AVR_INSN (lat,  "z,r",   "1001001rrrrr0111", 1, AVR_ISA_XCH, 0x9207)
>>> +AVR_INSN (xch,  "z,r",   "1001001rrrrr0100", 1, AVR_ISA_RMW, 0x9204)
>>> +AVR_INSN (las,  "z,r",   "1001001rrrrr0101", 1, AVR_ISA_RMW, 0x9205)
>>> +AVR_INSN (lac,  "z,r",   "1001001rrrrr0110", 1, AVR_ISA_RMW, 0x9206)
>>> +AVR_INSN (lat,  "z,r",   "1001001rrrrr0111", 1, AVR_ISA_RMW, 0x9207)
>>>
>>>     /* Known to be decoded as `nop' by the old core.  */
>>>  AVR_INSN (movw, "v,v", "00000001ddddrrrr", 1, AVR_ISA_MOVW, 0x0100)


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]