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Re: [PATCH] arm: allow SIMD instructions to be used without VFP support enabled
- From: "Jan Beulich" <JBeulich at suse dot com>
- To: "Richard Earnshaw" <rearnsha at arm dot com>
- Cc: "paul at codesourcery dot com" <paul at codesourcery dot com>, "nickc at redhat dot com" <nickc at redhat dot com>, "binutils at sourceware dot org" <binutils at sourceware dot org>
- Date: Tue, 09 Apr 2013 10:04:57 +0100
- Subject: Re: [PATCH] arm: allow SIMD instructions to be used without VFP support enabled
- References: <5162F06D02000078000CB5DC at nat28 dot tlf dot novell dot com> <5162E529 dot 1080404 at arm dot com> <5163028802000078000CB67A at nat28 dot tlf dot novell dot com> <5162F0E9 dot 3070109 at arm dot com> <5163D96602000078000CB96D at nat28 dot tlf dot novell dot com> <5163D21D dot 6020600 at arm dot com>
>>> On 09.04.13 at 10:32, Richard Earnshaw <firstname.lastname@example.org> wrote:
> On 09/04/13 08:03, Jan Beulich wrote:
> The only thing that's useful to think about is what is permitted by the
> architecture. The architecture only permits INT_NEON + FP_NEON + FP, FP
> (in various guises) and INT_NEON. It doesn't make sense to me to allow
> other random permutations. Ergo
> .arch_extension "neon"
> .arch_extension "nofp"
> should give INT_NEON in the terminology above.
Mind pointing me to where this is stated? As said, the FPSID and
MVFRx register descriptions in the v7-A and v7-R edition of the
ARM Architecture Reference Manual don't say anything to that
effect according to my reading.