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Re: [PATCH] arm: allow SIMD instructions to be used without VFP support enabled
- From: Richard Earnshaw <rearnsha at arm dot com>
- To: Jan Beulich <JBeulich at suse dot com>
- Cc: "paul at codesourcery dot com" <paul at codesourcery dot com>, "nickc at redhat dot com" <nickc at redhat dot com>, "binutils at sourceware dot org" <binutils at sourceware dot org>
- Date: Tue, 09 Apr 2013 09:32:29 +0100
- Subject: Re: [PATCH] arm: allow SIMD instructions to be used without VFP support enabled
- References: <5162F06D02000078000CB5DC at nat28 dot tlf dot novell dot com> <5162E529 dot 1080404 at arm dot com> <5163028802000078000CB67A at nat28 dot tlf dot novell dot com> <5162F0E9 dot 3070109 at arm dot com> <5163D96602000078000CB96D at nat28 dot tlf dot novell dot com>
On 09/04/13 08:03, Jan Beulich wrote:
On 08.04.13 at 18:31, Richard Earnshaw <email@example.com> wrote:
The class of common mnemonics you've changed includes instructions such
as vmul. When you have Neon but no FP, both the scalar FP and vector FP
variants of the instructions should be disabled, but the integer
By example of vabs I already know that this isn't the case -
vabs.f32 (with Dn or Qn register operands) continues to assemble
The fundamental question here is what the meaning of
and its "nofp" counterpart really is: The current meaning is to
enable/disable VFP, not floating point support in general. And
again, according to my reading of the spec you'd need a
separate enable/disable for SIMD-without-FP first in order to
achieve the effect you appear to aim at (iow to me "no VFP"
does not imply integer only SIMD, no matter whether in actual
implementations this will likely be the case, as there's no
dependency mentioned in the FPSID and MVFRx registers).
The only thing that's useful to think about is what is permitted by the
architecture. The architecture only permits INT_NEON + FP_NEON + FP, FP
(in various guises) and INT_NEON. It doesn't make sense to me to allow
other random permutations. Ergo
should give INT_NEON in the terminology above.