This is the mail archive of the binutils@sourceware.org mailing list for the binutils project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

[PATCH] Add initial POWER8 and HTM support


IBM has released some early POWER8 ISA details, specifically information
about the Hardware Transactional Memory (HTM) facility:

  https://www.power.org/documentation/power-isa-transactional-memory/

The following patch adds support for the POWER8 and HTM options, as
well as the new HTM instructions.  Further patches will be submitted
as IBM releases more POWER8 information.

This builds and passes the testsuite.  Is this ok for trunk?

Peter



include/opcode/
	* ppc.h (PPC_OPCODE_POWER8): New define.
	(PPC_OPCODE_HTM): Likewise.

opcodes/
	* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
	* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
	XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
	(SH6): Update.
	<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
	"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
	"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
	<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.

gas/
	* doc/as.texinfo (Target PowerPC): Document -mpower8 and -mhtm.
	* doc/c-ppc.texi (PowerPC-Opts):  Likewise.
	* config/tc-ppc.c (md_show_usage): Likewise.
	(ppc_handle_align): Handle power8's group ending nop.

gas/testsuite/
	* gas/ppc/htm.d: New test.
	* gas/ppc/htm.s: Likewise.
	* gas/ppc/power8.d: Likewise.
	* gas/ppc/power8.s: Likewise.
	* gas/ppc/ppc.exp: Run them.

Index: include/opcode/ppc.h
===================================================================
RCS file: /cvs/src/src/include/opcode/ppc.h,v
retrieving revision 1.45
diff -u -p -r1.45 ppc.h
--- include/opcode/ppc.h	23 Nov 2012 03:28:09 -0000	1.45
+++ include/opcode/ppc.h	10 Jan 2013 20:01:25 -0000
@@ -188,6 +188,14 @@ extern const int vle_num_opcodes;
 /* Opcode which is supported by the VLE extension.  */
 #define PPC_OPCODE_VLE	      0x1000000000ull
 
+/* Opcode is only supported by Power8 architecture.  */
+#define PPC_OPCODE_POWER8     0x2000000000ull
+
+/* Opcode which is supported by the Hardware Transactional Memory extension.  */
+/* Currently, this is the same as the POWER8 mask.  If another cpu comes out
+   that isn't a superset of POWER8, we can define this to its own mask.  */
+#define PPC_OPCODE_HTM        PPC_OPCODE_POWER8
+
 /* A macro to extract the major opcode from an instruction.  */
 #define PPC_OP(i) (((i) >> 26) & 0x3f)
 
Index: opcodes/ppc-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/ppc-dis.c,v
retrieving revision 1.61
diff -u -p -r1.61 ppc-dis.c
--- opcodes/ppc-dis.c	23 Nov 2012 03:28:11 -0000	1.61
+++ opcodes/ppc-dis.c	10 Jan 2013 20:01:26 -0000
@@ -147,6 +147,11 @@ struct ppc_mopt ppc_opts[] = {
 		| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 		| PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
     0 },
+  { "power8",  (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
+		| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
+		| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8 | PPC_OPCODE_HTM
+		| PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_VSX),
+    0 },
   { "ppc",     (PPC_OPCODE_PPC),
     0 },
   { "ppc32",   (PPC_OPCODE_PPC),
@@ -176,6 +181,11 @@ struct ppc_mopt ppc_opts[] = {
 		| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
 		| PPC_OPCODE_POWER7 | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX),
     0 },
+  { "pwr8",    (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_64
+		| PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6
+		| PPC_OPCODE_POWER7 | PPC_OPCODE_POWER8
+		| PPC_OPCODE_ALTIVEC | PPC_OPCODE_ALTIVEC2 | PPC_OPCODE_VSX),
+    0 },
   { "pwrx",    (PPC_OPCODE_POWER | PPC_OPCODE_POWER2),
     0 },
   { "spe",     (PPC_OPCODE_PPC | PPC_OPCODE_EFS),
@@ -187,6 +197,8 @@ struct ppc_mopt ppc_opts[] = {
     PPC_OPCODE_VLE },
   { "vsx",     (PPC_OPCODE_PPC),
     PPC_OPCODE_VSX },
+  { "htm",     (PPC_OPCODE_PPC),
+    PPC_OPCODE_HTM },
 };
 
 /* Switch between Booke and VLE dialects for interlinked dumps.  */
Index: opcodes/ppc-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/ppc-opc.c,v
retrieving revision 1.157
diff -u -p -r1.157 ppc-opc.c
--- opcodes/ppc-opc.c	13 Dec 2012 07:46:13 -0000	1.157
+++ opcodes/ppc-opc.c	10 Jan 2013 20:01:26 -0000
@@ -388,6 +388,8 @@ const struct powerpc_operand powerpc_ope
 
   /* The L field in a D or X form instruction.  */
 #define L IMM20 + 1
+  /* The R field in a HTM X form instruction.  */
+#define HTM_R L
   { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 
   /* The LEV field in a POWER SVC form instruction.  */
@@ -572,8 +574,12 @@ const struct powerpc_operand powerpc_ope
 #define EVUIMM SH
   { 0x1f, 11, NULL, NULL, 0 },
 
+  /* The SI field in a HTM X form instruction.  */
+#define HTM_SI SH + 1
+  { 0x1f, 11, NULL, NULL, PPC_OPERAND_SIGNED },
+
   /* The SH field in an MD form instruction.  This is split.  */
-#define SH6 SH + 1
+#define SH6 HTM_SI + 1
 #define SH6_MASK ((0x1f << 11) | (1 << 1))
   { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 },
 
@@ -757,7 +763,9 @@ const struct powerpc_operand powerpc_ope
   { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
 
   /* The L field in an mtfsf or XFL form instruction.  */
+  /* The A field in a HTM X form instruction.  */
 #define XFL_L EH + 1
+#define HTM_A XFL_L
   { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
 
   /* Xilinx APU related masks and macros */
@@ -2427,15 +2435,33 @@ extract_vleil (unsigned long insn,
 /* An X_MASK with the RT and RA fields fixed.  */
 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
 
+/* An X_MASK with the RT and RB fields fixed.  */
+#define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK)
+
 /* An XRTRA_MASK, but with L bit clear.  */
 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
 
+/* An X_MASK with the RT, RA and RB fields fixed.  */
+#define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK)
+
+/* An XRTRARB_MASK, but with L bit clear.  */
+#define XRTLRARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 21))
+
+/* An XRTRARB_MASK, but with A bit clear.  */
+#define XRTARARB_MASK (XRTRARB_MASK & ~((unsigned long) 1 << 25))
+
+/* An XRTRARB_MASK, but with BF bits clear.  */
+#define XRTBFRARB_MASK (XRTRARB_MASK & ~((unsigned long) 7 << 23))
+
 /* An X form instruction with the L bit specified.  */
 #define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
 
 /* An X form instruction with the L bits specified.  */
 #define XOPL2(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
 
+/* An X form instruction with the L bit and RC bit specified.  */
+#define XRCL(op, xop, l, rc) (XRC ((op), (xop), (rc)) | ((((unsigned long)(l)) & 1) << 21))
+
 /* An X form instruction with RT fields specified */
 #define XRT(op, xop, rt) (X ((op), (xop)) \
         | ((((unsigned long)(rt)) & 0x1f) << 21))
@@ -2659,6 +2685,7 @@ extract_vleil (unsigned long insn,
 #define POWER5	PPC_OPCODE_POWER5
 #define POWER6	PPC_OPCODE_POWER6
 #define POWER7	PPC_OPCODE_POWER7
+#define POWER8	PPC_OPCODE_POWER8
 #define CELL	PPC_OPCODE_CELL
 #define PPC64	PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
 #define NON32	(PPC_OPCODE_64 | PPC_OPCODE_POWER4	\
@@ -2702,6 +2729,7 @@ extract_vleil (unsigned long insn,
 #define E500	PPC_OPCODE_E500
 #define E6500	PPC_OPCODE_E6500
 #define PPCVLE  PPC_OPCODE_VLE
+#define PPCHTM  PPC_OPCODE_HTM
 
 /* The opcode table.
 
@@ -5315,6 +5343,8 @@ const struct powerpc_opcode powerpc_opco
 {"stvlx",	X(31,647),	X_MASK,      CELL,	PPCNONE,	{VS, RA0, RB}},
 {"stbfcmux",	APU(31,647,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
 
+{"tbegin.",	XRC(31,654,1), XRTLRARB_MASK,PPCHTM,	PPCNONE,	{HTM_R}},
+
 {"subfeo",	XO(31,136,1,0),	XO_MASK, PPCCOM|PPCVLE, PPCNONE,	{RT, RA, RB}},
 {"sfeo",	XO(31,136,1,0),	XO_MASK,     PWRCOM,	PPCNONE,	{RT, RA, RB}},
 {"subfeo.",	XO(31,136,1,1),	XO_MASK, PPCCOM|PPCVLE, PPCNONE,	{RT, RA, RB}},
@@ -5350,6 +5380,9 @@ const struct powerpc_opcode powerpc_opco
 {"stvrx",	X(31,679),	X_MASK,      CELL,	PPCNONE,	{VS, RA0, RB}},
 {"sthfcmux",	APU(31,679,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
 
+{"tendall.",	XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, PPCNONE,	{0}},
+{"tend.",	XRC(31,686,1), XRTARARB_MASK, PPCHTM,	PPCNONE,	{HTM_A}},
+
 {"stbcx.",	XRC(31,694,1),	X_MASK,      POWER7,	PPCNONE,	{RS, RA0, RB}},
 
 {"stfsux",	X(31,695),	X_MASK,      COM,	PPCEFS,		{FRS, RAS, RB}},
@@ -5365,6 +5398,8 @@ const struct powerpc_opcode powerpc_opco
 
 {"stxsdx",	X(31,716),	XX1_MASK,    PPCVSX,	PPCNONE,	{XS6, RA0, RB}},
 
+{"tcheck",	X(31,718),   XRTBFRARB_MASK, PPCHTM,	PPCNONE,	{BF}},
+
 {"subfzeo",	XO(31,200,1,0),	XORB_MASK, PPCCOM|PPCVLE, PPCNONE,	{RT, RA}},
 {"sfzeo",	XO(31,200,1,0),	XORB_MASK,   PWRCOM,	PPCNONE,	{RT, RA}},
 {"subfzeo.",	XO(31,200,1,1),	XORB_MASK, PPCCOM|PPCVLE, PPCNONE,	{RT, RA}},
@@ -5415,6 +5450,10 @@ const struct powerpc_opcode powerpc_opco
 {"mullwo.",	XO(31,235,1,1),	XO_MASK,     PPCCOM|PPCVLE, PPCNONE,	{RT, RA, RB}},
 {"mulso.",	XO(31,235,1,1),	XO_MASK,     PWRCOM,	PPCNONE,	{RT, RA, RB}},
 
+{"tsuspend.",	XRCL(31,750,0,1), XRTRARB_MASK,PPCHTM,	PPCNONE,	{0}},
+{"tresume.",	XRCL(31,750,1,1), XRTRARB_MASK,PPCHTM,	PPCNONE,	{0}},
+{"tsr.",	XRC(31,750,1),    XRTLRARB_MASK,PPCHTM,	PPCNONE,	{L}},
+
 {"dcba",	X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RA0, RB}},
 {"dcbal",	XOPL(31,758,1), XRT_MASK,    E500MC,	PPCNONE,	{RA0, RB}},
 
@@ -5438,6 +5477,8 @@ const struct powerpc_opcode powerpc_opco
 
 {"lxvw4x",	X(31,780),	XX1_MASK,    PPCVSX,	PPCNONE,	{XT6, RA0, RB}},
 
+{"tabortwc.",	XRC(31,782,1),	X_MASK,      PPCHTM,	PPCNONE,	{TO, RA, RB}},
+
 {"tlbivax",	X(31,786),	XRT_MASK, BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RA0, RB}},
 
 {"lwzcix",	X(31,789),	X_MASK,      POWER6,	PPCNONE,	{RT, RA0, RB}},
@@ -5461,6 +5502,8 @@ const struct powerpc_opcode powerpc_opco
 {"stvepx",	X(31,807),	X_MASK,      PPCVEC2,	PPCNONE,	{VS, RA0, RB}},
 {"lvrxl",	X(31,807),	X_MASK,      CELL,	PPCNONE,	{VD, RA0, RB}},
 
+{"tabortdc.",	XRC(31,814,1),	X_MASK,      PPCHTM,	PPCNONE,	{TO, RA, RB}},
+
 {"rac",		X(31,818),	X_MASK,      M601,	PPCNONE,	{RT, RA, RB}},
 
 {"erativax",	X(31,819),	X_MASK,	     PPCA2,	PPCNONE,	{RS, RA0, RB}},
@@ -5486,6 +5529,8 @@ const struct powerpc_opcode powerpc_opco
 
 {"lxvd2x",	X(31,844),	XX1_MASK,    PPCVSX,	PPCNONE,	{XT6, RA0, RB}},
 
+{"tabortwci.",	XRC(31,846,1),	X_MASK,      PPCHTM,	PPCNONE,	{TO, RA, HTM_SI}},
+
 {"tlbsrx.",	XRC(31,850,1),	XRT_MASK,    PPCA2,	PPCNONE,	{RA0, RB}},
 
 {"slbmfev",	X(31,851),	XRA_MASK,    PPC64,	PPCNONE,	{RT, RB}},
@@ -5507,6 +5552,8 @@ const struct powerpc_opcode powerpc_opco
 {"divso",	XO(31,363,1,0),	XO_MASK,     M601,	PPCNONE,	{RT, RA, RB}},
 {"divso.",	XO(31,363,1,1),	XO_MASK,     M601,	PPCNONE,	{RT, RA, RB}},
 
+{"tabortdci.",	XRC(31,878,1),	X_MASK,      PPCHTM,	PPCNONE,	{TO, RA, HTM_SI}},
+
 {"ldcix",	X(31,885),	X_MASK,      POWER6,	PPCNONE,	{RT, RA0, RB}},
 
 {"lfiwzx",	X(31,887),	X_MASK,   POWER7|PPCA2,	PPCNONE,	{FRT, RA0, RB}},
@@ -5521,6 +5568,8 @@ const struct powerpc_opcode powerpc_opco
 
 {"stxvw4x",	X(31,908),	XX1_MASK,    PPCVSX,	PPCNONE,	{XS6, RA0, RB}},
 
+{"tabort.",	XRC(31,910,1),	XRTRB_MASK,  PPCHTM,	PPCNONE,	{RA}},
+
 {"tlbsx",	XRC(31,914,0),	X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA0, RB}},
 {"tlbsx.",	XRC(31,914,1),	X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA0, RB}},
 
@@ -5559,6 +5608,8 @@ const struct powerpc_opcode powerpc_opco
 {"divweo",	XO(31,427,1,0),	XO_MASK,  POWER7|PPCA2,	PPCNONE,	{RT, RA, RB}},
 {"divweo.",	XO(31,427,1,1),	XO_MASK,  POWER7|PPCA2,	PPCNONE,	{RT, RA, RB}},
 
+{"treclaim.",	XRC(31,942,1),	XRTRB_MASK,  PPCHTM,	PPCNONE,	{RA}},
+
 {"tlbrehi",	XTLB(31,946,0),	XTLB_MASK,   PPC403,	PPCA2,		{RT, RA}},
 {"tlbrelo",	XTLB(31,946,1),	XTLB_MASK,   PPC403,	PPCA2,		{RT, RA}},
 {"tlbre",	X(31,946),	X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}},
@@ -5618,6 +5669,7 @@ const struct powerpc_opcode powerpc_opco
 {"divwo",	XO(31,491,1,0),	XO_MASK,   PPC|PPCVLE,	PPCNONE,	{RT, RA, RB}},
 {"divwo.",	XO(31,491,1,1),	XO_MASK,   PPC|PPCVLE,	PPCNONE,	{RT, RA, RB}},
 
+{"trechkpt.",	XRC(31,1006,1),	XRTRARB_MASK,PPCHTM,	PPCNONE,	{0}},
 
 {"tlbli",	X(31,1010),	XRTRA_MASK,  PPC,	TITAN,  	{RB}},
 
Index: gas/doc/as.texinfo
===================================================================
RCS file: /cvs/src/src/gas/doc/as.texinfo,v
retrieving revision 1.262
diff -u -p -r1.262 as.texinfo
--- gas/doc/as.texinfo	10 Jan 2013 09:49:09 -0000	1.262
+++ gas/doc/as.texinfo	10 Jan 2013 20:01:25 -0000
@@ -451,8 +451,8 @@ gcc(1), ld(1), and the Info entries for 
     @b{-m440}|@b{-m464}|@b{-m476}|@b{-m7400}|@b{-m7410}|@b{-m7450}|@b{-m7455}|@b{-m750cl}|@b{-mppc64}|
     @b{-m620}|@b{-me500}|@b{-e500x2}|@b{-me500mc}|@b{-me500mc64}|@b{-me5500}|@b{-me6500}|@b{-mppc64bridge}|
     @b{-mbooke}|@b{-mpower4}|@b{-mpwr4}|@b{-mpower5}|@b{-mpwr5}|@b{-mpwr5x}|@b{-mpower6}|@b{-mpwr6}|
-    @b{-mpower7}|@b{-mpwr7}|@b{-ma2}|@b{-mcell}|@b{-mspe}|@b{-mtitan}|@b{-me300}|@b{-mvle}|@b{-mcom}]
-   [@b{-many}] [@b{-maltivec}|@b{-mvsx}]
+    @b{-mpower7}|@b{-mpwr7}|@b{-mpower8}|@b{-mpwr8}|@b{-ma2}|@b{-mcell}|@b{-mspe}|@b{-mtitan}|@b{-me300}|@b{-mcom}]
+   [@b{-many}] [@b{-maltivec}|@b{-mvsx}|@b{-mhtm}|@b{-mvle}]
    [@b{-mregnames}|@b{-mno-regnames}]
    [@b{-mrelocatable}|@b{-mrelocatable-lib}|@b{-K PIC}] [@b{-memb}]
    [@b{-mlittle}|@b{-mlittle-endian}|@b{-le}|@b{-mbig}|@b{-mbig-endian}|@b{-be}]
Index: gas/doc/c-ppc.texi
===================================================================
RCS file: /cvs/src/src/gas/doc/c-ppc.texi,v
retrieving revision 1.24
diff -u -p -r1.24 c-ppc.texi
--- gas/doc/c-ppc.texi	5 Sep 2012 18:01:00 -0000	1.24
+++ gas/doc/c-ppc.texi	10 Jan 2013 20:01:25 -0000
@@ -121,6 +121,9 @@ Generate code for Freescale PowerPC VLE 
 @item -mvsx
 Generate code for processors with Vector-Scalar (VSX) instructions.
 
+@item -mhtm
+Generate code for processors with Hardware Transactional Memory instructions.
+
 @item -mpower4, -mpwr4
 Generate code for Power4 architecture.
 
@@ -133,6 +136,10 @@ Generate code for Power6 architecture.
 @item -mpower7, -mpwr7
 Generate code for Power7 architecture.
 
+@item -mpower8, -mpwr8
+Generate code for Power8 architecture.
+
+@item -mcell
 @item -mcell
 Generate code for Cell Broadband Engine architecture.
 
Index: gas/config/tc-ppc.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-ppc.c,v
retrieving revision 1.192
diff -u -p -r1.192 tc-ppc.c
--- gas/config/tc-ppc.c	23 Nov 2012 03:28:12 -0000	1.192
+++ gas/config/tc-ppc.c	10 Jan 2013 20:01:25 -0000
@@ -1302,12 +1302,14 @@ PowerPC options:\n\
                         generate code for Power5 architecture\n\
 -mpower6, -mpwr6        generate code for Power6 architecture\n\
 -mpower7, -mpwr7        generate code for Power7 architecture\n\
+-mpower8, -mpwr8        generate code for Power8 architecture\n\
 -mcell                  generate code for Cell Broadband Engine architecture\n\
 -mcom                   generate code Power/PowerPC common instructions\n\
 -many                   generate code for any architecture (PWR/PWRX/PPC)\n"));
   fprintf (stream, _("\
 -maltivec               generate code for AltiVec\n\
 -mvsx                   generate code for Vector-Scalar (VSX) instructions\n\
+-mhtm                   generate code for Hardware Transactional Memory\n\
 -me300                  generate code for PowerPC e300 family\n\
 -me500, -me500x2        generate code for Motorola e500 core complex\n\
 -me500mc,               generate code for Freescale e500mc core complex\n\
@@ -6265,9 +6267,10 @@ ppc_handle_align (struct frag *fragP)
       md_number_to_chars (dest, 0x60000000, 4);
 
       if ((ppc_cpu & PPC_OPCODE_POWER6) != 0
-	  || (ppc_cpu & PPC_OPCODE_POWER7) != 0)
+	  || (ppc_cpu & PPC_OPCODE_POWER7) != 0
+	  || (ppc_cpu & PPC_OPCODE_POWER8) != 0)
 	{
-	  /* For power6 and power7, we want the last nop to be a group
+	  /* For power6, power7 and power8, we want the last nop to be a group
 	     terminating one.  Do this by inserting an rs_fill frag immediately
 	     after this one, with its address set to the last nop location.
 	     This will automatically reduce the number of nops in the current
@@ -6285,13 +6288,14 @@ ppc_handle_align (struct frag *fragP)
 	      dest = group_nop->fr_literal;
 	    }
 
-	  if ((ppc_cpu & PPC_OPCODE_POWER7) != 0)
+	  if ((ppc_cpu & PPC_OPCODE_POWER7) != 0
+	      || (ppc_cpu & PPC_OPCODE_POWER8) != 0)
 	    {
 	      if (ppc_cpu & PPC_OPCODE_E500MC)
 		/* e500mc group terminating nop: "ori 0,0,0".  */
 		md_number_to_chars (dest, 0x60000000, 4);
 	      else
-		/* power7 group terminating nop: "ori 2,2,0".  */
+		/* power7/power8 group terminating nop: "ori 2,2,0".  */
 		md_number_to_chars (dest, 0x60420000, 4);
 	    }
 	  else
Index: gas/testsuite/gas/ppc/htm.d
===================================================================
RCS file: gas/testsuite/gas/ppc/htm.d
diff -N gas/testsuite/gas/ppc/htm.d
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/ppc/htm.d	10 Jan 2013 20:01:25 -0000
@@ -0,0 +1,26 @@
+#as: -mhtm
+#objdump: -dr -Mhtm
+#name: Hardware Transactional Memory (HTM) tests
+
+.*: +file format elf(32)?(64)?-powerpc.*
+
+Disassembly of section \.text:
+
+0+00 <htm>:
+   0:	(7c 05 07 1d|1d 07 05 7c) 	tabort\. r5
+   4:	(7c e8 86 1d|1d 86 e8 7c) 	tabortwc\. 7,r8,r16
+   8:	(7e 8b 56 5d|5d 56 8b 7e) 	tabortdc\. 20,r11,r10
+   c:	(7e 2a 9e 9d|9d 9e 2a 7e) 	tabortwci\. 17,r10,-13
+  10:	(7f a3 de dd|dd de a3 7f) 	tabortdci\. 29,r3,-5
+  14:	(7c 00 05 1d|1d 05 00 7c) 	tbegin\. 
+  18:	(7f 80 05 9c|9c 05 80 7f) 	tcheck  cr7
+  1c:	(7c 00 05 5d|5d 05 00 7c) 	tend\.   
+  20:	(7c 00 05 5d|5d 05 00 7c) 	tend\.   
+  24:	(7e 00 05 5d|5d 05 00 7e) 	tendall\.
+  28:	(7e 00 05 5d|5d 05 00 7e) 	tendall\.
+  2c:	(7c 18 07 5d|5d 07 18 7c) 	treclaim\. r24
+  30:	(7c 00 07 dd|dd 07 00 7c) 	trechkpt\.
+  34:	(7c 00 05 dd|dd 05 00 7c) 	tsuspend\.
+  38:	(7c 00 05 dd|dd 05 00 7c) 	tsuspend\.
+  3c:	(7c 20 05 dd|dd 05 20 7c) 	tresume\.
+  40:	(7c 20 05 dd|dd 05 20 7c) 	tresume\.
Index: gas/testsuite/gas/ppc/htm.s
===================================================================
RCS file: gas/testsuite/gas/ppc/htm.s
diff -N gas/testsuite/gas/ppc/htm.s
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/ppc/htm.s	10 Jan 2013 20:01:25 -0000
@@ -0,0 +1,19 @@
+	.section	".text"
+htm:
+	tabort.      5
+	tabortwc.    7,8,16
+	tabortdc.    20,11,10
+	tabortwci.   17,10,-13
+	tabortdci.   29,3,-5
+	tbegin.      0
+	tcheck       7
+	tend.        0
+	tend.
+	tend.        1
+	tendall.     
+	treclaim.    24
+	trechkpt.    
+	tsr.         0
+	tsuspend.    
+	tsr.         1
+	tresume.     
Index: gas/testsuite/gas/ppc/power8.d
===================================================================
RCS file: gas/testsuite/gas/ppc/power8.d
diff -N gas/testsuite/gas/ppc/power8.d
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/ppc/power8.d	10 Jan 2013 20:01:25 -0000
@@ -0,0 +1,29 @@
+#as: -mpower8
+#objdump: -dr -Mpower8
+#name: POWER8 tests (includes Altivec, VSX and HTM)
+
+.*: +file format elf(32)?(64)?-powerpc.*
+
+Disassembly of section \.text:
+
+0+00 <power8>:
+   0:	(7c 05 07 1d|1d 07 05 7c) 	tabort\. r5
+   4:	(7c e8 86 1d|1d 86 e8 7c) 	tabortwc\. 7,r8,r16
+   8:	(7e 8b 56 5d|5d 56 8b 7e) 	tabortdc\. 20,r11,r10
+   c:	(7e 2a 9e 9d|9d 9e 2a 7e) 	tabortwci\. 17,r10,-13
+  10:	(7f a3 de dd|dd de a3 7f) 	tabortdci\. 29,r3,-5
+  14:	(7c 00 05 1d|1d 05 00 7c) 	tbegin\. 
+  18:	(7f 80 05 9c|9c 05 80 7f) 	tcheck  cr7
+  1c:	(7c 00 05 5d|5d 05 00 7c) 	tend\.   
+  20:	(7c 00 05 5d|5d 05 00 7c) 	tend\.   
+  24:	(7e 00 05 5d|5d 05 00 7e) 	tendall\.
+  28:	(7e 00 05 5d|5d 05 00 7e) 	tendall\.
+  2c:	(7c 18 07 5d|5d 07 18 7c) 	treclaim\. r24
+  30:	(7c 00 07 dd|dd 07 00 7c) 	trechkpt\.
+  34:	(7c 00 05 dd|dd 05 00 7c) 	tsuspend\.
+  38:	(7c 00 05 dd|dd 05 00 7c) 	tsuspend\.
+  3c:	(7c 20 05 dd|dd 05 20 7c) 	tresume\.
+  40:	(7c 20 05 dd|dd 05 20 7c) 	tresume\.
+  44:	(60 42 00 00|00 00 42 60) 	ori     r2,r2,0
+  48:	(60 00 00 00|00 00 00 60) 	nop
+  4c:	(60 42 00 00|00 00 42 60) 	ori     r2,r2,0
Index: gas/testsuite/gas/ppc/power8.s
===================================================================
RCS file: gas/testsuite/gas/ppc/power8.s
diff -N gas/testsuite/gas/ppc/power8.s
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/ppc/power8.s	10 Jan 2013 20:01:25 -0000
@@ -0,0 +1,21 @@
+	.section	".text"
+power8:
+	tabort.      5
+	tabortwc.    7,8,16
+	tabortdc.    20,11,10
+	tabortwci.   17,10,-13
+	tabortdci.   29,3,-5
+	tbegin.
+	tcheck       7
+	tend.        0
+	tend.
+	tend.        1
+	tendall.     
+	treclaim.    24
+	trechkpt.    
+	tsr.         0
+	tsuspend.    
+	tsr.         1
+	tresume.     
+	ori	     2,2,0
+	.p2align     4,,15
Index: gas/testsuite/gas/ppc/ppc.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/ppc/ppc.exp,v
retrieving revision 1.32
diff -u -p -r1.32 ppc.exp
--- gas/testsuite/gas/ppc/ppc.exp	17 Dec 2012 16:55:58 -0000	1.32
+++ gas/testsuite/gas/ppc/ppc.exp	10 Jan 2013 20:01:25 -0000
@@ -83,7 +83,9 @@ if { [istarget powerpc*-*-*] } then {
 	run_dump_test "power4_32"
 	run_dump_test "power6"
 	run_dump_test "power7"
+	run_dump_test "power8"
 	run_dump_test "vsx"
+	run_dump_test "htm"
 	run_dump_test "titan"
     }
 }



Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]