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Re: [PATCH ARM]: Architectural Extensions (Matthew Gretton-Dann or Richard Earnshaw)


Hi Richard,

Great, thanks for the info. That will keep me going. I'll look into
.inst, as I was using just a .word to define it for now.

Just as a comment to the whole thing, AFAIK both Cortex-Rn and
Cortex-An have in essence the same architecture, i.e. same instruction
set, same possible extensions, etc. The difference is that while
extensions like virt and sec are standard in Cortex-An, they are
optional in Cortex-Rn.

So I would suggest, that both armv7-r and arm-v7a should have access
to the same extensions, just that armv7-r will have most disabled by
default, while armv7-a would have some enabled by default.

Also, the banked registers instructions are not part of any extension,
and should be present all time. It is a bit weird that you don't have
them unless you enable the virt extension.

Anyway. I guess I can keep going as it is by now, so thanks very much
for your answer.

David.

On Tue, Dec 18, 2012 at 11:47 AM, Richard Earnshaw <rearnsha@arm.com> wrote:
> On 17/12/12 20:19, David Fernandez wrote:
>>
>> DDI04060c.b, A8.8.247, UDF Encoding T1: ARMv4T, ARMv5T*, ARMv6, ARMv7
>> Encoding T2: ARMv6T2, ARMv7
>> udf #imm8
>>
>
> Missed this bit in my previous reply.  UDF is a pseudo instruction that was
> added in rev-C of the ARM ARM, it wasn't listed in earlier versions (I guess
> that's why it wasn't caught when the other updates were done).
>
> The traditional way in gas to get an UNDEF instruction was to hard-code the
> bit-pattern into an opcode.  The correct way to do this is with the .inst,
> .inst.n or .inst.w directives.
>
> HTH,
>
> R.
>


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