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[Patch, AArch64] Fix alignment check on load/store uimm12 offset
- From: Yufeng Zhang <Yufeng dot Zhang at arm dot com>
- To: "binutils at sourceware dot org" <binutils at sourceware dot org>
- Cc: Richard Earnshaw <Richard dot Earnshaw at arm dot com>
- Date: Fri, 12 Oct 2012 14:43:29 +0100
- Subject: [Patch, AArch64] Fix alignment check on load/store uimm12 offset
Hi,
This patch fixes the alignment check on the immediate offset of the
load/store instructions with 12-bit unsigned immediate field. It fixes
the bug where e.g. ldr x0, [x0, #257] was silently assembled as ldr x0,
[x0, #256].
Is it OK to commit?
Thanks,
Yufeng
opcodes/ChangeLog
* aarch64-opc.c (operand_general_constraint_met_p): Change to check
the alignment of addr.offset.imm instead of that of
shifter.amount for
operand type AARCH64_OPND_ADDR_UIMM12.
gas/testsuite/ChangeLog
* gas/aarch64/illegal-2.s: Add test case.
* gas/aarch64/illegal-2.l: Likewise.diff --git a/gas/testsuite/gas/aarch64/illegal-2.l b/gas/testsuite/gas/aarch64/illegal-2.l
index 2ba6894..372596b 100644
--- a/gas/testsuite/gas/aarch64/illegal-2.l
+++ b/gas/testsuite/gas/aarch64/illegal-2.l
@@ -6,3 +6,4 @@
[^:]*:16: Error: .*$
[^:]*:19: Error: .*$
[^:]*:20: Error: .*$
+[^:]*:24: Error: .*$
diff --git a/gas/testsuite/gas/aarch64/illegal-2.s b/gas/testsuite/gas/aarch64/illegal-2.s
index 3aa7283..7711e14 100644
--- a/gas/testsuite/gas/aarch64/illegal-2.s
+++ b/gas/testsuite/gas/aarch64/illegal-2.s
@@ -20,3 +20,5 @@
mov wsp, #0x33030000
.set u16, 0xfff0
+
+ ldr x0, [x0, #257]
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index dc7544f..b5e0984 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -1426,7 +1426,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
0, 4095 * size);
return 0;
}
- if (!value_aligned_p (opnd->shifter.amount, size))
+ if (!value_aligned_p (opnd->addr.offset.imm, size))
{
set_unaligned_error (mismatch_detail, idx, size);
return 0;