This is the mail archive of the
binutils@sourceware.org
mailing list for the binutils project.
[PATCH v2 10/12] opcodes/ * config/tc-microblaze.c: Add support for slr and shr insns
- From: david dot holsgrove at xilinx dot com
- To: binutils at sourceware dot org
- Cc: eager at eagercon dot com, edgar dot iglesias at gmail dot com, joseph at codesourcery dot com, john dot williams at xilinx dot com, vidhumouli dot hunsigida at xilinx dot com, nagaraju dot mekala at xilinx dot com, David Holsgrove <david dot holsgrove at xilinx dot com>
- Date: Thu, 11 Oct 2012 17:17:12 +1000
- Subject: [PATCH v2 10/12] opcodes/ * config/tc-microblaze.c: Add support for slr and shr insns
- References: <cover.1349938301.git.david.holsgrove@xilinx.com>
- References: <cover.1349938301.git.david.holsgrove@xilinx.com>
From: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Add stack high register and stack low register
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
---
gas/ChangeLog | 4 ++++
gas/config/tc-microblaze.c | 20 ++++++++++++++++++++
opcodes/ChangeLog | 5 +++++
opcodes/microblaze-dis.c | 6 ++++++
opcodes/microblaze-opcm.h | 4 ++++
5 files changed, 39 insertions(+), 0 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index b8ac685..29daf78 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,7 @@
+2012-10-10 David Holsgrove <david.holsgrove@xilinx.com>
+
+ * config/tc-microblaze.c: Add support for slr and shr insns
+
2012-10-10 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
* config/tc-microblaze.c: Add support for mbar and sleep insns
diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
index 7d84776..e9c7846 100644
--- a/gas/config/tc-microblaze.c
+++ b/gas/config/tc-microblaze.c
@@ -531,6 +531,17 @@ parse_reg (char * s, unsigned * reg)
}
return s;
}
+ /* Stack protection registers. */
+ else if (strncasecmp (s, "rshr", 4) == 0)
+ {
+ *reg = REG_SHR;
+ return s + 4;
+ }
+ else if (strncasecmp (s, "rslr", 4) == 0)
+ {
+ *reg = REG_SLR;
+ return s + 4;
+ }
else
{
if (TOLOWER (s[0]) == 'r')
@@ -760,6 +771,7 @@ check_spl_reg (unsigned * reg)
|| (*reg == REG_PID) || (*reg == REG_ZPR)
|| (*reg == REG_TLBX) || (*reg == REG_TLBLO)
|| (*reg == REG_TLBHI) || (*reg == REG_TLBSX)
+ || (*reg == REG_SHR) || (*reg == REG_SLR)
|| (*reg >= REG_PVR+MIN_PVR_REGNUM && *reg <= REG_PVR+MAX_PVR_REGNUM))
return TRUE;
@@ -1280,6 +1292,10 @@ md_assemble (char * str)
immed = opcode->immval_mask | REG_TLBLO_MASK;
else if (reg2 == REG_TLBHI)
immed = opcode->immval_mask | REG_TLBHI_MASK;
+ else if (reg2 == REG_SHR)
+ immed = opcode->immval_mask | REG_SHR_MASK;
+ else if (reg2 == REG_SLR)
+ immed = opcode->immval_mask | REG_SLR_MASK;
else if (reg2 >= (REG_PVR+MIN_PVR_REGNUM) && reg2 <= (REG_PVR+MAX_PVR_REGNUM))
immed = opcode->immval_mask | REG_PVR_MASK | reg2;
else
@@ -1331,6 +1347,10 @@ md_assemble (char * str)
immed = opcode->immval_mask | REG_TLBHI_MASK;
else if (reg1 == REG_TLBSX)
immed = opcode->immval_mask | REG_TLBSX_MASK;
+ else if (reg1 == REG_SHR)
+ immed = opcode->immval_mask | REG_SHR_MASK;
+ else if (reg1 == REG_SLR)
+ immed = opcode->immval_mask | REG_SLR_MASK;
else
as_fatal (_("invalid value for special purpose register"));
inst |= (reg2 << RA_LOW) & RA_MASK;
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 5753664..7907a2d 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2012-10-10 David Holsgrove <david.holsgrove@xilinx.com>
+
+ * microblaze-opcm.h: Add support for slr and shr insns
+ * microblaze-dis.c: Likewise
+
2012-10-10 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
* microblaze-opc.h: Add support for mbar and sleep insns
diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
index 9025da9..bf028c4 100644
--- a/opcodes/microblaze-dis.c
+++ b/opcodes/microblaze-dis.c
@@ -139,6 +139,12 @@ get_field_special (long instr, struct op_code_struct * op)
case REG_TLBSX_MASK :
strcpy (spr, "tlbsx");
break;
+ case REG_SHR_MASK :
+ strcpy (spr, "shr");
+ break;
+ case REG_SLR_MASK :
+ strcpy (spr, "slr");
+ break;
default :
if (((((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask) & 0xE000)
== REG_PVR_MASK)
diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
index 7b8d20b..1f5d85a 100644
--- a/opcodes/microblaze-opcm.h
+++ b/opcodes/microblaze-opcm.h
@@ -78,6 +78,8 @@ enum microblaze_instr_type
#define REG_BTR_MASK 0x800b
#define REG_EDR_MASK 0x800d
#define REG_PVR_MASK 0xa000
+#define REG_SLR_MASK 0x8800
+#define REG_SHR_MASK 0x8802
#define REG_PID_MASK 0x9000
#define REG_ZPR_MASK 0x9001
@@ -99,6 +101,8 @@ enum microblaze_instr_type
#define REG_FSR 39 /* FPU Status reg. */
#define REG_BTR 43 /* Branch Target reg. */
#define REG_EDR 45 /* Exception reg. */
+#define REG_SHR 50 /* Stack High reg. */
+#define REG_SLR 51 /* Stack Low reg. */
#define REG_PVR 40960 /* Program Verification reg. */
#define REG_PID 36864 /* MMU: Process ID reg. */
--
1.7.0.4