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[PATCH 11/12] opcodes/ * microblaze-opc.h: Add support for swapb and swaph insns
From: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
Add swap byte (swapb) and swap halfwords (swaph) instructions.
Signed-off-by: Nagaraju Mekala <nagaraju.mekala@xilinx.com>
Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
---
opcodes/ChangeLog | 5 +++++
opcodes/microblaze-opc.h | 2 ++
opcodes/microblaze-opcm.h | 2 +-
3 files changed, 8 insertions(+), 1 deletions(-)
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 7907a2d..7c4c810 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2012-10-10 Nagaraju Mekala <nagaraju.mekala@xilinx.com>
+
+ * microblaze-opc.h: Add support for swapb and swaph insns
+ * microblaze-opcm.h: Likewise
+
2012-10-10 David Holsgrove <david.holsgrove@xilinx.com>
* microblaze-opcm.h: Add support for slr and shr insns
diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
index 78e5fa5..0d44074 100644
--- a/opcodes/microblaze-opc.h
+++ b/opcodes/microblaze-opc.h
@@ -269,6 +269,8 @@ struct op_code_struct
{"fcmp.ge", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000260, OPCODE_MASK_H4, fcmp_ge, arithmetic_inst },
{"fcmp.un", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000200, OPCODE_MASK_H4, fcmp_un, arithmetic_inst },
{"flt", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000280, OPCODE_MASK_H4, flt, arithmetic_inst },
+ {"swapb", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E0, OPCODE_MASK_H4, swapb, arithmetic_inst },
+ {"swaph", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4, swaph, arithmetic_inst },
{"fint", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000300, OPCODE_MASK_H4, fint, arithmetic_inst },
{"fsqrt", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000380, OPCODE_MASK_H4, fsqrt, arithmetic_inst },
{"tget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001000, OPCODE_MASK_H32, tget, anyware_inst },
diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
index 1f5d85a..71de752 100644
--- a/opcodes/microblaze-opcm.h
+++ b/opcodes/microblaze-opcm.h
@@ -27,7 +27,7 @@ enum microblaze_instr
{
add, rsub, addc, rsubc, addk, rsubk, addkc, rsubkc, clz, cmp, cmpu,
addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
- mulh, mulhu, mulhsu,
+ mulh, mulhu, mulhsu,swapb,swaph,
idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
ncget, ncput, muli, bslli, bsrai, bsrli, mului, or, and, xor,
andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
--
1.7.0.4