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[PATCH 03/12] gas/ * config/tc-microblaze.c: INST_TYPE_RD_R1_SPECIAL -> INST_TYPE_R1_R2_SPECIAL
From: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Change write to data cache and write to instruction cache insns to be
of type INST_TYPE_R1_R2_SPECIAL
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
---
gas/ChangeLog | 4 ++++
gas/config/tc-microblaze.c | 7 +++----
opcodes/ChangeLog | 5 +++++
opcodes/microblaze-dis.c | 4 ++--
opcodes/microblaze-opc.h | 10 +++++-----
5 files changed, 19 insertions(+), 11 deletions(-)
diff --git a/gas/ChangeLog b/gas/ChangeLog
index ff75419..eeea5c9 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,7 @@
+2012-10-10 Edgar E. Iglesias <edgar.iglesias@gmail.com>
+
+ * config/tc-microblaze.c: INST_TYPE_RD_R1_SPECIAL -> INST_TYPE_R1_R2_SPECIAL
+
2012-10-10 David Holsgrove <david.holsgrove@xilinx.com>
* config/tc-microblaze.c: Remove special register condition check
diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
index de0efda..4f5fa1d 100644
--- a/gas/config/tc-microblaze.c
+++ b/gas/config/tc-microblaze.c
@@ -1335,16 +1335,16 @@ md_assemble (char * str)
output = frag_more (isize);
break;
- case INST_TYPE_RD_R1_SPECIAL:
+ case INST_TYPE_R1_R2_SPECIAL:
if (strcmp (op_end, ""))
- op_end = parse_reg (op_end + 1, ®1); /* Get rd. */
+ op_end = parse_reg (op_end + 1, ®1); /* Get r1. */
else
{
as_fatal (_("Error in statement syntax"));
reg1 = 0;
}
if (strcmp (op_end, ""))
- op_end = parse_reg (op_end + 1, ®2); /* Get r1. */
+ op_end = parse_reg (op_end + 1, ®2); /* Get r2. */
else
{
as_fatal (_("Error in statement syntax"));
@@ -1358,7 +1358,6 @@ md_assemble (char * str)
as_fatal (_("Cannot use special register with this instruction"));
/* insn wic ra, rb => wic ra, ra, rb. */
- inst |= (reg1 << RD_LOW) & RD_MASK;
inst |= (reg1 << RA_LOW) & RA_MASK;
inst |= (reg2 << RB_LOW) & RB_MASK;
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 96c98bf..9025f9e 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2012-10-10 Edgar E. Iglesias <edgar.iglesias@gmail.com>
+
+ * opcodes/microblaze-dis.c: INST_TYPE_RD_R1_SPECIAL -> INST_TYPE_R1_R2_SPECIAL
+ * opcodes/microblaze-opc.h: Likewise
+
2012-09-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* arm-dis.c: Changed ldra and strl-form mnemonics
diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
index bdbf831..4874cc9 100644
--- a/opcodes/microblaze-dis.c
+++ b/opcodes/microblaze-dis.c
@@ -368,8 +368,8 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
case INST_TYPE_R1:
print_func (stream, "\t%s", get_field_r1 (inst));
break;
- case INST_TYPE_RD_R1_SPECIAL:
- print_func (stream, "\t%s, %s", get_field_rd (inst), get_field_r2 (inst));
+ case INST_TYPE_R1_R2_SPECIAL:
+ print_func (stream, "\t%s, %s", get_field_r1 (inst), get_field_r2 (inst));
break;
case INST_TYPE_RD_IMM15:
print_func (stream, "\t%s, %s", get_field_rd (inst), get_field_imm15 (inst));
diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
index 02ac83f..0d23499 100644
--- a/opcodes/microblaze-opc.h
+++ b/opcodes/microblaze-opc.h
@@ -45,7 +45,7 @@
#define INST_TYPE_R1_RFSL 15
/* New insn type for insn cache. */
-#define INST_TYPE_RD_R1_SPECIAL 16
+#define INST_TYPE_R1_R2_SPECIAL 16
/* New insn type for msrclr, msrset insns. */
#define INST_TYPE_RD_IMM15 17
@@ -166,10 +166,10 @@ struct op_code_struct
{"srl", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000041, OPCODE_MASK_H34, srl, logical_inst },
{"sext8", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000060, OPCODE_MASK_H34, sext8, logical_inst },
{"sext16",INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000061, OPCODE_MASK_H34, sext16, logical_inst },
- {"wic", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst },
- {"wdc", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst },
- {"wdc.clear", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst },
- {"wdc.flush", INST_TYPE_RD_R1_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
+ {"wic", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst },
+ {"wdc", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst },
+ {"wdc.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst },
+ {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
{"mts", INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
{"mfs", INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
{"br", INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
--
1.7.0.4