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Re: [PATCH, v3]: AMD btver1 and btver2 enablement
- From: "H.J. Lu" <hjl dot tools at gmail dot com>
- To: "Eggone, NagaJyothi" <NagaJyothi dot Eggone at amd dot com>
- Cc: "binutils at sourceware dot org" <binutils at sourceware dot org>
- Date: Fri, 17 Aug 2012 06:10:30 -0700
- Subject: Re: [PATCH, v3]: AMD btver1 and btver2 enablement
- References: <80417A078608EC4BBFDAFAE7DF706EC50178E8@sausexdag03.amd.com>
On Thu, Aug 16, 2012 at 11:28 PM, Eggone, NagaJyothi
> Hello H.J.,
>> -----Original Message-----
>> From: H.J. Lu [mailto:firstname.lastname@example.org]
>> Sent: Thursday, August 16, 2012 11:31 PM
>> To: Eggone, NagaJyothi
>> Cc: email@example.com
>> Subject: Re: [PATCH, v2]: AMD btver1 and btver2 enablement
>> >> Do you really need Cpu3dnowPrfch? Where will it be used?
>> > The 3dnow 'prefetch' and 'prefetchw' instructions are available both
>> on the btver1 and btver2 cores. I could not have enabled both these
>> instructions for these cores without adding a cpu flag bit (this
>> corresponds to the cpuid ECX bit 8 on AMD processors).
>> Please drop Cpu3dnowPrfch and add CpuPRFCHW to
>> gas/testsuite changes should be in gas/testsuite/ChangeLog.
> I have changed the patch as per suggestions above. This patch also includes the diffs of files opcodes/i386-init.h and opcodes/i386-tbl.h.
> Please review and if OK, commit to trunk.
Please reformat your ChangeLog entries to follow
existing ones. You have extra blank lines and
+ /* Supports prefetchw and 3dnow prefetch instructions. */
Please drop 3dnow here.