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Re: [RFA] PowerPC VLE port


Hi Alan,

Well, it's taken a while, but I am now resubmitting the patch for the PPC VLE port. I believe that your comments have all been addressed and the additional testing that you suggested has been successfully completed. Does this now look okay to commit?

Thanks,
Catherine

On 08/13/2011 07:47 AM, Alan Modra wrote:

On Fri, Aug 12, 2011 at 02:05:46PM -0400, Catherine Moore wrote:
Tests for binutils/gas/ld testsuites for the ppc-eabi, power64,
powerpc-aix, powerpc-linux, powerpc-rtems, and powerpc-sysv4
configurations reported no regressions.  If I've missed an important
configuration for testing, please let me know.
I'd like to see you do a 32-bit powerpc-linux gcc bootstrap and
regression test using binutils with your patch applied, and compare
results with the same using baseline binutils.  Comparing all object
files in the trees would also give me a feeling of security.

(DWARF2_LINE_MIN_INSN_LENGTH): Redefine to 2.
Of course, comparing object files won't work with the current patch.
This needs fixing.  I'm not sure, but I think
DWARF2_LINE_MIN_INSN_LENGTH is only used after gas has finished
reading the input file, so you can select 2 if a 2 byte VLE insn has
been used anywhere in the file.

-/* This bit is reserved by BFD for processor specific stuff.  Name
-   it properly so that we can easily stay consistent elsewhere.  */
-#define SEC_PPC_VLE		SEC_TIC54X_BLOCK

Please revert this accidental commit now rather than waiting until the
whole patch is approved.

+/* Processor specific program headers, p_flags field.  */
+#define PF_PPC_VLE		0x10000000	/* PowerPC VLE.  */

Used where?

-      table_op = PPC_OP (opcode->opcode);
-      if (op<  table_op)
+      mask = opcode->mask;
+      table_opcode = opcode->opcode;
+      table_op_is_short = PPC_OP_SE_VLE (mask);
+      table_op = PPC_OP (table_opcode, PPC_OP_SA (mask));
+
+      masked_op = op;
+      if (table_op_is_short)
+        {
+          /* Some short instructions only have 4 or 5 opcode bits.  */
+          if ((mask&  0xfff) == 0)
+            masked_op&= 0x3c;
+          else if ((mask&  0x7ff) == 0)
+            masked_op&= 0x3e;
+        }
+      if (masked_op<  table_op)
  	break;
-      if (op>  table_op)
+      if (masked_op>  table_op)
  	continue;
Hmm.  How much does this patch slow down objdump -d of large powerpc
object files?  If significant, can you do something about it?

+          /* Skip se_bc in favor of simplified mnemonics.  */
+          if (table_opcode == 0xe000&&  !strcmp (opcode->name, "se_bc"))
+            continue;
Sort the opcode table differently instead?

+      /* Skip e_bc or e_bcl in favor of simplified mnemonics.  */
+      else if (table_opcode == 0x7a000000&&  !strcmp (opcode->name, "e_bc"))
+          continue;
+      else if (table_opcode == 0x7a000001&&  !strcmp (opcode->name, "e_bcl"))
+          continue;
Ditto.

-	    (*info->fprintf_func) (info->stream, "%ld", value);
+	    (*info->fprintf_func) (info->stream, "%d", value);
value is a long isn't it?

+  /* A relative 8 bit branch.  */
+  HOWTO (R_PPC_VLE_REL8,	/* type */
+	 1,			/* rightshift */
+	 1,			/* size (0 = byte, 1 = short, 2 = long) */
+	 8,			/* bitsize */
+	 TRUE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_bitfield, /* complain_on_overflow */
complain_overflow_signed? Ditto other relative branches.

+static bfd_reloc_status_type
+ppc_elf_vle_addr16_split16a (bfd *abfd ATTRIBUTE_UNUSED,
Unfinished?  I don't see anything to insert the split field, and the
function is identical to..

+static bfd_reloc_status_type
+ppc_elf_vle_addr16_split16d (bfd *abfd ATTRIBUTE_UNUSED,
..this one.

@@ -3502,6 +3903,9 @@

        switch (r_type)
  	{
+	default:
+	  break;
+
Please don't add default cases to switch statements that previously
lacked them.  I like a warning if some relocation type is missing
in check_relocs.

+.  {*  Indicate that the section has the VLE bit set. *}
+.#define SEC_PPC_VLE 0x80000000
+.
Where is this used?  If needed, I'd rather see one of the sec_flg[0-6]
bits used instead for backend specific flags.


Attachment: bfd.cl
Description: Text document

Index: archures.c
===================================================================
RCS file: /cvs/src/src/bfd/archures.c,v
retrieving revision 1.163
diff -u -p -r1.163 archures.c
--- archures.c	31 Jan 2012 17:54:32 -0000	1.163
+++ archures.c	19 Feb 2012 21:16:18 -0000
@@ -242,6 +242,7 @@ DESCRIPTION
 .#define bfd_mach_ppc_e500mc    5001
 .#define bfd_mach_ppc_e500mc64  5005
 .#define bfd_mach_ppc_titan     83
+.#define bfd_mach_ppc_vle     	84
 .  bfd_arch_rs6000,    {* IBM RS/6000 *}
 .#define bfd_mach_rs6k		6000
 .#define bfd_mach_rs6k_rs1	6001
Index: bfd-in2.h
===================================================================
RCS file: /cvs/src/src/bfd/bfd-in2.h,v
retrieving revision 1.557
diff -u -p -r1.557 bfd-in2.h
--- bfd-in2.h	17 Feb 2012 10:57:33 -0000	1.557
+++ bfd-in2.h	19 Feb 2012 21:16:19 -0000
@@ -1353,6 +1353,9 @@ typedef struct bfd_section
      when memory read flag isn't set. */
 #define SEC_COFF_NOREAD 0x40000000
 
+  /*  Indicate that the section has the VLE bit set. */
+#define SEC_PPC_VLE 0x80000000
+
   /*  End of section flags.  */
 
   /* Some internal packed boolean fields.  */
@@ -1948,6 +1951,7 @@ enum bfd_architecture
 #define bfd_mach_ppc_e500mc    5001
 #define bfd_mach_ppc_e500mc64  5005
 #define bfd_mach_ppc_titan     83
+#define bfd_mach_ppc_vle       84
   bfd_arch_rs6000,    /* IBM RS/6000 */
 #define bfd_mach_rs6k          6000
 #define bfd_mach_rs6k_rs1      6001
@@ -3075,6 +3079,23 @@ relaxation.  */
   BFD_RELOC_PPC_EMB_RELST_HA,
   BFD_RELOC_PPC_EMB_BIT_FLD,
   BFD_RELOC_PPC_EMB_RELSDA,
+  BFD_RELOC_PPC_VLE_REL8,
+  BFD_RELOC_PPC_VLE_REL15,
+  BFD_RELOC_PPC_VLE_REL24,
+  BFD_RELOC_PPC_VLE_LO16A,
+  BFD_RELOC_PPC_VLE_LO16D,
+  BFD_RELOC_PPC_VLE_HI16A,
+  BFD_RELOC_PPC_VLE_HI16D,
+  BFD_RELOC_PPC_VLE_HA16A,
+  BFD_RELOC_PPC_VLE_HA16D,
+  BFD_RELOC_PPC_VLE_SDA21,
+  BFD_RELOC_PPC_VLE_SDA21_LO,
+  BFD_RELOC_PPC_VLE_SDAREL_LO16A,
+  BFD_RELOC_PPC_VLE_SDAREL_LO16D,
+  BFD_RELOC_PPC_VLE_SDAREL_HI16A,
+  BFD_RELOC_PPC_VLE_SDAREL_HI16D,
+  BFD_RELOC_PPC_VLE_SDAREL_HA16A,
+  BFD_RELOC_PPC_VLE_SDAREL_HA16D,
   BFD_RELOC_PPC64_HIGHER,
   BFD_RELOC_PPC64_HIGHER_S,
   BFD_RELOC_PPC64_HIGHEST,
Index: cpu-powerpc.c
===================================================================
RCS file: /cvs/src/src/bfd/cpu-powerpc.c,v
retrieving revision 1.25
diff -u -p -r1.25 cpu-powerpc.c
--- cpu-powerpc.c	31 Jan 2012 17:54:35 -0000	1.25
+++ cpu-powerpc.c	19 Feb 2012 21:16:19 -0000
@@ -373,6 +373,21 @@ const bfd_arch_info_type bfd_powerpc_arc
     powerpc_compatible,
     bfd_default_scan,
     bfd_arch_default_fill,
+    &bfd_powerpc_archs[19]
+  },
+  {
+    16, /* 16 or 32 bits in a word */
+    32, /* 32 bits in an address */
+    8,  /* 8 bits in a byte */
+    bfd_arch_powerpc,
+    bfd_mach_ppc_vle,
+    "powerpc",
+    "powerpc:vle",
+    3,
+    FALSE, /* not the default */
+    powerpc_compatible,
+    bfd_default_scan,
+    bfd_arch_default_fill,
     0
   }
 };
Index: elf32-ppc.c
===================================================================
RCS file: /cvs/src/src/bfd/elf32-ppc.c,v
retrieving revision 1.307
diff -u -p -r1.307 elf32-ppc.c
--- elf32-ppc.c	16 Jan 2012 22:30:19 -0000	1.307
+++ elf32-ppc.c	19 Feb 2012 21:16:19 -0000
@@ -38,13 +38,21 @@
 #include "elf-vxworks.h"
 #include "dwarf2.h"
 
+typedef enum split16_format_type
+{
+  split16a_type = 0,
+  split16d_type
+}
+split16_format_type;
+
 /* RELA relocations are used here.  */
 
 static bfd_reloc_status_type ppc_elf_addr16_ha_reloc
   (bfd *, arelent *, asymbol *, void *, asection *, bfd *, char **);
 static bfd_reloc_status_type ppc_elf_unhandled_reloc
   (bfd *, arelent *, asymbol *, void *, asection *, bfd *, char **);
-
+static void ppc_elf_vle_split16
+  (bfd *, bfd_byte *, bfd_vma, bfd_vma, split16_format_type);
 /* Branch prediction bit for branch taken relocs.  */
 #define BRANCH_PREDICT_BIT 0x200000
 /* Mask to set RA in memory instructions.  */
@@ -1392,6 +1400,262 @@ static reloc_howto_type ppc_elf_howto_ra
 	 0xffff,		/* dst_mask */
 	 FALSE),		/* pcrel_offset */
 
+  /* A relative 8 bit branch.  */
+  HOWTO (R_PPC_VLE_REL8,	/* type */
+	 1,			/* rightshift */
+	 1,			/* size (0 = byte, 1 = short, 2 = long) */
+	 8,			/* bitsize */
+	 TRUE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_signed, /* complain_on_overflow */
+	 bfd_elf_generic_reloc,	/* special_function */
+	 "R_PPC_VLE_REL8",	/* name */
+	 FALSE,			/* partial_inplace */
+	 0,			/* src_mask */
+	 0xff,			/* dst_mask */
+	 TRUE),			/* pcrel_offset */
+	 
+  /* A relative 15 bit branch.  */
+  HOWTO (R_PPC_VLE_REL15,	/* type */
+	 1,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 15,			/* bitsize */
+	 TRUE,			/* pc_relative */
+	 1,			/* bitpos */
+	 complain_overflow_signed, /* complain_on_overflow */
+	 bfd_elf_generic_reloc,	/* special_function */
+	 "R_PPC_VLE_REL15",	/* name */
+	 FALSE,			/* partial_inplace */
+	 0,			/* src_mask */
+	 0xfe,			/* dst_mask */
+	 TRUE),			/* pcrel_offset */
+
+  /* A relative 24 bit branch.  */ 
+  HOWTO (R_PPC_VLE_REL24,	/* type */
+	 1,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 24,			/* bitsize */
+	 TRUE,			/* pc_relative */
+	 1,			/* bitpos */
+	 complain_overflow_signed, /* complain_on_overflow */
+	 bfd_elf_generic_reloc,	/* special_function */
+	 "R_PPC_VLE_REL24",	/* name */
+	 FALSE,			/* partial_inplace */
+	 0,			/* src_mask */
+	 0x1fffffe,		/* dst_mask */
+	 TRUE),			/* pcrel_offset */
+
+  /* The 16 LSBS in split16a format.  */
+  HOWTO (R_PPC_VLE_LO16A,	/* type */
+	 0,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 32,			/* bitsize */
+	 FALSE,			/* pc_relative */  /* FIXME: Does this apply to split relocs? */
+	 0,			/* bitpos */
+	 complain_overflow_bitfield, /* complain_on_overflow */
+	 bfd_elf_generic_reloc,	 /* special_function */
+	 "R_PPC_VLE_LO16A",	/* name */
+	 FALSE,			/* partial_inplace */
+	 0,			/* src_mask */
+	 0x1f00fff,		/* dst_mask */
+	 FALSE),		/* pcrel_offset */
+
+  /* The 16 LSBS in split16d format.  */
+  HOWTO (R_PPC_VLE_LO16D,	/* type */
+	 0,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 32,			/* bitsize */
+	 FALSE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_bitfield, /* complain_on_overflow */
+	 bfd_elf_generic_reloc,	 /* special_function */
+	 "R_PPC_VLE_LO16D",		/* name */
+	 FALSE,			/* partial_inplace */
+	 0,			/* src_mask */
+	 0x1f07ff,		/* dst_mask */
+	 FALSE),		/* pcrel_offset */
+
+  /* Bits 16-31 split16a format.  */
+  HOWTO (R_PPC_VLE_HI16A,	/* type */
+	 0,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 32,			/* bitsize */
+	 FALSE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_bitfield, /* complain_on_overflow */
+	 bfd_elf_generic_reloc,	 /* special_function */
+	 "R_PPC_VLE_HI16A",		/* name */
+	 FALSE,			/* partial_inplace */
+	 0,			/* src_mask */
+	 0x1f00fff,		/* dst_mask */
+	 FALSE),		/* pcrel_offset */
+
+  /* Bits 16-31 split16d format.  */
+  HOWTO (R_PPC_VLE_HI16D,	/* type */
+	 0,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 32,			/* bitsize */
+	 FALSE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_bitfield, /* complain_on_overflow */
+	 bfd_elf_generic_reloc,	 /* special_function */
+	 "R_PPC_VLE_HI16D",		/* name */
+	 FALSE,			/* partial_inplace */
+	 0,			/* src_mask */
+	 0x1f07ff,		/* dst_mask */
+	 FALSE),		/* pcrel_offset */
+
+  /* Bits 16-31 (High Adjusted) in split16a format.  */
+  HOWTO (R_PPC_VLE_HA16A,	/* type */
+	 0,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 32,			/* bitsize */
+	 FALSE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_bitfield, /* complain_on_overflow */
+	 bfd_elf_generic_reloc,	 /* special_function */
+	 "R_PPC_VLE_HA16A",		/* name */
+	 FALSE,			/* partial_inplace */
+	 0,			/* src_mask */
+	 0x1f00fff,		/* dst_mask */
+	 FALSE),		/* pcrel_offset */
+
+  /* Bits 16-31 (High Adjusted) in split16d format.  */
+  HOWTO (R_PPC_VLE_HA16D,	/* type */
+	 0,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 32,			/* bitsize */
+	 FALSE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_bitfield, /* complain_on_overflow */
+	 bfd_elf_generic_reloc,	 /* special_function */
+	 "R_PPC_VLE_HA16D",		/* name */
+	 FALSE,			/* partial_inplace */
+	 0,			/* src_mask */
+	 0x1f07ff,		/* dst_mask */
+	 FALSE),		/* pcrel_offset */
+
+  /* This reloc does nothing.  */
+  HOWTO (R_PPC_VLE_SDA21,		/* type */
+	 0,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 32,			/* bitsize */
+	 FALSE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_bitfield, /* complain_on_overflow */
+	 bfd_elf_generic_reloc,	/* special_function */
+	 "R_PPC_VLE_SDA21",		/* name */
+	 FALSE,			/* partial_inplace */
+	 0,			/* src_mask */
+	 0xffff,		/* dst_mask */
+	 FALSE),		/* pcrel_offset */
+
+  /* This reloc does nothing.  */
+  HOWTO (R_PPC_VLE_SDA21_LO,	/* type */
+	 0,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 32,			/* bitsize */
+	 FALSE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_bitfield, /* complain_on_overflow */
+	 bfd_elf_generic_reloc,	/* special_function */
+	 "R_PPC_VLE_SDA21_LO",	/* name */
+	 FALSE,			/* partial_inplace */
+	 0,			/* src_mask */
+	 0,			/* dst_mask */
+	 FALSE),		/* pcrel_offset */
+
+  /* The 16 LSBS relative to _SDA_BASE_ in split16a format.  */
+  HOWTO (R_PPC_VLE_SDAREL_LO16A,/* type */
+	 0,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 32,			/* bitsize */
+	 FALSE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_bitfield,	/* complain_on_overflow */
+	 bfd_elf_generic_reloc,	 /* special_function */
+	 "R_PPC_VLE_SDAREL_LO16A",	/* name */
+	 FALSE,			/* partial_inplace */
+	 0,			/* src_mask */
+	 0x1f00fff,		/* dst_mask */
+	 FALSE),		/* pcrel_offset */
+
+  /* The 16 LSBS relative to _SDA_BASE_ in split16d format.  */
+  /* This reloc does nothing.  */
+  HOWTO (R_PPC_VLE_SDAREL_LO16D, /* type */
+	 0,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 32,			/* bitsize */
+	 FALSE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_bitfield,	/* complain_on_overflow */
+	 bfd_elf_generic_reloc,	 /* special_function */
+	 "R_PPC_VLE_SDAREL_LO16D",		/* name */
+	 FALSE,			/* partial_inplace */
+	 0,			/* src_mask */
+	 0x1f07ff,		/* dst_mask */
+	 FALSE),		/* pcrel_offset */
+
+  /* Bits 16-31 relative to _SDA_BASE_ in split16a format.  */
+  HOWTO (R_PPC_VLE_SDAREL_HI16A,	/* type */
+	 0,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 32,			/* bitsize */
+	 FALSE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_bitfield,	/* complain_on_overflow */
+	 bfd_elf_generic_reloc,	 /* special_function */
+	 "R_PPC_VLE_SDAREL_HI16A",	/* name */
+	 FALSE,			/* partial_inplace */
+	 0,			/* src_mask */
+	 0x1f00fff,		/* dst_mask */
+	 FALSE),		/* pcrel_offset */
+
+  /* Bits 16-31 relative to _SDA_BASE_ in split16d format.  */
+  HOWTO (R_PPC_VLE_SDAREL_HI16D,	/* type */
+	 0,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 32,			/* bitsize */
+	 FALSE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_bitfield,	/* complain_on_overflow */
+	 bfd_elf_generic_reloc,	 /* special_function */
+	 "R_PPC_VLE_SDAREL_HI16D",	/* name */
+	 FALSE,			/* partial_inplace */
+	 0,			/* src_mask */
+	 0x1f07ff,		/* dst_mask */
+	 FALSE),		/* pcrel_offset */
+
+  /* Bits 16-31 (HA) relative to _SDA_BASE split16a format.  */
+  HOWTO (R_PPC_VLE_SDAREL_HA16A,	/* type */
+	 0,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 32,			/* bitsize */
+	 FALSE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_bitfield,	/* complain_on_overflow */
+	 bfd_elf_generic_reloc,	 /* special_function */
+	 "R_PPC_VLE_SDAREL_HA16A",	/* name */
+	 FALSE,			/* partial_inplace */
+	 0,			/* src_mask */
+	 0x1f00fff,		/* dst_mask */
+	 FALSE),		/* pcrel_offset */
+
+  /* Bits 16-31 (HA) relative to _SDA_BASE split16d format.  */
+  HOWTO (R_PPC_VLE_SDAREL_HA16D,	/* type */
+	 0,			/* rightshift */
+	 2,			/* size (0 = byte, 1 = short, 2 = long) */
+	 32,			/* bitsize */
+	 FALSE,			/* pc_relative */
+	 0,			/* bitpos */
+	 complain_overflow_bitfield,	/* complain_on_overflow */
+	 bfd_elf_generic_reloc,	 /* special_function */
+	 "R_PPC_VLE_SDAREL_HA16D",	/* name */
+	 FALSE,			/* partial_inplace */
+	 0,			/* src_mask */
+	 0x1f07ff,		/* dst_mask */
+	 FALSE),		/* pcrel_offset */
+
   HOWTO (R_PPC_IRELATIVE,	/* type */
 	 0,			/* rightshift */
 	 2,			/* size (0 = byte, 1 = short, 2 = long) */
@@ -1628,6 +1892,36 @@ ppc_elf_reloc_type_lookup (bfd *abfd ATT
     case BFD_RELOC_PPC_EMB_RELST_HA:	r = R_PPC_EMB_RELST_HA;		break;
     case BFD_RELOC_PPC_EMB_BIT_FLD:	r = R_PPC_EMB_BIT_FLD;		break;
     case BFD_RELOC_PPC_EMB_RELSDA:	r = R_PPC_EMB_RELSDA;		break;
+
+    case BFD_RELOC_PPC_VLE_REL8:	r = R_PPC_VLE_REL8;		break;
+    case BFD_RELOC_PPC_VLE_REL15:	r = R_PPC_VLE_REL15;		break;
+    case BFD_RELOC_PPC_VLE_REL24:	r = R_PPC_VLE_REL24;		break;
+    case BFD_RELOC_PPC_VLE_LO16A:	r = R_PPC_VLE_LO16A;		break;
+    case BFD_RELOC_PPC_VLE_LO16D:	r = R_PPC_VLE_LO16D;		break;
+    case BFD_RELOC_PPC_VLE_HI16A:	r = R_PPC_VLE_HI16A;		break;
+    case BFD_RELOC_PPC_VLE_HI16D:	r = R_PPC_VLE_HI16D;		break;
+    case BFD_RELOC_PPC_VLE_HA16A:	r = R_PPC_VLE_HA16A;		break;
+    case BFD_RELOC_PPC_VLE_HA16D:	r = R_PPC_VLE_HA16D;		break;
+    case BFD_RELOC_PPC_VLE_SDA21:	r = R_PPC_VLE_SDA21;		break;
+    case BFD_RELOC_PPC_VLE_SDA21_LO:	r = R_PPC_VLE_SDA21_LO;		break;
+    case BFD_RELOC_PPC_VLE_SDAREL_LO16A:
+      r = R_PPC_VLE_SDAREL_LO16A;
+      break;
+    case BFD_RELOC_PPC_VLE_SDAREL_LO16D:
+      r = R_PPC_VLE_SDAREL_LO16D;
+      break;
+    case BFD_RELOC_PPC_VLE_SDAREL_HI16A:
+      r = R_PPC_VLE_SDAREL_HI16A;
+      break;
+    case BFD_RELOC_PPC_VLE_SDAREL_HI16D:
+      r = R_PPC_VLE_SDAREL_HI16D;
+      break;
+    case BFD_RELOC_PPC_VLE_SDAREL_HA16A:
+      r = R_PPC_VLE_SDAREL_HA16A;
+      break;
+    case BFD_RELOC_PPC_VLE_SDAREL_HA16D:
+      r = R_PPC_VLE_SDAREL_HA16D;
+      break;
     case BFD_RELOC_16_PCREL:		r = R_PPC_REL16;		break;
     case BFD_RELOC_LO16_PCREL:		r = R_PPC_REL16_LO;		break;
     case BFD_RELOC_HI16_PCREL:		r = R_PPC_REL16_HI;		break;
@@ -1952,6 +2246,36 @@ ppc_elf_write_core_note (bfd *abfd, char
     }
 }
 
+static bfd_boolean
+ppc_elf_section_flags (flagword *flags, const Elf_Internal_Shdr *hdr)
+{
+  if (hdr->sh_flags & SHF_PPC_VLE)
+    *flags |= SEC_PPC_VLE;
+  return TRUE;
+}
+
+static flagword
+ppc_elf_lookup_section_flags (char *flag_name) 
+{
+
+  if (!strcmp (flag_name, "SHF_PPC_VLE"))
+    return SEC_PPC_VLE;
+
+  return 0;
+}
+
+/* Add the VLE flag if required.  */
+
+bfd_boolean
+ppc_elf_section_processing (bfd *abfd, Elf_Internal_Shdr *shdr)
+{
+  if (bfd_get_mach (abfd) == bfd_mach_ppc_vle
+      && (shdr->sh_flags & SHF_EXECINSTR) != 0)
+    shdr->sh_flags |= SHF_PPC_VLE;
+
+  return TRUE;
+}
+
 /* Return address for Ith PLT stub in section PLT, for relocation REL
    or (bfd_vma) -1 if it should not be included.  */
 
@@ -2025,6 +2349,69 @@ ppc_elf_additional_program_headers (bfd 
   return ret;
 }
 
+/* Modify the segment map for VLE executables.  */ 
+
+bfd_boolean
+ppc_elf_modify_segment_map (bfd *abfd,
+			    struct bfd_link_info *info ATTRIBUTE_UNUSED)
+{
+  struct elf_segment_map *m, *n;
+  bfd_size_type amt;
+  unsigned int j, k;
+  bfd_vma sect0_vle, sectj_vle;
+
+  /* At this point in the link, output sections have already been sorted by
+     LMA and assigned to segments.  All that is left to do is to ensure
+     there is no mixing of VLE & non-VLE sections in a text segment.
+     If we find that case, we split the segment.
+     We maintain the original output section order.  */
+
+  for (m = elf_tdata (abfd)->segment_map; m != NULL; m = m->next)
+    {
+      if (m->count == 0)
+	continue;
+
+      sect0_vle = m->sections[0]->flags & SEC_PPC_VLE;
+      for (j = 1; j < m->count; ++j)
+	{
+	  if ((m->sections[j]->flags & SEC_PPC_VLE) != sect0_vle)
+	    break;
+        }
+      if (j >= m->count)
+	continue;
+
+      sectj_vle = m->sections[j]->flags & SEC_PPC_VLE;
+
+      /* sections 0..j-1 stay in this (current) segment,
+	 the remainder are put in a new segment.
+	 The scan resumes with the new segment.  */
+
+      /* Fix the new segment.  */
+      amt = sizeof (struct elf_segment_map);
+      amt += (m->count - j - 1) * sizeof (asection *);
+      n = (struct elf_segment_map *) bfd_zalloc (abfd, amt);
+      if (n == NULL)
+        return FALSE;
+
+      n->p_type = PT_LOAD;
+      n->p_flags = PF_X | PF_R;
+      if (sectj_vle)
+        n->p_flags |= PF_PPC_VLE;
+      n->count = m->count - j;
+      for (k = 0; k < n->count; ++k)
+        {
+          n->sections[k] = m->sections[j+k];
+          m->sections[j+k] = NULL;
+	}
+      n->next = m->next;
+      m->next = n;
+
+      /* Fix the current segment  */
+      m->count = j;
+    }
+
+  return TRUE;
+}
 /* Add extra PPC sections -- Note, for now, make .sbss2 and
    .PPC.EMB.sbss0 a normal section, and not a bss section so
    that the linker doesn't crater when trying to make more than
@@ -3620,10 +4007,21 @@ ppc_elf_check_relocs (bfd *abfd,
 	    }
 	  break;
 
+	case R_PPC_VLE_SDAREL_LO16A:
+	case R_PPC_VLE_SDAREL_LO16D:
+	case R_PPC_VLE_SDAREL_HI16A:
+	case R_PPC_VLE_SDAREL_HI16D:
+	case R_PPC_VLE_SDAREL_HA16A:
+	case R_PPC_VLE_SDAREL_HA16D:
 	case R_PPC_SDAREL16:
 	  if (htab->sdata[0].sym == NULL
 	      && !create_sdata_sym (info, &htab->sdata[0]))
 	    return FALSE;
+
+	  if (htab->sdata[1].sym == NULL
+	      && !create_sdata_sym (info, &htab->sdata[1]))
+	    return FALSE;
+
 	  if (h != NULL)
 	    {
 	      ppc_elf_hash_entry (h)->has_sda_refs = TRUE;
@@ -3631,6 +4029,17 @@ ppc_elf_check_relocs (bfd *abfd,
 	    }
 	  break;
 
+	case R_PPC_VLE_REL8:
+	case R_PPC_VLE_REL15:
+	case R_PPC_VLE_REL24:
+	case R_PPC_VLE_LO16A:
+	case R_PPC_VLE_LO16D:
+	case R_PPC_VLE_HI16A:
+	case R_PPC_VLE_HI16D:
+	case R_PPC_VLE_HA16A:
+	case R_PPC_VLE_HA16D:
+	  break;
+
 	case R_PPC_EMB_SDA2REL:
 	  if (info->shared)
 	    {
@@ -3647,6 +4056,8 @@ ppc_elf_check_relocs (bfd *abfd,
 	    }
 	  break;
 
+	case R_PPC_VLE_SDA21_LO:
+	case R_PPC_VLE_SDA21:
 	case R_PPC_EMB_SDA21:
 	case R_PPC_EMB_RELSDA:
 	  if (info->shared)
@@ -4244,7 +4655,24 @@ ppc_elf_merge_private_bfd_data (bfd *ibf
 
   return TRUE;
 }
-
+
+static void
+ppc_elf_vle_split16 (bfd *output_bfd, bfd_byte *contents,
+                 bfd_vma offset, bfd_vma relocation,
+		 split16_format_type split16_format)
+
+{
+  bfd_vma insn, top5, bottom11;
+
+  insn = bfd_get_32 (output_bfd, contents + offset);
+  top5 = relocation >> 11;
+  top5 = top5 << (split16_format == split16a_type ? 20 : 16);
+  bottom11 = relocation & 0x7ff;
+  insn |= top5;
+  insn |= bottom11;
+  bfd_put_32 (output_bfd, insn, contents + offset);
+}
+
 /* Choose which PLT scheme to use, and set .plt flags appropriately.
    Returns -1 on error, 0 for old PLT, 1 for new PLT.  */
 int
@@ -7617,7 +8045,9 @@ ppc_elf_relocate_section (bfd *output_bf
 	case R_PPC_UADDR32:
 	case R_PPC_UADDR16:
 	  goto dodyn;
-
+	case R_PPC_VLE_REL8:
+	case R_PPC_VLE_REL15:
+	case R_PPC_VLE_REL24:
 	case R_PPC_REL24:
 	case R_PPC_REL14:
 	case R_PPC_REL14_BRTAKEN:
@@ -7929,7 +8359,6 @@ ppc_elf_relocate_section (bfd *output_bf
 	  }
 	  break;
 
-	  /* Relocate against _SDA_BASE_.  */
 	case R_PPC_SDAREL16:
 	  {
 	    const char *name;
@@ -7991,9 +8420,53 @@ ppc_elf_relocate_section (bfd *output_bf
 	  }
 	  break;
 
+	case R_PPC_VLE_LO16A:
+	  relocation = (relocation + addend) & 0xffff;
+	  ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
+                               relocation, split16a_type);
+	  continue;
+
+	case R_PPC_VLE_LO16D:
+	  relocation = (relocation + addend) & 0xffff;
+	  ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
+                               relocation, split16d_type);
+	  continue;
+
+	case R_PPC_VLE_HI16A:
+	  relocation = ((relocation + addend) >> 16) & 0xffff;
+	  ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
+                               relocation, split16a_type);
+	  continue;
+
+	case R_PPC_VLE_HI16D:
+	  relocation = ((relocation + addend) >> 16) & 0xffff;
+	  ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
+                               relocation, split16d_type);
+	  continue;
+
+	case R_PPC_VLE_HA16A:
+	  {
+	    bfd_vma value = relocation + addend;
+	    value = (((value >> 16) + ((value & 0x8000) ? 1 : 0)) & 0xffff);
+	    ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
+                                 value, split16a_type);
+	  }
+	  continue;
+
+	case R_PPC_VLE_HA16D:
+	  {
+	    bfd_vma value = relocation + addend;
+	    value = (((value >> 16) + ((value & 0x8000) ? 1 : 0)) & 0xffff);
+	    ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
+                                 value, split16d_type);
+	  }
+	  continue;
+
 	  /* Relocate against either _SDA_BASE_, _SDA2_BASE_, or 0.  */
 	case R_PPC_EMB_SDA21:
+	case R_PPC_VLE_SDA21:
 	case R_PPC_EMB_RELSDA:
+	case R_PPC_VLE_SDA21_LO:
 	  {
 	    const char *name;
 	    int reg;
@@ -8050,10 +8523,28 @@ ppc_elf_relocate_section (bfd *output_bf
 		addend -= SYM_VAL (sda);
 	      }
 
-	    if (r_type == R_PPC_EMB_SDA21)
+	    if (reg == 0
+		&& (r_type == R_PPC_VLE_SDA21
+		    || r_type == R_PPC_VLE_SDA21_LO))
+	      {
+		/* Use the split20 format.  */
+		bfd_vma insn, bits12to15, bits21to31;
+		bfd_vma value  = (relocation + rel->r_offset) & 0xffff;
+		/* Propagate sign bit, if necessary.  */
+		insn = (value & 0x8000) ? 0x70107800 : 0x70000000;
+		bits12to15 = value & 0x700;
+		bits21to31 = value & 0x7ff;
+		insn |= bits12to15;
+		insn |= bits21to31;
+  		bfd_put_32 (output_bfd, insn, contents + rel->r_offset);
+		continue;
+	      }
+	    else if (r_type == R_PPC_EMB_SDA21
+		     || r_type == R_PPC_VLE_SDA21
+		     || r_type == R_PPC_VLE_SDA21_LO)
 	      {
 		bfd_vma insn;  /* Fill in register field.  */
-
+	
 		insn = bfd_get_32 (output_bfd, contents + rel->r_offset);
 		insn = (insn & ~RA_REGISTER_MASK) | (reg << RA_REGISTER_SHIFT);
 		bfd_put_32 (output_bfd, insn, contents + rel->r_offset);
@@ -8061,6 +8552,107 @@ ppc_elf_relocate_section (bfd *output_bf
 	  }
 	  break;
 
+	case R_PPC_VLE_SDAREL_LO16A:
+	case R_PPC_VLE_SDAREL_LO16D:
+	case R_PPC_VLE_SDAREL_HI16A:
+	case R_PPC_VLE_SDAREL_HI16D:
+	case R_PPC_VLE_SDAREL_HA16A:
+	case R_PPC_VLE_SDAREL_HA16D:
+	  {
+	    bfd_vma value;
+	    const char *name;
+	    //int reg;
+	    struct elf_link_hash_entry *sda = NULL;
+
+	    if (sec == NULL || sec->output_section == NULL)
+	      {
+		unresolved_reloc = TRUE;
+		break;
+	      }
+
+	    name = bfd_get_section_name (abfd, sec->output_section);
+	    if (((CONST_STRNEQ (name, ".sdata")
+		  && (name[6] == 0 || name[6] == '.'))
+		 || (CONST_STRNEQ (name, ".sbss")
+		     && (name[5] == 0 || name[5] == '.'))))
+	      {
+		//reg = 13;
+		sda = htab->sdata[0].sym;
+	      }
+	    else if (CONST_STRNEQ (name, ".sdata2")
+		     || CONST_STRNEQ (name, ".sbss2"))
+	      {
+		//reg = 2;
+		sda = htab->sdata[1].sym;
+	      }
+	    else
+	      {
+		(*_bfd_error_handler)
+		  (_("%B: the target (%s) of a %s relocation is "
+		     "in the wrong output section (%s)"),
+		   input_bfd,
+		   sym_name,
+		   howto->name,
+		   name);
+
+		bfd_set_error (bfd_error_bad_value);
+		ret = FALSE;
+		continue;
+	      }
+
+	    if (sda != NULL)
+	      {
+		if (!is_static_defined (sda))
+		  {
+		    unresolved_reloc = TRUE;
+		    break;
+		  }
+	      }
+
+	   value = sda->root.u.def.section->output_section->vma
+   		   + sda->root.u.def.section->output_offset;
+
+	   if (r_type == R_PPC_VLE_SDAREL_LO16A)
+	      {
+		value = (value + addend) & 0xffff;
+	        ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
+                                     value, split16a_type);
+	      }
+	   else if (r_type == R_PPC_VLE_SDAREL_LO16D)
+	      {
+		value = (value + addend) & 0xffff;
+	        ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
+                                     value, split16d_type);
+	      }
+	   else if (r_type == R_PPC_VLE_SDAREL_HI16A)
+	      {
+		value = ((value + addend) >> 16) & 0xffff;
+	        ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
+                                     value, split16a_type);
+	      }
+	   else if (r_type == R_PPC_VLE_SDAREL_HI16D)
+	      {
+		value = ((value + addend) >> 16) & 0xffff;
+	        ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
+                                     value, split16d_type);
+	      }
+	   else if (r_type == R_PPC_VLE_SDAREL_HA16A)
+	      {
+		value += addend;
+		value = (((value >> 16) + ((value & 0x8000) ? 1 : 0)) & 0xffff);
+	        ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
+                                     value, split16a_type);
+	      }
+	   else if (r_type == R_PPC_VLE_SDAREL_HA16D)
+	      {
+		value += addend;
+		value = (((value >> 16) + ((value & 0x8000) ? 1 : 0)) & 0xffff);
+	        ppc_elf_vle_split16 (output_bfd, contents, rel->r_offset,
+                                     value, split16d_type);
+	      }
+	  }
+	  continue;
+
 	  /* Relocate against the beginning of the section.  */
 	case R_PPC_SECTOFF:
 	case R_PPC_SECTOFF_LO:
@@ -9120,6 +9712,7 @@ ppc_elf_finish_dynamic_sections (bfd *ou
 #define elf_backend_finish_dynamic_sections	ppc_elf_finish_dynamic_sections
 #define elf_backend_fake_sections		ppc_elf_fake_sections
 #define elf_backend_additional_program_headers	ppc_elf_additional_program_headers
+#define elf_backend_modify_segment_map     	ppc_elf_modify_segment_map
 #define elf_backend_grok_prstatus		ppc_elf_grok_prstatus
 #define elf_backend_grok_psinfo			ppc_elf_grok_psinfo
 #define elf_backend_write_core_note		ppc_elf_write_core_note
@@ -9132,6 +9725,9 @@ ppc_elf_finish_dynamic_sections (bfd *ou
 #define elf_backend_action_discarded		ppc_elf_action_discarded
 #define elf_backend_init_index_section		_bfd_elf_init_1_index_section
 #define elf_backend_post_process_headers	_bfd_elf_set_osabi
+#define elf_backend_lookup_section_flags_hook	ppc_elf_lookup_section_flags
+#define elf_backend_section_flags		ppc_elf_section_flags
+#define elf_backend_section_processing		ppc_elf_section_processing
 
 #include "elf32-target.h"
 
Index: elf32-ppc.h
===================================================================
RCS file: /cvs/src/src/bfd/elf32-ppc.h,v
retrieving revision 1.12
diff -u -p -r1.12 elf32-ppc.h
--- elf32-ppc.h	21 Sep 2009 11:51:01 -0000	1.12
+++ elf32-ppc.h	19 Feb 2012 21:16:19 -0000
@@ -31,3 +31,6 @@ int ppc_elf_select_plt_layout (bfd *, st
 asection *ppc_elf_tls_setup (bfd *, struct bfd_link_info *, int);
 bfd_boolean ppc_elf_tls_optimize (bfd *, struct bfd_link_info *);
 void ppc_elf_set_sdata_syms (bfd *, struct bfd_link_info *);
+extern bfd_boolean ppc_elf_modify_segment_map (bfd *,
+					       struct bfd_link_info * ATTRIBUTE_UNUSED);
+extern bfd_boolean ppc_elf_section_processing (bfd *, Elf_Internal_Shdr *);
Index: libbfd.h
===================================================================
RCS file: /cvs/src/src/bfd/libbfd.h,v
retrieving revision 1.268
diff -u -p -r1.268 libbfd.h
--- libbfd.h	17 Feb 2012 10:57:33 -0000	1.268
+++ libbfd.h	19 Feb 2012 21:16:19 -0000
@@ -1327,6 +1327,23 @@ static const char *const bfd_reloc_code_
   "BFD_RELOC_PPC_EMB_RELST_HA",
   "BFD_RELOC_PPC_EMB_BIT_FLD",
   "BFD_RELOC_PPC_EMB_RELSDA",
+  "BFD_RELOC_PPC_VLE_REL8",
+  "BFD_RELOC_PPC_VLE_REL15",
+  "BFD_RELOC_PPC_VLE_REL24",
+  "BFD_RELOC_PPC_VLE_LO16A",
+  "BFD_RELOC_PPC_VLE_LO16D",
+  "BFD_RELOC_PPC_VLE_HI16A",
+  "BFD_RELOC_PPC_VLE_HI16D",
+  "BFD_RELOC_PPC_VLE_HA16A",
+  "BFD_RELOC_PPC_VLE_HA16D",
+  "BFD_RELOC_PPC_VLE_SDA21",
+  "BFD_RELOC_PPC_VLE_SDA21_LO",
+  "BFD_RELOC_PPC_VLE_SDAREL_LO16A",
+  "BFD_RELOC_PPC_VLE_SDAREL_LO16D",
+  "BFD_RELOC_PPC_VLE_SDAREL_HI16A",
+  "BFD_RELOC_PPC_VLE_SDAREL_HI16D",
+  "BFD_RELOC_PPC_VLE_SDAREL_HA16A",
+  "BFD_RELOC_PPC_VLE_SDAREL_HA16D",
   "BFD_RELOC_PPC64_HIGHER",
   "BFD_RELOC_PPC64_HIGHER_S",
   "BFD_RELOC_PPC64_HIGHEST",
Index: reloc.c
===================================================================
RCS file: /cvs/src/src/bfd/reloc.c,v
retrieving revision 1.221
diff -u -p -r1.221 reloc.c
--- reloc.c	17 Feb 2012 10:57:33 -0000	1.221
+++ reloc.c	19 Feb 2012 21:16:19 -0000
@@ -2767,6 +2767,40 @@ ENUMX
 ENUMX
   BFD_RELOC_PPC_EMB_RELSDA
 ENUMX
+  BFD_RELOC_PPC_VLE_REL8
+ENUMX
+  BFD_RELOC_PPC_VLE_REL15
+ENUMX
+  BFD_RELOC_PPC_VLE_REL24
+ENUMX
+  BFD_RELOC_PPC_VLE_LO16A
+ENUMX
+  BFD_RELOC_PPC_VLE_LO16D
+ENUMX
+  BFD_RELOC_PPC_VLE_HI16A
+ENUMX
+  BFD_RELOC_PPC_VLE_HI16D
+ENUMX
+  BFD_RELOC_PPC_VLE_HA16A
+ENUMX
+  BFD_RELOC_PPC_VLE_HA16D
+ENUMX
+  BFD_RELOC_PPC_VLE_SDA21
+ENUMX
+  BFD_RELOC_PPC_VLE_SDA21_LO
+ENUMX
+  BFD_RELOC_PPC_VLE_SDAREL_LO16A
+ENUMX
+  BFD_RELOC_PPC_VLE_SDAREL_LO16D
+ENUMX
+  BFD_RELOC_PPC_VLE_SDAREL_HI16A
+ENUMX
+  BFD_RELOC_PPC_VLE_SDAREL_HI16D
+ENUMX
+  BFD_RELOC_PPC_VLE_SDAREL_HA16A
+ENUMX
+  BFD_RELOC_PPC_VLE_SDAREL_HA16D
+ENUMX
   BFD_RELOC_PPC64_HIGHER
 ENUMX
   BFD_RELOC_PPC64_HIGHER_S

Attachment: binutils.cl
Description: Text document

Index: NEWS
===================================================================
RCS file: /cvs/src/src/binutils/NEWS,v
retrieving revision 1.106
diff -p -u -r1.106 NEWS
--- NEWS	2 Nov 2011 03:09:01 -0000	1.106
+++ NEWS	21 Feb 2012 23:56:49 -0000
@@ -2,6 +2,8 @@
 
 * Add support for the Renesas RL78 architecture.
 
+* Add support for the VLE extension to the PowerPC architecture.
+
 Changes in 2.22:
 
 * Add support for displaying the contents of .debug.macro sections.

Attachment: include.cl
Description: Text document

Index: elf/ppc.h
===================================================================
RCS file: /cvs/src/src/include/elf/ppc.h,v
retrieving revision 1.30
diff -p -u -r1.30 ppc.h
--- elf/ppc.h	11 Jul 2011 15:03:08 -0000	1.30
+++ elf/ppc.h	21 Feb 2012 23:58:29 -0000
@@ -131,6 +131,25 @@ START_RELOC_NUMBERS (elf_ppc_reloc_type)
   RELOC_NUMBER (R_PPC_EMB_BIT_FLD,	115)
   RELOC_NUMBER (R_PPC_EMB_RELSDA,	116)
 
+/* PowerPC VLE relocations.  */
+  RELOC_NUMBER (R_PPC_VLE_REL8,		216)
+  RELOC_NUMBER (R_PPC_VLE_REL15,	217)
+  RELOC_NUMBER (R_PPC_VLE_REL24,	218)
+  RELOC_NUMBER (R_PPC_VLE_LO16A,	219)
+  RELOC_NUMBER (R_PPC_VLE_LO16D,	220)
+  RELOC_NUMBER (R_PPC_VLE_HI16A,	221)
+  RELOC_NUMBER (R_PPC_VLE_HI16D,	222)
+  RELOC_NUMBER (R_PPC_VLE_HA16A,	223)
+  RELOC_NUMBER (R_PPC_VLE_HA16D,	224)
+  RELOC_NUMBER (R_PPC_VLE_SDA21,	225)
+  RELOC_NUMBER (R_PPC_VLE_SDA21_LO,	226)
+  RELOC_NUMBER (R_PPC_VLE_SDAREL_LO16A,	227)
+  RELOC_NUMBER (R_PPC_VLE_SDAREL_LO16D,	228)
+  RELOC_NUMBER (R_PPC_VLE_SDAREL_HI16A,	229)
+  RELOC_NUMBER (R_PPC_VLE_SDAREL_HI16D,	230)
+  RELOC_NUMBER (R_PPC_VLE_SDAREL_HA16A,	231)
+  RELOC_NUMBER (R_PPC_VLE_SDAREL_HA16D,	232)
+
 /* Support STT_GNU_IFUNC plt calls.  */
   RELOC_NUMBER (R_PPC_IRELATIVE,	248)
 
@@ -166,9 +185,11 @@ END_RELOC_NUMBERS (R_PPC_max)
 #define	EF_PPC_RELOCATABLE	0x00010000	/* PowerPC -mrelocatable flag.  */
 #define	EF_PPC_RELOCATABLE_LIB	0x00008000	/* PowerPC -mrelocatable-lib flag.  */
 
-/* This bit is reserved by BFD for processor specific stuff.  Name
-   it properly so that we can easily stay consistent elsewhere.  */
-#define SEC_PPC_VLE		SEC_TIC54X_BLOCK
+/* Processor specific program headers, p_flags field.  */
+#define PF_PPC_VLE		0x10000000	/* PowerPC VLE.  */
+
+/* Processor specific section headers, sh_flags field.  */
+#define SHF_PPC_VLE		0x10000000	/* PowerPC VLE text section.  */
 
 /* Processor specific section headers, sh_type field.  */
 
Index: opcode/ppc.h
===================================================================
RCS file: /cvs/src/src/include/opcode/ppc.h,v
retrieving revision 1.42
diff -p -u -r1.42 ppc.h
--- opcode/ppc.h	3 Jul 2010 06:51:53 -0000	1.42
+++ opcode/ppc.h	21 Feb 2012 23:58:29 -0000
@@ -174,8 +174,21 @@ extern const int powerpc_num_opcodes;
 /* Opcode which is supported by the e500 family */
 #define PPC_OPCODE_E500	       0x100000000ull
 
+/* Opcode which is supported by the VLE extension.  */
+#define PPC_OPCODE_VLE	       0x200000000ull
+
+/* A macro to determine the shift amount to be used in PPC_OP.  */
+#define PPC_OP_SA(m) (((m) <= 0xffff) ? 10 : 26)
+
+/* A macro to determine if the instruction is a 2-byte VLE insn.  */
+#define PPC_OP_SE_VLE(m) ((m) <= 0xffff) 
+
 /* A macro to extract the major opcode from an instruction.  */
-#define PPC_OP(i) (((i) >> 26) & 0x3f)
+#define PPC_OP(i, s) (((i) >> s) & 0x3f)
+
+/* Macros for the base opcodes of the VLE insns se_bc, se_blt.  */
+#define PPC_OP_SE_BC		0x38
+#define PPC_OP_SE_BLT		0x39
 
 /* The operands table is an array of struct powerpc_operand.  */
 
@@ -184,16 +197,22 @@ struct powerpc_operand
   /* A bitmask of bits in the operand.  */
   unsigned int bitm;
 
-  /* How far the operand is left shifted in the instruction.
-     -1 to indicate that BITM and SHIFT cannot be used to determine
-     where the operand goes in the insn.  */
+  /* The shift operation to be applied to the operand.  No shift
+     is made if this is zero.  For positive values, the operand
+     is shifted left by SHIFT.  For negative values, the operand
+     is shifted right by -SHIFT.  Use PPC_OPSHIFT_INV to indicate
+     that BITM and SHIFT cannot be used to determine where the
+     operand goes in the insn.  */
   int shift;
 
   /* Insertion function.  This is used by the assembler.  To insert an
      operand value into an instruction, check this field.
 
      If it is NULL, execute
-	 i |= (op & o->bitm) << o->shift;
+	 if (o->shift >= 0)
+	   i |= (op & o->bitm) << o->shift;
+	 else
+	   i |= (op & o->bitm) >> -o->shift;
      (i is the instruction which we are filling in, o is a pointer to
      this structure, and op is the operand value).
 
@@ -211,7 +230,10 @@ struct powerpc_operand
      extract this operand type from an instruction, check this field.
 
      If it is NULL, compute
-	 op = (i >> o->shift) & o->bitm;
+	 if (o->shift >= 0)
+	   op = (i >> o->shift) & o->bitm;
+	 else
+	   op = (i << -o->shift) & o->bitm;
 	 if ((o->flags & PPC_OPERAND_SIGNED) != 0)
 	   sign_extend (op);
      (i is the instruction, o is a pointer to this structure, and op
@@ -235,6 +257,11 @@ struct powerpc_operand
 extern const struct powerpc_operand powerpc_operands[];
 extern const unsigned int num_powerpc_operands;
 
+/* Use with the shift field of a struct powerpc_operand to indicate
+   that BITM and SHIFT cannot be used to determine where the operand
+   goes in the insn.  */
+#define PPC_OPSHIFT_INV (-1 << 31)
+
 /* Values defined for the flags field of a struct powerpc_operand.  */
 
 /* This operand takes signed values.  */
@@ -268,7 +295,7 @@ extern const unsigned int num_powerpc_op
        cr4 4	cr5 5	cr6 6	cr7 7
    These may be combined arithmetically, as in cr2*4+gt.  These are
    only supported on the PowerPC, not the POWER.  */
-#define PPC_OPERAND_CR (0x10)
+#define PPC_OPERAND_CR_BIT (0x10)
 
 /* This operand names a register.  The disassembler uses this to print
    register names with a leading 'r'.  */
@@ -333,6 +360,10 @@ extern const unsigned int num_powerpc_op
 /* This operand names a vector-scalar unit register.  The disassembler
    prints these with a leading 'vs'.  */
 #define PPC_OPERAND_VSR (0x100000)
+
+/* This is a CR FIELD that does not use symbolic names.  */
+#define PPC_OPERAND_CR_REG (0x200000)
+
 
 /* The POWER and PowerPC assemblers use a few macros.  We keep them
    with the operands table for simplicity.  The macro table is an

Attachment: ld.cl
Description: Text document

Index: NEWS
===================================================================
RCS file: /cvs/src/src/ld/NEWS,v
retrieving revision 1.125
diff -u -p -r1.125 NEWS
--- NEWS	2 Nov 2011 16:28:31 -0000	1.125
+++ NEWS	19 Feb 2012 21:49:35 -0000
@@ -1,4 +1,5 @@
 -*- text -*-
+* Add support for the VLE extension to the PowerPC architecture.
 
 * Add option -f FILE on AIX (for response file).
 
Index: testsuite/ld-powerpc/apuinfo.rd
===================================================================
RCS file: /cvs/src/src/ld/testsuite/ld-powerpc/apuinfo.rd,v
retrieving revision 1.4
diff -u -p -r1.4 apuinfo.rd
--- testsuite/ld-powerpc/apuinfo.rd	8 Feb 2010 07:09:39 -0000	1.4
+++ testsuite/ld-powerpc/apuinfo.rd	19 Feb 2012 21:49:35 -0000
@@ -6,6 +6,7 @@
 #target: powerpc-eabi*
 
 Hex dump of section '.PPC.EMB.apuinfo':
-  0x00000000 00000008 0000001c 00000002 41505569 ............APUi
+  0x00000000 00000008 00000020 00000002 41505569 ....... ....APUi
   0x00000010 6e666f00 00420001 00430001 00410001 nfo..B...C...A..
-  0x00000020 01020001 01010001 00400001 01000001 .........@......
+  0x00000020 01020001 01010001 00400001 01040001 .........@......
+  0x00000030 01000001                            ....$
Index: testsuite/ld-powerpc/powerpc.exp
===================================================================
RCS file: /cvs/src/src/ld/testsuite/ld-powerpc/powerpc.exp,v
retrieving revision 1.38
diff -u -p -r1.38 powerpc.exp
--- testsuite/ld-powerpc/powerpc.exp	8 Nov 2011 13:06:03 -0000	1.38
+++ testsuite/ld-powerpc/powerpc.exp	19 Feb 2012 21:49:35 -0000
@@ -215,6 +215,33 @@ set ppc64elftests {
 	{{objdump -s tocopt5.d}} "tocopt5"}
 }
 
+set ppceabitests {
+    {"VLE multiple segments 1" "-T vle-multiseg-1.ld"
+     "-mregnames -mvle" {vle-multiseg.s}
+    {{readelf "-l" vle-multiseg-1.d}} "vle-multiseg-1"}
+    {"VLE multiple segments 2" "-T vle-multiseg-2.ld"
+     "-mregnames -mvle" {vle-multiseg.s}
+    {{readelf "-l" vle-multiseg-2.d}} "vle-multiseg-2"}
+    {"VLE multiple segments 3" "-T vle-multiseg-3.ld"
+     "-mregnames -mvle" {vle-multiseg.s}
+    {{readelf "-l" vle-multiseg-3.d}} "vle-multiseg-3"}
+    {"VLE multiple segments 4" "-T vle-multiseg-4.ld"
+     "-mregnames -mvle" {vle-multiseg.s}
+    {{readelf "-l" vle-multiseg-4.d}} "vle-multiseg-4"}
+    {"VLE multiple segments 5" "-T vle-multiseg-5.ld"
+     "-mregnames -mvle" {vle-multiseg.s}
+    {{readelf "-l" vle-multiseg-5.d}} "vle-multiseg-5"}
+    {"VLE relocations 1" ""
+     "-mvle" {vle-reloc-1.s vle-reloc-def-1.s}
+    {{objdump "-Mvle -d" vle-reloc-1.d}} "vle-reloc-1"}
+    {"VLE relocations 2" ""
+     "-mvle" {vle-reloc-2.s vle-reloc-def-2.s}
+    {{objdump "-Mvle -d" vle-reloc-2.d}} "vle-reloc-2"}
+    {"VLE relocations 3" ""
+     "-mvle" {vle-reloc-3.s vle-reloc-def-3.s}
+    {{objdump "-Mvle -d" vle-reloc-3.d}} "vle-reloc-3"}
+}
+
 
 run_ld_link_tests $ppcelftests
 
@@ -223,6 +250,10 @@ if [ supports_ppc64 ] then {
     run_dump_test "relbrlt"
 }
 
+if { [istarget "powerpc*-eabi*"] } {
+    run_ld_link_tests $ppceabitests
+}
+
 run_dump_test "plt1"
 
 run_dump_test "attr-gnu-4-00"
@@ -251,3 +282,5 @@ run_dump_test "attr-gnu-8-31"
 
 run_dump_test "attr-gnu-12-11"
 run_dump_test "attr-gnu-12-21"
+
+run_dump_test "vle-multiseg-6"
Index: testsuite/ld-powerpc/vle-multiseg-1.d
===================================================================
RCS file: testsuite/ld-powerpc/vle-multiseg-1.d
diff -N testsuite/ld-powerpc/vle-multiseg-1.d
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ testsuite/ld-powerpc/vle-multiseg-1.d	19 Feb 2012 21:49:35 -0000
@@ -0,0 +1,14 @@
+
+Elf file type is EXEC.*
+Entry point 0x0
+There are 2 program headers, starting at offset [0-9]+
+
+Program Headers:
+  Type           Offset   VirtAddr   PhysAddr   FileSiz MemSiz  Flg Align
+  LOAD ( +0x[0-9a-f]+){5} ([RWE ]+){3} 0x[0-f]+
+  LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
+
+ Section to Segment mapping:
+  Segment Sections...
+   00     .data 
+   01     .text_vle .text_iv .iv_handlers 
Index: testsuite/ld-powerpc/vle-multiseg-1.ld
===================================================================
RCS file: testsuite/ld-powerpc/vle-multiseg-1.ld
diff -N testsuite/ld-powerpc/vle-multiseg-1.ld
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ testsuite/ld-powerpc/vle-multiseg-1.ld	19 Feb 2012 21:49:35 -0000
@@ -0,0 +1,17 @@
+SECTIONS
+{
+  .data		0x00000400 :
+  { *(.data) *(.ctors) *(.dtors) *(.eh_frame) *(.jcr) }
+  .text_vle	0x00001000 :
+  {
+	. = ALIGN(16);
+	INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text_vle)
+	INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text)
+	INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init)
+	INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init_vle) 
+	INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini)
+	INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini_vle) 		
+  }
+  .text_iv	. : { . = ALIGN(16); *(.text_iv) }
+  .iv_handlers	0x0001F000 : { *(.iv_handlers) }
+}
Index: testsuite/ld-powerpc/vle-multiseg-2.d
===================================================================
RCS file: testsuite/ld-powerpc/vle-multiseg-2.d
diff -N testsuite/ld-powerpc/vle-multiseg-2.d
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ testsuite/ld-powerpc/vle-multiseg-2.d	19 Feb 2012 21:49:35 -0000
@@ -0,0 +1,16 @@
+
+Elf file type is EXEC.*
+Entry point 0x0
+There are 3 program headers, starting at offset [0-9]+
+
+Program Headers:
+  Type           Offset   VirtAddr   PhysAddr   FileSiz MemSiz  Flg Align
+  LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
+  LOAD ( +0x[0-9a-f]+){5} ([RWE ]+){3} 0x[0-f]+
+  LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
+
+ Section to Segment mapping:
+  Segment Sections...
+   00     .text_vle 
+   01     .data 
+   02     .text_iv .iv_handlers 
Index: testsuite/ld-powerpc/vle-multiseg-2.ld
===================================================================
RCS file: testsuite/ld-powerpc/vle-multiseg-2.ld
diff -N testsuite/ld-powerpc/vle-multiseg-2.ld
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ testsuite/ld-powerpc/vle-multiseg-2.ld	19 Feb 2012 21:49:35 -0000
@@ -0,0 +1,17 @@
+SECTIONS
+{
+  .text_vle	0x00001000 :
+  {
+	. = ALIGN(16);
+	INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text_vle)
+	INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text)
+	INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init)
+	INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init_vle) 
+	INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini)
+	INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini_vle) 		
+  }
+  .data		0x00001400 :
+  { *(.data) *(.ctors) *(.dtors) *(.eh_frame) *(.jcr) }
+  .text_iv	. : { . = ALIGN(16); *(.text_iv) }
+  .iv_handlers	0x0001F000 : { *(.iv_handlers) }
+}
Index: testsuite/ld-powerpc/vle-multiseg-3.d
===================================================================
RCS file: testsuite/ld-powerpc/vle-multiseg-3.d
diff -N testsuite/ld-powerpc/vle-multiseg-3.d
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ testsuite/ld-powerpc/vle-multiseg-3.d	19 Feb 2012 21:49:35 -0000
@@ -0,0 +1,16 @@
+
+Elf file type is EXEC.*
+Entry point 0x0
+There are 3 program headers, starting at offset [0-9]+
+
+Program Headers:
+  Type           Offset   VirtAddr   PhysAddr   FileSiz MemSiz  Flg Align
+  LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
+  LOAD ( +0x[0-9a-f]+){5} ([RWE ]+){3} 0x[0-f]+
+  LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
+
+ Section to Segment mapping:
+  Segment Sections...
+   00     .text_vle .text_iv 
+   01     .data 
+   02     .iv_handlers 
Index: testsuite/ld-powerpc/vle-multiseg-3.ld
===================================================================
RCS file: testsuite/ld-powerpc/vle-multiseg-3.ld
diff -N testsuite/ld-powerpc/vle-multiseg-3.ld
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ testsuite/ld-powerpc/vle-multiseg-3.ld	19 Feb 2012 21:49:35 -0000
@@ -0,0 +1,17 @@
+SECTIONS
+{
+  .text_vle	0x00001000 :
+  {
+	. = ALIGN(16);
+	INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text_vle)
+	INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text)
+	INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init)
+	INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init_vle) 
+	INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini)
+	INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini_vle) 		
+  }
+  .text_iv	. : { . = ALIGN(16); *(.text_iv) }
+  .data		0x00001400 :
+  { *(.data) *(.ctors) *(.dtors) *(.eh_frame) *(.jcr) }
+  .iv_handlers	0x0001F000 : { *(.iv_handlers) }
+}
Index: testsuite/ld-powerpc/vle-multiseg-4.d
===================================================================
RCS file: testsuite/ld-powerpc/vle-multiseg-4.d
diff -N testsuite/ld-powerpc/vle-multiseg-4.d
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ testsuite/ld-powerpc/vle-multiseg-4.d	19 Feb 2012 21:49:35 -0000
@@ -0,0 +1,14 @@
+
+Elf file type is EXEC.*
+Entry point 0x0
+There are 2 program headers, starting at offset [0-9]+
+
+Program Headers:
+  Type           Offset   VirtAddr   PhysAddr   FileSiz MemSiz  Flg Align
+  LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
+  LOAD ( +0x[0-9a-f]+){5} ([RWE ]+){3} 0x[0-f]+
+
+ Section to Segment mapping:
+  Segment Sections...
+   00     .text_vle .text_iv .iv_handlers 
+   01     .data 
Index: testsuite/ld-powerpc/vle-multiseg-4.ld
===================================================================
RCS file: testsuite/ld-powerpc/vle-multiseg-4.ld
diff -N testsuite/ld-powerpc/vle-multiseg-4.ld
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ testsuite/ld-powerpc/vle-multiseg-4.ld	19 Feb 2012 21:49:35 -0000
@@ -0,0 +1,17 @@
+SECTIONS
+{
+  .text_vle	0x00001000 :
+  {
+	. = ALIGN(16);
+	INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text_vle)
+	INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text)
+	INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init)
+	INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init_vle) 
+	INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini)
+	INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini_vle) 		
+  }
+  .text_iv	. : { . = ALIGN(16); *(.text_iv) }
+  .iv_handlers	0x0001F000 : { *(.iv_handlers) }
+  .data		0x00020400 :
+  { *(.data) *(.ctors) *(.dtors) *(.eh_frame) *(.jcr) }
+}
Index: testsuite/ld-powerpc/vle-multiseg-5.d
===================================================================
RCS file: testsuite/ld-powerpc/vle-multiseg-5.d
diff -N testsuite/ld-powerpc/vle-multiseg-5.d
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ testsuite/ld-powerpc/vle-multiseg-5.d	19 Feb 2012 21:49:35 -0000
@@ -0,0 +1,16 @@
+
+Elf file type is EXEC.*
+Entry point 0x0
+There are 3 program headers, starting at offset [0-9]+
+
+Program Headers:
+  Type           Offset   VirtAddr   PhysAddr   FileSiz MemSiz  Flg Align
+  LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
+  LOAD ( +0x[0-9a-f]+){5} ([RWE ]+){3} 0x[0-f]+
+  LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
+
+ Section to Segment mapping:
+  Segment Sections...
+   00     .text_vle .text_iv 
+   01     .data 
+   02     .iv_handlers 
Index: testsuite/ld-powerpc/vle-multiseg-5.ld
===================================================================
RCS file: testsuite/ld-powerpc/vle-multiseg-5.ld
diff -N testsuite/ld-powerpc/vle-multiseg-5.ld
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ testsuite/ld-powerpc/vle-multiseg-5.ld	19 Feb 2012 21:49:35 -0000
@@ -0,0 +1,44 @@
+
+MEMORY
+{
+        code_rom (rxw)	:	org = 0x00001000, len = 0x1EF000
+        irpt_rom (rx)	:	org = 0x001F0000, len = 0x2000
+        int__ram (rxw)	:	org = 0x40000000, len = 256K
+}
+
+REGION_ALIAS("INTR", irpt_rom)
+REGION_ALIAS("CODE", code_rom)
+REGION_ALIAS("RODATA", code_rom)
+REGION_ALIAS("RAM", int__ram)
+
+SECTIONS
+{
+	.iv_handlers :
+	{
+		INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.iv_handlers)
+	} > INTR
+
+	.text_vle :
+	{ 
+		INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text_vle)
+		INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text)
+		INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init)
+		INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init_vle) 
+		INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini)
+		INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini_vle) 		
+	} > CODE
+        
+	.rodata :
+	{
+		*(.rodata)
+	} > RODATA
+        
+	.data   :
+	{
+		*(.data)
+		*(.data.*)
+		*(.ctors)
+		*(.dtors)    
+	}  > RAM AT>RODATA
+
+}
Index: testsuite/ld-powerpc/vle-multiseg-6.d
===================================================================
RCS file: testsuite/ld-powerpc/vle-multiseg-6.d
diff -N testsuite/ld-powerpc/vle-multiseg-6.d
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ testsuite/ld-powerpc/vle-multiseg-6.d	19 Feb 2012 21:49:35 -0000
@@ -0,0 +1,25 @@
+#source: vle-multiseg-6a.s -mregnames -mvle
+#source: vle-multiseg-6b.s
+#source: vle-multiseg-6c.s
+#source: vle-multiseg-6d.s -mregnames -mvle
+#ld: -T vle-multiseg-6.ld
+#target: powerpc*-eabi
+#readelf: -l
+
+Elf file type is EXEC.*
+Entry point 0x[0-9a-f]+
+There are 4 program headers, starting at offset [0-9]+
+
+Program Headers:
+  Type           Offset   VirtAddr   PhysAddr   FileSiz MemSiz  Flg Align
+  LOAD ( +0x[0-9a-f]+){5} ([RWE ]+){3} 0x[0-f]+
+  LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
+  LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
+  LOAD ( +0x[0-9a-f]+){5} R E 0x[0-9a-f]+
+
+ Section to Segment mapping:
+  Segment Sections...
+   00     .data 
+   01     .text_vle 
+   02     .text_iv 
+   03     .text 
Index: testsuite/ld-powerpc/vle-multiseg-6.ld
===================================================================
RCS file: testsuite/ld-powerpc/vle-multiseg-6.ld
diff -N testsuite/ld-powerpc/vle-multiseg-6.ld
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ testsuite/ld-powerpc/vle-multiseg-6.ld	19 Feb 2012 21:49:35 -0000
@@ -0,0 +1,37 @@
+MEMORY
+{
+	vle_seg1 (rxw):     	org = 0x00000000, len = 0x10000
+	vle_seg2 (rxw):     	org = 0x00100000, len = 0x10000
+        nonvle_seg (rxw):	org = 0x001F0000, len = 0x20000
+}
+SECTIONS
+{
+  .data		0x00000100 :
+  {
+	*(.data)
+	*(.ctors)
+	*(.dtors)
+	*(.eh_frame)
+	*(.jcr)
+  }
+  .text_vle	0x00001000 :
+  {
+	. = ALIGN(16);
+	INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text*)
+	INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init*)
+	INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini*)
+  }  > vle_seg1
+
+  .text_iv	0x100000 :
+  {
+	. = ALIGN(16);
+	INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text_iv)
+	INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.iv_handlers)
+  } >vle_seg2
+
+  .text 	. :
+  {
+	. = ALIGN(16);
+	INPUT_SECTION_FLAGS (!SHF_PPC_VLE) *(.text*)
+  }
+}
Index: testsuite/ld-powerpc/vle-multiseg-6a.s
===================================================================
RCS file: testsuite/ld-powerpc/vle-multiseg-6a.s
diff -N testsuite/ld-powerpc/vle-multiseg-6a.s
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ testsuite/ld-powerpc/vle-multiseg-6a.s	19 Feb 2012 21:49:35 -0000
@@ -0,0 +1,47 @@
+	.text
+
+	e_stw    r12, 0x4C(r1)
+	e_stw    r11, 0x48(r1)
+	e_stw    r10, 0x44(r1)
+	e_stw    r9,  0x40(r1)
+	e_stw    r8,  0x3C(r1)
+	e_stw    r7,  0x38(r1)
+	e_stw    r6,  0x34(r1)
+	e_stw    r5,  0x30(r1)
+	e_stw    r4,  0x2c(r1)
+
+        .globl   IV_table
+	.section ".iv_handlers", "ax"
+IV_table:
+	e_b dummy
+	.align 4
+	e_b dummy
+	.align 4
+	e_b dummy
+	.align 4
+	e_b dummy
+	.align 4
+	e_b dummy
+	.align 4
+	e_b dummy
+	.align 4
+	e_b dummy
+	.align 4
+	e_b dummy
+	.align 4
+dummy:
+	se_nop
+	e_b dummy
+
+	.section ".text_iv", "ax"
+	e_lis r3, IV_table@h
+	mtivpr r3
+	e_li r3, IV_table@l+0x00
+	mtivor0 r3
+	e_li r3, IV_table@l+0x10
+	mtivor1 r3
+	e_li r3, IV_table@l+0x20
+	mtivor2 r3
+
+	.data
+	.long 0xdeadbeef
Index: testsuite/ld-powerpc/vle-multiseg-6b.s
===================================================================
RCS file: testsuite/ld-powerpc/vle-multiseg-6b.s
diff -N testsuite/ld-powerpc/vle-multiseg-6b.s
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ testsuite/ld-powerpc/vle-multiseg-6b.s	19 Feb 2012 21:49:35 -0000
@@ -0,0 +1,6 @@
+	.text
+
+        and.    3,4,5
+        and     3,4,5
+        andc    13,14,15
+        andc.   16,17,18
Index: testsuite/ld-powerpc/vle-multiseg-6c.s
===================================================================
RCS file: testsuite/ld-powerpc/vle-multiseg-6c.s
diff -N testsuite/ld-powerpc/vle-multiseg-6c.s
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ testsuite/ld-powerpc/vle-multiseg-6c.s	19 Feb 2012 21:49:35 -0000
@@ -0,0 +1,6 @@
+	.text
+
+        and.    3,4,5
+        and     3,4,5
+        andc    13,14,15
+        andc.   16,17,18
Index: testsuite/ld-powerpc/vle-multiseg-6d.s
===================================================================
RCS file: testsuite/ld-powerpc/vle-multiseg-6d.s
diff -N testsuite/ld-powerpc/vle-multiseg-6d.s
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ testsuite/ld-powerpc/vle-multiseg-6d.s	19 Feb 2012 21:49:35 -0000
@@ -0,0 +1,9 @@
+	.section ".text_iv", "ax"
+	e_lis r3, IV_table@h
+	mtivpr r3
+	e_li r3, IV_table@l+0x00
+	mtivor0 r3
+	e_li r3, IV_table@l+0x10
+	mtivor1 r3
+	e_li r3, IV_table@l+0x20
+	mtivor2 r3
Index: testsuite/ld-powerpc/vle-multiseg.s
===================================================================
RCS file: testsuite/ld-powerpc/vle-multiseg.s
diff -N testsuite/ld-powerpc/vle-multiseg.s
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ testsuite/ld-powerpc/vle-multiseg.s	19 Feb 2012 21:49:35 -0000
@@ -0,0 +1,50 @@
+# Make up several VLE text sections which the linker script will put into
+# separate output sections.  We will then check for separate load segments.
+#	.include "mpc5500_usrdefs.inc"
+#	.section ".text_vle"
+
+	e_stw    r12, 0x4C(r1)
+	e_stw    r11, 0x48(r1)
+	e_stw    r10, 0x44(r1)
+	e_stw    r9,  0x40(r1)
+	e_stw    r8,  0x3C(r1)
+	e_stw    r7,  0x38(r1)
+	e_stw    r6,  0x34(r1)
+	e_stw    r5,  0x30(r1)
+	e_stw    r4,  0x2c(r1)
+
+        .globl   IV_table
+	.section ".iv_handlers", "ax"
+IV_table:
+	e_b dummy
+	.align 4
+	e_b dummy
+	.align 4
+	e_b dummy
+	.align 4
+	e_b dummy
+	.align 4
+	e_b dummy
+	.align 4
+	e_b dummy
+	.align 4
+	e_b dummy
+	.align 4
+	e_b dummy
+	.align 4
+dummy:
+	se_nop
+	e_b dummy
+
+	.section ".text_iv", "ax"
+	e_lis r3, IV_table@h
+	mtivpr r3
+	e_li r3, IV_table@l+0x00
+	mtivor0 r3
+	e_li r3, IV_table@l+0x10
+	mtivor1 r3
+	e_li r3, IV_table@l+0x20
+	mtivor2 r3
+
+	.data
+	.long 0xdeadbeef
Index: testsuite/ld-powerpc/vle-reloc-1.d
===================================================================
RCS file: testsuite/ld-powerpc/vle-reloc-1.d
diff -N testsuite/ld-powerpc/vle-reloc-1.d
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ testsuite/ld-powerpc/vle-reloc-1.d	19 Feb 2012 21:49:35 -0000
@@ -0,0 +1,29 @@
+.*:     file format .*
+
+
+Disassembly of section .text:
+
+01800054 <sub1>:
+ 1800054:	00 04       	se_blr
+
+01800056 <sub2>:
+ 1800056:	00 04       	se_blr
+
+01800058 <vle_reloc>:
+ 1800058:	e8 fe       	se_b    1800054 <sub1>
+ 180005a:	e9 fd       	se_bl   1800054 <sub1>
+ 180005c:	e1 fd       	se_ble  1800056 <sub2>
+ 180005e:	e6 fc       	se_beq  1800056 <sub2>
+ 1800060:	78 00 00 10 	e_b     1800070 <sub3>
+ 1800064:	78 00 00 0f 	e_bl    1800072 <sub4>
+ 1800068:	7a 05 00 0c 	e_ble   cr1,1800074 <sub5>
+ 180006c:	7a 1a 00 09 	e_beql  cr2,1800074 <sub5>
+
+01800070 <sub3>:
+ 1800070:	00 04       	se_blr
+
+01800072 <sub4>:
+ 1800072:	00 04       	se_blr
+
+01800074 <sub5>:
+ 1800074:	00 04       	se_blr
Index: testsuite/ld-powerpc/vle-reloc-1.s
===================================================================
RCS file: testsuite/ld-powerpc/vle-reloc-1.s
diff -N testsuite/ld-powerpc/vle-reloc-1.s
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ testsuite/ld-powerpc/vle-reloc-1.s	19 Feb 2012 21:49:35 -0000
@@ -0,0 +1,18 @@
+        .section .text
+sub1:
+        se_blr
+
+sub2:
+        se_blr
+
+	.section .text
+vle_reloc:
+	se_b	sub1
+	se_bl	sub1
+	se_bc	0,1,sub2
+	se_bc	1,2,sub2
+
+	e_b	sub3
+	e_bl	sub4
+	e_bc	0,5,sub5
+	e_bcl	1,10,sub5
Index: testsuite/ld-powerpc/vle-reloc-2.d
===================================================================
RCS file: testsuite/ld-powerpc/vle-reloc-2.d
diff -N testsuite/ld-powerpc/vle-reloc-2.d
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ testsuite/ld-powerpc/vle-reloc-2.d	19 Feb 2012 21:49:35 -0000
@@ -0,0 +1,87 @@
+.*:     file format .*
+
+Disassembly of section .text:
+
+01800094 <sub1>:
+ 1800094:	00 04       	se_blr
+01800096 <sub2>:
+ 1800096:	00 04       	se_blr
+01800098 <vle_reloc_2>:
+ 1800098:	70 20 c1 c2 	e_or2i  r1,450
+ 180009c:	70 40 c1 81 	e_or2i  r2,385
+ 18000a0:	70 60 c1 81 	e_or2i  r3,385
+ 18000a4:	70 80 c1 ce 	e_or2i  r4,462
+ 18000a8:	70 a0 c1 80 	e_or2i  r5,384
+ 18000ac:	70 40 c1 81 	e_or2i  r2,385
+ 18000b0:	70 20 c9 c2 	e_and2i. r1,450
+ 18000b4:	70 40 c9 81 	e_and2i. r2,385
+ 18000b8:	70 60 c9 81 	e_and2i. r3,385
+ 18000bc:	70 80 c9 ce 	e_and2i. r4,462
+ 18000c0:	70 a0 c9 80 	e_and2i. r5,384
+ 18000c4:	70 40 c9 81 	e_and2i. r2,385
+ 18000c8:	70 20 d1 c2 	e_or2is r1,450
+ 18000cc:	70 40 d1 81 	e_or2is r2,385
+ 18000d0:	70 60 d1 81 	e_or2is r3,385
+ 18000d4:	70 80 d1 ce 	e_or2is r4,462
+ 18000d8:	70 a0 d1 80 	e_or2is r5,384
+ 18000dc:	70 40 d1 81 	e_or2is r2,385
+ 18000e0:	70 20 e1 c2 	e_lis   r1,450
+ 18000e4:	70 40 e1 81 	e_lis   r2,385
+ 18000e8:	70 60 e1 81 	e_lis   r3,385
+ 18000ec:	70 80 e1 ce 	e_lis   r4,462
+ 18000f0:	70 a0 e1 80 	e_lis   r5,384
+ 18000f4:	70 40 e1 81 	e_lis   r2,385
+ 18000f8:	70 20 e9 c2 	e_and2is. r1,450
+ 18000fc:	70 40 e9 81 	e_and2is. r2,385
+ 1800100:	70 60 e9 81 	e_and2is. r3,385
+ 1800104:	70 80 e9 ce 	e_and2is. r4,462
+ 1800108:	70 a0 e9 80 	e_and2is. r5,384
+ 180010c:	70 40 e9 81 	e_and2is. r2,385
+ 1800110:	70 01 99 c2 	e_cmp16i r1,450
+ 1800114:	70 02 99 81 	e_cmp16i r2,385
+ 1800118:	70 03 99 81 	e_cmp16i r3,385
+ 180011c:	70 04 99 ce 	e_cmp16i r4,462
+ 1800120:	70 05 99 80 	e_cmp16i r5,384
+ 1800124:	70 02 99 81 	e_cmp16i r2,385
+ 1800128:	70 01 a9 c2 	e_cmpl16i r1,450
+ 180012c:	70 02 a9 81 	e_cmpl16i r2,385
+ 1800130:	70 03 a9 81 	e_cmpl16i r3,385
+ 1800134:	70 04 a9 ce 	e_cmpl16i r4,462
+ 1800138:	70 05 a9 80 	e_cmpl16i r5,384
+ 180013c:	70 02 a9 81 	e_cmpl16i r2,385
+ 1800140:	70 01 b1 c2 	e_cmph16i r1,450
+ 1800144:	70 02 b1 81 	e_cmph16i r2,385
+ 1800148:	70 03 b1 81 	e_cmph16i r3,385
+ 180014c:	70 04 b1 ce 	e_cmph16i r4,462
+ 1800150:	70 05 b1 80 	e_cmph16i r5,384
+ 1800154:	70 02 b1 81 	e_cmph16i r2,385
+ 1800158:	70 01 b9 c2 	e_cmphl16i r1,450
+ 180015c:	70 02 b9 81 	e_cmphl16i r2,385
+ 1800160:	70 03 b9 81 	e_cmphl16i r3,385
+ 1800164:	70 04 b9 ce 	e_cmphl16i r4,462
+ 1800168:	70 05 b9 80 	e_cmphl16i r5,384
+ 180016c:	70 02 b9 81 	e_cmphl16i r2,385
+ 1800170:	70 01 89 c2 	e_add2i. r1,450
+ 1800174:	70 02 89 81 	e_add2i. r2,385
+ 1800178:	70 03 89 81 	e_add2i. r3,385
+ 180017c:	70 04 89 ce 	e_add2i. r4,462
+ 1800180:	70 05 89 80 	e_add2i. r5,384
+ 1800184:	70 02 89 81 	e_add2i. r2,385
+ 1800188:	70 01 91 c2 	e_add2is r1,450
+ 180018c:	70 02 91 81 	e_add2is r2,385
+ 1800190:	70 03 91 81 	e_add2is r3,385
+ 1800194:	70 04 91 ce 	e_add2is r4,462
+ 1800198:	70 05 91 80 	e_add2is r5,384
+ 180019c:	70 02 91 81 	e_add2is r2,385
+ 18001a0:	70 01 a1 c2 	e_mull2i r1,450
+ 18001a4:	70 02 a1 81 	e_mull2i r2,385
+ 18001a8:	70 03 a1 81 	e_mull2i r3,385
+ 18001ac:	70 04 a1 ce 	e_mull2i r4,462
+ 18001b0:	70 05 a1 80 	e_mull2i r5,384
+ 18001b4:	70 02 a1 81 	e_mull2i r2,385
+018001b8 <sub3>:
+ 18001b8:	00 04       	se_blr
+018001ba <sub4>:
+ 18001ba:	00 04       	se_blr
+018001bc <sub5>:
+ 18001bc:	00 04       	se_blr
Index: testsuite/ld-powerpc/vle-reloc-2.s
===================================================================
RCS file: testsuite/ld-powerpc/vle-reloc-2.s
diff -N testsuite/ld-powerpc/vle-reloc-2.s
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ testsuite/ld-powerpc/vle-reloc-2.s	19 Feb 2012 21:49:35 -0000
@@ -0,0 +1,92 @@
+        .section .text
+sub1:
+        se_blr
+
+sub2:
+        se_blr
+
+	.section .text
+vle_reloc_2:
+	e_or2i 1, low@l
+	e_or2i 2, high@h
+	e_or2i 3, high_adjust@ha
+	e_or2i 4, low_sdarel@sdarel@l
+	e_or2i 5, high_sdarel@sdarel@h
+	e_or2i 2, high_adjust_sdarel@sdarel@ha
+
+	e_and2i. 1, low@l
+	e_and2i. 2, high@h
+	e_and2i. 3, high_adjust@ha
+	e_and2i. 4, low_sdarel@sdarel@l
+	e_and2i. 5, high_sdarel@sdarel@h
+	e_and2i. 2, high_adjust_sdarel@sdarel@ha
+
+	e_or2is 1, low@l
+	e_or2is 2, high@h
+	e_or2is 3, high_adjust@ha
+	e_or2is 4, low_sdarel@sdarel@l
+	e_or2is 5, high_sdarel@sdarel@h
+	e_or2is 2, high_adjust_sdarel@sdarel@ha
+
+	e_lis 1, low@l
+	e_lis 2, high@h
+	e_lis 3, high_adjust@ha
+	e_lis 4, low_sdarel@sdarel@l
+	e_lis 5, high_sdarel@sdarel@h
+	e_lis 2, high_adjust_sdarel@sdarel@ha
+
+	e_and2is. 1, low@l
+	e_and2is. 2, high@h
+	e_and2is. 3, high_adjust@ha
+	e_and2is. 4, low_sdarel@sdarel@l
+	e_and2is. 5, high_sdarel@sdarel@h
+	e_and2is. 2, high_adjust_sdarel@sdarel@ha
+
+	e_cmp16i 1, low@l
+	e_cmp16i 2, high@h
+	e_cmp16i 3, high_adjust@ha
+	e_cmp16i 4, low_sdarel@sdarel@l
+	e_cmp16i 5, high_sdarel@sdarel@h
+	e_cmp16i 2, high_adjust_sdarel@sdarel@ha
+
+	e_cmpl16i 1, low@l
+	e_cmpl16i 2, high@h
+	e_cmpl16i 3, high_adjust@ha
+	e_cmpl16i 4, low_sdarel@sdarel@l
+	e_cmpl16i 5, high_sdarel@sdarel@h
+	e_cmpl16i 2, high_adjust_sdarel@sdarel@ha
+
+	e_cmph16i 1, low@l
+	e_cmph16i 2, high@h
+	e_cmph16i 3, high_adjust@ha
+	e_cmph16i 4, low_sdarel@sdarel@l
+	e_cmph16i 5, high_sdarel@sdarel@h
+	e_cmph16i 2, high_adjust_sdarel@sdarel@ha
+
+	e_cmphl16i 1, low@l
+	e_cmphl16i 2, high@h
+	e_cmphl16i 3, high_adjust@ha
+	e_cmphl16i 4, low_sdarel@sdarel@l
+	e_cmphl16i 5, high_sdarel@sdarel@h
+	e_cmphl16i 2, high_adjust_sdarel@sdarel@ha
+
+	e_add2i. 1, low@l
+	e_add2i. 2, high@h
+	e_add2i. 3, high_adjust@ha
+	e_add2i. 4, low_sdarel@sdarel@l
+	e_add2i. 5, high_sdarel@sdarel@h
+	e_add2i. 2, high_adjust_sdarel@sdarel@ha
+
+	e_add2is 1, low@l
+	e_add2is 2, high@h
+	e_add2is 3, high_adjust@ha
+	e_add2is 4, low_sdarel@sdarel@l
+	e_add2is 5, high_sdarel@sdarel@h
+	e_add2is 2, high_adjust_sdarel@sdarel@ha
+
+	e_mull2i 1, low@l
+	e_mull2i 2, high@h
+	e_mull2i 3, high_adjust@ha
+	e_mull2i 4, low_sdarel@sdarel@l
+	e_mull2i 5, high_sdarel@sdarel@h
+	e_mull2i 2, high_adjust_sdarel@sdarel@ha
Index: testsuite/ld-powerpc/vle-reloc-3.d
===================================================================
RCS file: testsuite/ld-powerpc/vle-reloc-3.d
diff -N testsuite/ld-powerpc/vle-reloc-3.d
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ testsuite/ld-powerpc/vle-reloc-3.d	19 Feb 2012 21:49:35 -0000
@@ -0,0 +1,8 @@
+.*:     file format .*
+
+Disassembly of section .text:
+
+01800094 <sda21_test>:
+ 1800094:	1c ad 80 08 	e_add16i r5,r13,-32760
+ 1800098:	1c a2 80 04 	e_add16i r5,r2,-32764
+ 180009c:	70 00 00 a0 	e_li    r0,160
Index: testsuite/ld-powerpc/vle-reloc-3.s
===================================================================
RCS file: testsuite/ld-powerpc/vle-reloc-3.s
diff -N testsuite/ld-powerpc/vle-reloc-3.s
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ testsuite/ld-powerpc/vle-reloc-3.s	19 Feb 2012 21:49:35 -0000
@@ -0,0 +1,10 @@
+	.section .text
+	.extern exdat1c
+	.extern exdat2b
+	.extern exdat1a
+	.globl sda21_test
+
+sda21_test:
+	e_add16i  5, 4, exdat1c@sda21
+	e_add16i  5, 4, exdat2b@sda21
+	e_add16i  5, 4, exdat0b@sda21
Index: testsuite/ld-powerpc/vle-reloc-def-1.s
===================================================================
RCS file: testsuite/ld-powerpc/vle-reloc-def-1.s
diff -N testsuite/ld-powerpc/vle-reloc-def-1.s
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ testsuite/ld-powerpc/vle-reloc-def-1.s	19 Feb 2012 21:49:35 -0000
@@ -0,0 +1,13 @@
+	.section .text
+        .globl sub3
+sub3:
+        se_blr
+
+        .globl sub4
+sub4:
+        se_blr
+
+        .globl sub5
+sub5:
+        se_blr
+
Index: testsuite/ld-powerpc/vle-reloc-def-2.s
===================================================================
RCS file: testsuite/ld-powerpc/vle-reloc-def-2.s
diff -N testsuite/ld-powerpc/vle-reloc-def-2.s
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ testsuite/ld-powerpc/vle-reloc-def-2.s	19 Feb 2012 21:49:35 -0000
@@ -0,0 +1,41 @@
+	.section .text
+
+        .globl sub3
+sub3:
+        se_blr
+
+        .globl sub4
+sub4:
+        se_blr
+
+        .globl sub5
+sub5:
+        se_blr
+
+	.section .sdata
+	.globl low_sdarel
+low_sdarel:
+	.long	2
+
+	.globl high_adjust_sdarel
+high_adjust_sdarel:
+	.long	0xff
+
+	.section .sdata2
+	.globl	high_sdarel 
+high_sdarel:
+	.long	0xf
+
+
+	.data
+	.globl low
+low:
+	.long 5
+
+	.globl high
+high:
+	.long 0x10
+
+	.globl high_adjust
+high_adjust:
+	.long 0xffff
Index: testsuite/ld-powerpc/vle-reloc-def-3.s
===================================================================
RCS file: testsuite/ld-powerpc/vle-reloc-def-3.s
diff -N testsuite/ld-powerpc/vle-reloc-def-3.s
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ testsuite/ld-powerpc/vle-reloc-def-3.s	19 Feb 2012 21:49:35 -0000
@@ -0,0 +1,29 @@
+		.section .sdata
+		.globl exdat1a
+		.globl exdat1b
+		.globl exdat1c
+exdat1a:	.long 6
+exdat1b:	.long 7
+exdat1c:	.long 8
+
+		.section .sdata2
+		.globl exdat2a
+		.globl exdat2b
+		.globl exdat2c
+exdat2a:	 .long 5
+exdat2b:	 .long 4
+exdat2c:	 .long 3
+
+		.section .PPC.EMB.sdata0
+		.globl exdat0a
+		.globl exdat0b
+		.globl exdat0c
+exdat0a:	 .long 1
+exdat0b:	 .long 2
+exdat0c:	 .long 3
+
+		.section .sbss
+		.globl exbss1a
+		.globl exbss1b
+exbss1a:	.int
+exbss1b:	.int

Attachment: opcodes.cl
Description: Text document

Index: ppc-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/ppc-dis.c,v
retrieving revision 1.51
diff -p -u -r1.51 ppc-dis.c
--- ppc-dis.c	13 Dec 2011 08:19:01 -0000	1.51
+++ ppc-dis.c	21 Feb 2012 23:57:40 -0000
@@ -23,6 +23,8 @@
 #include <stdio.h>
 #include "sysdep.h"
 #include "dis-asm.h"
+#include "elf-bfd.h"
+#include "elf/ppc.h"
 #include "opintl.h"
 #include "opcode/ppc.h"
 
@@ -169,10 +171,28 @@ struct ppc_mopt ppc_opts[] = {
   { "titan",   (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_PMR
 		| PPC_OPCODE_RFMCI | PPC_OPCODE_TITAN),
     0 },
+  { "vle",     (PPC_OPCODE_PPC | PPC_OPCODE_ISEL | PPC_OPCODE_VLE),
+    PPC_OPCODE_VLE },
   { "vsx",     (PPC_OPCODE_PPC),
     PPC_OPCODE_VSX },
 };
 
+/* Switch between Booke and VLE dialects for interlinked dumps.  */
+static ppc_cpu_t
+get_powerpc_dialect (struct disassemble_info *info)
+{
+  ppc_cpu_t dialect = 0;
+
+  dialect = POWERPC_DIALECT (info);
+
+  /* Disassemble according to the section headers flags for VLE-mode.  */
+  if (dialect & PPC_OPCODE_VLE
+     && info->section->flags & SEC_PPC_VLE)
+    return dialect;
+  else
+   return dialect & ~ PPC_OPCODE_VLE;
+}
+
 /* Handle -m and -M options that set cpu type, and .machine arg.  */
 
 ppc_cpu_t
@@ -244,9 +264,12 @@ powerpc_init_dialect (struct disassemble
 	dialect |= PPC_OPCODE_64;
       else
 	dialect &= ~(ppc_cpu_t) PPC_OPCODE_64;
-      /* Choose a reasonable default.  */
-      dialect |= (PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_601
-		  | PPC_OPCODE_ALTIVEC);
+      if (info->mach == bfd_mach_ppc_vle)
+        dialect |= PPC_OPCODE_PPC | PPC_OPCODE_VLE;
+      else
+        /* Choose a reasonable default.  */
+        dialect |= (PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_601
+		    | PPC_OPCODE_ALTIVEC);
     }
 
   info->private_data = priv;
@@ -262,7 +285,7 @@ print_insn_big_powerpc (bfd_vma memaddr,
 {
   if (info->private_data == NULL && !powerpc_init_dialect (info))
     return -1;
-  return print_insn_powerpc (memaddr, info, 1, POWERPC_DIALECT(info));
+  return print_insn_powerpc (memaddr, info, 1, get_powerpc_dialect (info));
 }
 
 /* Print a little endian PowerPC instruction.  */
@@ -272,7 +295,7 @@ print_insn_little_powerpc (bfd_vma memad
 {
   if (info->private_data == NULL && !powerpc_init_dialect (info))
     return -1;
-  return print_insn_powerpc (memaddr, info, 0, POWERPC_DIALECT(info));
+  return print_insn_powerpc (memaddr, info, 0, get_powerpc_dialect (info));
 }
 
 /* Print a POWER (RS/6000) instruction.  */
@@ -296,11 +319,14 @@ operand_value_powerpc (const struct powe
     value = (*operand->extract) (insn, dialect, &invalid);
   else
     {
-      value = (insn >> operand->shift) & operand->bitm;
+      if (operand->shift >= 0)
+	value = (insn >> operand->shift) & operand->bitm;
+      else
+	value = (insn << -operand->shift) & operand->bitm;
       if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
 	{
 	  /* BITM is always some number of zeros followed by some
-	     number of ones, followed by some numer of zeros.  */
+	     number of ones, followed by some number of zeros.  */
 	  unsigned long top = operand->bitm;
 	  /* top & -top gives the rightmost 1 bit, so this
 	     fills in any trailing zeros.  */
@@ -344,15 +370,32 @@ print_insn_powerpc (bfd_vma memaddr,
   bfd_byte buffer[4];
   int status;
   unsigned long insn;
+  unsigned long mask, table_opcode;
   const struct powerpc_opcode *opcode;
   const struct powerpc_opcode *opcode_end;
   unsigned long op;
+  bfd_boolean insn_is_short, table_op_is_short;
 
   status = (*info->read_memory_func) (memaddr, buffer, 4, info);
   if (status != 0)
     {
-      (*info->memory_error_func) (status, memaddr, info);
-      return -1;
+      /* The final instruction may be a 2-byte VLE insn.  */
+      if ((dialect & PPC_OPCODE_VLE) != 0)
+        {
+          /* Clear buffer so unused bytes will not have garbage in them.  */
+          buffer[0] = buffer[1] = buffer[2] = buffer[3] = 0;
+          status = (*info->read_memory_func) (memaddr, buffer, 2, info);
+          if (status != 0)
+            {
+              (*info->memory_error_func) (status, memaddr, info);
+              return -1;
+            }
+        }
+      else
+        {
+          (*info->memory_error_func) (status, memaddr, info);
+          return -1;
+        }
     }
 
   if (bigendian)
@@ -360,8 +403,8 @@ print_insn_powerpc (bfd_vma memaddr,
   else
     insn = bfd_getl32 (buffer);
 
-  /* Get the major opcode of the instruction.  */
-  op = PPC_OP (insn);
+  /* Get the major opcode of the insn in short and long form.  */
+  op = PPC_OP (insn, 26);
 
   /* Find the first match in the opcode table.  We could speed this up
      a bit by doing a binary search on the major opcode.  */
@@ -370,6 +413,8 @@ print_insn_powerpc (bfd_vma memaddr,
   for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++)
     {
       unsigned long table_op;
+      unsigned long masked_op;
+      unsigned long masked_insn;
       const unsigned char *opindex;
       const struct powerpc_operand *operand;
       int invalid;
@@ -377,13 +422,41 @@ print_insn_powerpc (bfd_vma memaddr,
       int need_paren;
       int skip_optional;
 
-      table_op = PPC_OP (opcode->opcode);
-      if (op < table_op)
+      mask = opcode->mask;
+      table_opcode = opcode->opcode;
+      table_op_is_short = PPC_OP_SE_VLE (mask);
+      table_op = PPC_OP (table_opcode, PPC_OP_SA (mask));
+
+      masked_op = op;
+      if (table_op_is_short)
+        {
+          /* Some short instructions only have 4 or 5 opcode bits.  */
+          if ((mask & 0xfff) == 0)
+            masked_op &= 0x3c;
+          else if ((mask & 0x7ff) == 0)
+            masked_op &= 0x3e;
+        }
+      if (masked_op < table_op)
 	break;
-      if (op > table_op)
+      if (masked_op > table_op)
 	continue;
 
-      if ((insn & opcode->mask) != opcode->opcode
+      /* Handle 16-bit VLE instructions by comparing the
+         correct number of opcode bits.  The opcode field for
+         16-bit VLE instructions may only have 4 or 5 bits.  */
+
+      masked_insn = insn;
+      if (table_op_is_short)
+        {
+          if ((mask & 0xfff) == 0)
+            masked_insn &= 0xf3ffffff;
+          else if ((mask & 0x7ff) == 0)
+            masked_insn &= 0xfbffffff;
+          mask <<= 16;
+          table_opcode <<= 16;
+        }
+
+      if ((masked_insn & mask) != table_opcode
 	  || (opcode->flags & dialect) == 0
 	  || (dialect != ~(ppc_cpu_t) PPC_OPCODE_ANY
 	      && (opcode->deprecated & dialect) != 0))
@@ -408,6 +481,11 @@ print_insn_powerpc (bfd_vma memaddr,
       else
 	(*info->fprintf_func) (info->stream, "%s", opcode->name);
 
+      insn_is_short = table_op_is_short;
+      if (insn_is_short)
+        /* The operands will be fetched out of the 16-bit instruction.  */
+        insn >>= 16;
+
       /* Now extract and print the operands.  */
       need_comma = 0;
       need_paren = 0;
@@ -463,26 +541,26 @@ print_insn_powerpc (bfd_vma memaddr,
 	    (*info->fprintf_func) (info->stream, "fcr%ld", value);
 	  else if ((operand->flags & PPC_OPERAND_UDI) != 0)
 	    (*info->fprintf_func) (info->stream, "%ld", value);
-	  else if ((operand->flags & PPC_OPERAND_CR) != 0
-		   && (dialect & PPC_OPCODE_PPC) != 0)
+	  else if ((operand->flags & PPC_OPERAND_CR_REG) != 0
+		    && (((dialect & PPC_OPCODE_PPC) != 0)
+                          || ((dialect & PPC_OPCODE_VLE) != 0)))
+	    (*info->fprintf_func) (info->stream, "cr%ld", value);
+	  else if (((operand->flags & PPC_OPERAND_CR_BIT) != 0)
+		   && (((dialect & PPC_OPCODE_PPC) != 0)
+                        || ((dialect & PPC_OPCODE_VLE) != 0)))
 	    {
-	      if (operand->bitm == 7)
-		(*info->fprintf_func) (info->stream, "cr%ld", value);
-	      else
-		{
-		  static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
-		  int cr;
-		  int cc;
-
-		  cr = value >> 2;
-		  if (cr != 0)
-		    (*info->fprintf_func) (info->stream, "4*cr%d+", cr);
-		  cc = value & 3;
-		  (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
-		}
+	      static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
+	      int cr;
+	      int cc;
+
+	      cr = value >> 2;
+	      if (cr != 0)
+		(*info->fprintf_func) (info->stream, "4*cr%d+", cr);
+	      cc = value & 3;
+	      (*info->fprintf_func) (info->stream, "%s", cbnames[cc]);
 	    }
 	  else
-	    (*info->fprintf_func) (info->stream, "%ld", value);
+	    (*info->fprintf_func) (info->stream, "%d", value);
 
 	  if (need_paren)
 	    {
@@ -500,7 +578,14 @@ print_insn_powerpc (bfd_vma memaddr,
 	}
 
       /* We have found and printed an instruction; return.  */
-      return 4;
+      if (insn_is_short)
+        {
+          memaddr += 2;
+          return 2;
+        }
+      else
+        /* Otherwise, return.  */
+        return 4;
     }
 
   if ((dialect & PPC_OPCODE_ANY) != 0)
Index: ppc-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/ppc-opc.c,v
retrieving revision 1.140
diff -p -u -r1.140 ppc-opc.c
--- ppc-opc.c	13 Dec 2011 08:19:02 -0000	1.140
+++ ppc-opc.c	21 Feb 2012 23:57:40 -0000
@@ -39,6 +39,10 @@
 
 /* Local insertion and extraction functions.  */
 
+static unsigned long insert_arx (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_arx (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_ary (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_ary (unsigned long, ppc_cpu_t, int *);
 static unsigned long insert_bat (unsigned long, long, ppc_cpu_t, const char **);
 static long extract_bat (unsigned long, ppc_cpu_t, int *);
 static unsigned long insert_bba (unsigned long, long, ppc_cpu_t, const char **);
@@ -53,6 +57,8 @@ static unsigned long insert_boe (unsigne
 static long extract_boe (unsigned long, ppc_cpu_t, int *);
 static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **);
 static long extract_fxm (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_li20 (unsigned long, ppc_cpu_t, int *);
 static unsigned long insert_mbe (unsigned long, long, ppc_cpu_t, const char **);
 static long extract_mbe (unsigned long, ppc_cpu_t, int *);
 static unsigned long insert_mb6 (unsigned long, long, ppc_cpu_t, const char **);
@@ -61,15 +67,29 @@ static long extract_nb (unsigned long, p
 static unsigned long insert_nbi (unsigned long, long, ppc_cpu_t, const char **);
 static unsigned long insert_nsi (unsigned long, long, ppc_cpu_t, const char **);
 static long extract_nsi (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_oimm (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_oimm (unsigned long, ppc_cpu_t, int *);
 static unsigned long insert_ral (unsigned long, long, ppc_cpu_t, const char **);
 static unsigned long insert_ram (unsigned long, long, ppc_cpu_t, const char **);
 static unsigned long insert_raq (unsigned long, long, ppc_cpu_t, const char **);
 static unsigned long insert_ras (unsigned long, long, ppc_cpu_t, const char **);
 static unsigned long insert_rbs (unsigned long, long, ppc_cpu_t, const char **);
 static long extract_rbs (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_rx (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_rx (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_ry (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_ry (unsigned long, ppc_cpu_t, int *);
 static unsigned long insert_rbx (unsigned long, long, ppc_cpu_t, const char **);
 static unsigned long insert_sh6 (unsigned long, long, ppc_cpu_t, const char **);
 static long extract_sh6 (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_sci8 (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_sci8 (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_sci8n (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_sci8n (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_sd4h (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_sd4h (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_sd4w (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_sd4w (unsigned long, ppc_cpu_t, int *);
 static unsigned long insert_spr (unsigned long, long, ppc_cpu_t, const char **);
 static long extract_spr (unsigned long, ppc_cpu_t, int *);
 static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **);
@@ -88,6 +108,14 @@ static unsigned long insert_xc6 (unsigne
 static long extract_xc6 (unsigned long, ppc_cpu_t, int *);
 static unsigned long insert_dm (unsigned long, long, ppc_cpu_t, const char **);
 static long extract_dm (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_vlesi (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_vlesi (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_vlensi (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_vlensi (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_vleui (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_vleui (unsigned long, ppc_cpu_t, int *);
+static unsigned long insert_vleil (unsigned long, long, ppc_cpu_t, const char **);
+static long extract_vleil (unsigned long, ppc_cpu_t, int *);
 
 /* The operands table.
 
@@ -112,7 +140,7 @@ const struct powerpc_operand powerpc_ope
   /* The BI field in a B form or XL form instruction.  */
 #define BI BA
 #define BI_MASK (0x1f << 16)
-  { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR },
+  { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
 
   /* The BA field in an XL form instruction when it must be the same
      as the BT field in the same instruction.  */
@@ -122,7 +150,7 @@ const struct powerpc_operand powerpc_ope
   /* The BB field in an XL form instruction.  */
 #define BB BAT + 1
 #define BB_MASK (0x1f << 11)
-  { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR },
+  { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR_BIT },
 
   /* The BB field in an XL form instruction when it must be the same
      as the BA field in the same instruction.  */
@@ -167,7 +195,9 @@ const struct powerpc_operand powerpc_ope
 #define BF BDPA + 1
   /* The CRFD field in an X form instruction.  */
 #define CRFD BF
-  { 0x7, 23, NULL, NULL, PPC_OPERAND_CR },
+  /* The CRD field in an XL form instruction.  */
+#define CRD BF
+  { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG },
 
   /* The BF field in an X or XL form instruction.  */
 #define BFF BF + 1
@@ -176,11 +206,11 @@ const struct powerpc_operand powerpc_ope
   /* An optional BF field.  This is used for comparison instructions,
      in which an omitted BF field is taken as zero.  */
 #define OBF BFF + 1
-  { 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
+  { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
 
   /* The BFA field in an X or XL form instruction.  */
 #define BFA OBF + 1
-  { 0x7, 18, NULL, NULL, PPC_OPERAND_CR },
+  { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG },
 
   /* The BO field in a B form instruction.  Certain values are
      illegal.  */
@@ -198,14 +228,40 @@ const struct powerpc_operand powerpc_ope
 
   /* The BT field in an X or XL form instruction.  */
 #define BT BH + 1
-  { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR },
+  { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT },
+
+  /* The BI16 field in a BD8 form instruction.  */
+#define BI16 BT + 1
+  { 0x3, 8, NULL, NULL, PPC_OPERAND_CR_BIT },
+
+  /* The BI32 field in a BD15 form instruction.  */
+#define BI32 BI16 + 1
+  { 0xf, 16, NULL, NULL, PPC_OPERAND_CR_BIT },
+
+  /* The BO32 field in a BD15 form instruction.  */
+#define BO32 BI32 + 1
+  { 0x3, 20, NULL, NULL, 0 },
+
+  /* The B8 field in a BD8 form instruction.  */
+#define B8 BO32 + 1
+  { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
+
+  /* The B15 field in a BD15 form instruction.  The lowest bit is
+     forced to zero.  */
+#define B15 B8 + 1
+  { 0xfffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
+
+  /* The B24 field in a BD24 form instruction.  The lowest bit is
+     forced to zero.  */
+#define B24 B15 + 1
+  { 0x1fffffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
 
   /* The condition register number portion of the BI field in a B form
      or XL form instruction.  This is used for the extended
      conditional branch mnemonics, which set the lower two bits of the
      BI field.  This field is optional.  */
-#define CR BT + 1
-  { 0x7, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
+#define CR B24 + 1
+  { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
 
   /* The CRB field in an X form instruction.  */
 #define CRB CR + 1
@@ -214,12 +270,19 @@ const struct powerpc_operand powerpc_ope
 #define MB_MASK (0x1f << 6)
   { 0x1f, 6, NULL, NULL, 0 },
 
+  /* The CRD32 field in an XL form instruction.  */
+#define CRD32 CRB + 1
+  { 0x3, 21, NULL, NULL, PPC_OPERAND_CR_REG },
+
   /* The CRFS field in an X form instruction.  */
-#define CRFS CRB + 1
-  { 0x7, 0, NULL, NULL, PPC_OPERAND_CR },
+#define CRFS CRD32 + 1
+  { 0x7, 0, NULL, NULL, PPC_OPERAND_CR_REG },
+
+#define CRS CRFS + 1
+  { 0x3, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
 
   /* The CT field in an X form instruction.  */
-#define CT CRFS + 1
+#define CT CRS + 1
   /* The MO field in an mbar instruction.  */
 #define MO CT
   { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
@@ -230,9 +293,15 @@ const struct powerpc_operand powerpc_ope
 #define D CT + 1
   { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 
+  /* The D8 field in a D form instruction.  This is a displacement off
+     a register, and implies that the next operand is a register in
+     parentheses.  */
+#define D8 D + 1
+  { 0xff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
+
   /* The DQ field in a DQ form instruction.  This is like D, but the
      lower four bits are forced to zero. */
-#define DQ D + 1
+#define DQ D8 + 1
   { 0xfff0, 0, NULL, NULL,
     PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
 
@@ -309,8 +378,12 @@ const struct powerpc_operand powerpc_ope
 #define FXM4 FXM + 1
   { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
 
+  /* The IMM20 field in an LI instruction.  */
+#define IMM20 FXM4 + 1
+  { 0xfffff, PPC_OPSHIFT_INV, insert_li20, extract_li20, PPC_OPERAND_SIGNED},
+
   /* The L field in a D or X form instruction.  */
-#define L FXM4 + 1
+#define L IMM20 + 1
   { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 
   /* The LEV field in a POWER SVC form instruction.  */
@@ -372,7 +445,7 @@ const struct powerpc_operand powerpc_ope
   { 0xffff, 0, insert_nsi, extract_nsi,
       PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
 
-  /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction.  */
+  /* The RA field in a D, DS, DQ, X, XO, M, or MDS form instruction.  */
 #define RA NSI + 1
 #define RA_MASK (0x1f << 16)
   { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },
@@ -431,10 +504,11 @@ const struct powerpc_operand powerpc_ope
 
   /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
      instruction or the RT field in a D, DS, X, XFX or XO form
-     instruction.  */
+     instruction or the RD field in an I16L form instruction.  */
 #define RS RBOPT + 1
 #define RT RS
 #define RT_MASK (0x1f << 21)
+#define RD RS
   { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
 
   /* The RS and RT fields of the DS form stq instruction, which have
@@ -448,8 +522,47 @@ const struct powerpc_operand powerpc_ope
 #define RTO RSO
   { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },
 
+  /* The RX field of the SE_RR form instruction.  */
+#define RX RSO + 1
+  { 0x1f, PPC_OPSHIFT_INV, insert_rx, extract_rx, PPC_OPERAND_GPR },
+
+  /* The ARX field of the SE_RR form instruction.  */
+#define ARX RX + 1
+  { 0x1f, PPC_OPSHIFT_INV, insert_arx, extract_arx, PPC_OPERAND_GPR },
+
+  /* The RY field of the SE_RR form instruction.  */
+#define RY ARX + 1
+#define RZ RY
+  { 0x1f, PPC_OPSHIFT_INV, insert_ry, extract_ry, PPC_OPERAND_GPR },
+
+  /* The ARY field of the SE_RR form instruction.  */
+#define ARY RY + 1
+  { 0x1f, PPC_OPSHIFT_INV, insert_ary, extract_ary, PPC_OPERAND_GPR },
+
+  /* The SCLSCI8 field in a D form instruction.  */
+#define SCLSCI8 ARY + 1
+  { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8, extract_sci8, 0 },
+
+  /* The SCLSCI8N field in a D form instruction.  This is the same as the
+     SCLSCI8 field, only negated.  */
+#define SCLSCI8N SCLSCI8 + 1
+  { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8n, extract_sci8n,
+      PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
+
+  /* The SD field of the SD4 form instruction.  */
+#define SE_SD SCLSCI8N + 1
+  { 0xf, 8, NULL, NULL, PPC_OPERAND_PARENS },
+
+  /* The SD field of the SD4 form instruction, for halfword.  */
+#define SE_SDH SE_SD + 1
+  { 0x1e, PPC_OPSHIFT_INV, insert_sd4h, extract_sd4h, PPC_OPERAND_PARENS },
+
+  /* The SD field of the SD4 form instruction, for word.  */
+#define SE_SDW SE_SDH + 1
+  { 0x3c, PPC_OPSHIFT_INV, insert_sd4w, extract_sd4w, PPC_OPERAND_PARENS },
+
   /* The SH field in an X or M form instruction.  */
-#define SH RSO + 1
+#define SH SE_SDW + 1
 #define SH_MASK (0x1f << 11)
   /* The other UIMM field in a EVX form instruction.  */
 #define EVUIMM SH
@@ -458,7 +571,7 @@ const struct powerpc_operand powerpc_ope
   /* The SH field in an MD form instruction.  This is split.  */
 #define SH6 SH + 1
 #define SH6_MASK ((0x1f << 11) | (1 << 1))
-  { 0x3f, -1, insert_sh6, extract_sh6, 0 },
+  { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 },
 
   /* The SH field of the tlbwe instruction, which is optional.  */
 #define SHO SH6 + 1
@@ -473,9 +586,13 @@ const struct powerpc_operand powerpc_ope
 #define SISIGNOPT SI + 1
   { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
 
+  /* The SI8 field in a D form instruction.  */
+#define SI8 SISIGNOPT + 1
+  { 0xff, 0, NULL, NULL, PPC_OPERAND_SIGNED },
+
   /* The SPR field in an XFX form instruction.  This is flipped--the
      lower 5 bits are stored in the upper 5 and vice- versa.  */
-#define SPR SISIGNOPT + 1
+#define SPR SI8 + 1
 #define PMR SPR
 #define SPR_MASK (0x3ff << 11)
   { 0x3ff, 11, insert_spr, extract_spr, 0 },
@@ -518,8 +635,20 @@ const struct powerpc_operand powerpc_ope
 #define UI TO + 1
   { 0xffff, 0, NULL, NULL, 0 },
 
+  /* The IMM field in an SE_IM5 instruction.  */
+#define UI5 UI + 1
+  { 0x1f, 4, NULL, NULL, 0 },
+
+  /* The OIMM field in an SE_OIM5 instruction.  */
+#define OIMM5 UI5 + 1
+  { 0x1f, PPC_OPSHIFT_INV, insert_oimm, extract_oimm, PPC_OPERAND_PLUS1 },
+
+  /* The UI7 field in an SE_LI instruction.  */
+#define UI7 OIMM5 + 1
+  { 0x7f, 4, NULL, NULL, 0 },
+
   /* The VA field in a VA, VX or VXR form instruction.  */
-#define VA UI + 1
+#define VA UI7 + 1
   { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },
 
   /* The VB field in a VA, VX or VXR form instruction.  */
@@ -567,10 +696,12 @@ const struct powerpc_operand powerpc_ope
   /* PowerPC paired singles extensions.  */
   /* W bit in the pair singles instructions for x type instructions.  */
 #define PSWM WS + 1
-  {  0x1, 10, 0, 0, 0 },
+  /* The BO16 field in a BD8 form instruction.  */
+#define BO16 PSWM
+  { 0x1, 10, NULL, NULL, 0 },
 
   /* IDX bits for quantization in the pair singles instructions.  */
-#define PSQ PSWM + 1
+#define PSQ BO16 + 1
   {  0x7, 12, 0, 0, 0 },
 
   /* IDX bits for quantization in the pair singles x-type instructions.  */
@@ -636,28 +767,46 @@ const struct powerpc_operand powerpc_ope
 #define URC URB + 1
   { 0x1f, 6, 0, 0, PPC_OPERAND_UDI },
 
+  /* The VLESIMM field in a D form instruction.  */
+#define VLESIMM URC + 1
+  { 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi,
+      PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
+
+  /* The VLENSIMM field in a D form instruction.  */
+#define VLENSIMM VLESIMM + 1
+  { 0xffff, PPC_OPSHIFT_INV, insert_vlensi, extract_vlensi,
+      PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
+
+  /* The VLEUIMM field in a D form instruction.  */
+#define VLEUIMM VLENSIMM + 1
+  { 0xffff, PPC_OPSHIFT_INV, insert_vleui, extract_vleui, 0 },
+
+  /* The VLEUIMML field in a D form instruction.  */
+#define VLEUIMML VLEUIMM + 1
+  { 0xffff, PPC_OPSHIFT_INV, insert_vleil, extract_vleil, 0 },
+
   /* The XT and XS fields in an XX1 or XX3 form instruction.  This is split.  */
-#define XS6 URC + 1
+#define XS6 VLEUIMML + 1
 #define XT6 XS6
-  { 0x3f, -1, insert_xt6, extract_xt6, PPC_OPERAND_VSR },
+  { 0x3f, PPC_OPSHIFT_INV, insert_xt6, extract_xt6, PPC_OPERAND_VSR },
 
   /* The XA field in an XX3 form instruction.  This is split.  */
 #define XA6 XT6 + 1
-  { 0x3f, -1, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
+  { 0x3f, PPC_OPSHIFT_INV, insert_xa6, extract_xa6, PPC_OPERAND_VSR },
 
   /* The XB field in an XX2 or XX3 form instruction.  This is split.  */
 #define XB6 XA6 + 1
-  { 0x3f, -1, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
+  { 0x3f, PPC_OPSHIFT_INV, insert_xb6, extract_xb6, PPC_OPERAND_VSR },
 
   /* The XB field in an XX3 form instruction when it must be the same as
      the XA field in the instruction.  This is used in extended mnemonics
      like xvmovdp.  This is split.  */
 #define XB6S XB6 + 1
-  { 0x3f, -1, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE },
+  { 0x3f, PPC_OPSHIFT_INV, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE },
 
   /* The XC field in an XX4 form instruction.  This is split.  */
 #define XC6 XB6S + 1
-  { 0x3f, -1, insert_xc6, extract_xc6, PPC_OPERAND_VSR },
+  { 0x3f, PPC_OPSHIFT_INV, insert_xc6, extract_xc6, PPC_OPERAND_VSR },
 
   /* The DM or SHW field in an XX3 form instruction.  */
 #define DM XC6 + 1
@@ -681,6 +830,112 @@ const unsigned int num_powerpc_operands 
 
 /* The functions used to insert and extract complicated operands.  */
 
+/* The ARX, ARY, RX and RY operands are alternate encodings of GPRs.  */
+
+static unsigned long
+insert_arx (unsigned long insn,
+	    long value,
+	    ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	    const char **errmsg ATTRIBUTE_UNUSED)
+{
+  if (value >= 8 && value < 24)
+    return insn | ((value - 8) & 0xf);
+  else
+    {
+      *errmsg = _("invalid register");
+      return 0;
+    }
+}
+
+static long
+extract_arx (unsigned long insn,
+	     ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	     int *invalid ATTRIBUTE_UNUSED)
+{
+  return (insn & 0xf) + 8;
+}
+
+static unsigned long
+insert_ary (unsigned long insn,
+	    long value,
+	    ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	    const char **errmsg ATTRIBUTE_UNUSED)
+{
+  if (value >= 8 && value < 24)
+    return insn | (((value - 8) & 0xf) << 4);
+  else
+    {
+      *errmsg = _("invalid register");
+      return 0;
+    }
+}
+
+static long
+extract_ary (unsigned long insn,
+	     ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	     int *invalid ATTRIBUTE_UNUSED)
+{
+  return ((insn >> 4) & 0xf) + 8;
+}
+
+static unsigned long
+insert_rx (unsigned long insn,
+	    long value,
+	    ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	    const char **errmsg)
+{
+  if (value >=0 && value < 8)
+    return insn | value;
+  else if (value >= 24 && value <= 31)
+    return insn | (value - 16);
+  else
+    {
+      *errmsg = _("invalid register");
+      return 0;
+    }
+}
+
+static long
+extract_rx (unsigned long insn,
+	     ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	     int *invalid ATTRIBUTE_UNUSED)
+{
+  int value = insn & 0xf;
+  if (value >=0 && value < 8)
+    return value;
+  else
+    return value + 16;
+}
+
+static unsigned long
+insert_ry (unsigned long insn,
+	    long value,
+	    ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	    const char **errmsg)
+{
+  if (value >=0 && value < 8)
+    return insn | (value << 4);
+  else if (value >= 24 && value <= 31)
+    return insn | ((value - 16) << 4);
+  else
+    {
+      *errmsg = _("invalid register");
+      return 0;
+    }
+}
+
+static long
+extract_ry (unsigned long insn,
+	     ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	     int *invalid ATTRIBUTE_UNUSED)
+{
+  int value = (insn >> 4) & 0xf;
+  if (value >=0 && value < 8)
+    return value;
+  else
+    return value + 16;
+}
+
 /* The BA field in an XL form instruction when it must be the same as
    the BT field in the same instruction.  This operand is marked FAKE.
    The insertion function just copies the BT field into the BA field,
@@ -913,7 +1168,7 @@ insert_bo (unsigned long insn,
 {
   if (!valid_bo (value, dialect, 0))
     *errmsg = _("invalid conditional option");
-  else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
+  else if (PPC_OP (insn, 26) == 19 && (insn & 0x400) && ! (value & 4))
     *errmsg = _("invalid counter access");
   return insn | ((value & 0x1f) << 21);
 }
@@ -943,7 +1198,7 @@ insert_boe (unsigned long insn,
 {
   if (!valid_bo (value, dialect, 0))
     *errmsg = _("invalid conditional option");
-  else if (PPC_OP (insn) == 19 && (insn & 0x400) && ! (value & 4))
+  else if (PPC_OP (insn, 26) == 19 && (insn & 0x400) && ! (value & 4))
     *errmsg = _("invalid counter access");
   else if ((value & 1) != 0)
     *errmsg = _("attempt to set y bit when using + or - modifier");
@@ -1036,6 +1291,32 @@ extract_fxm (unsigned long insn,
   return mask;
 }
 
+static unsigned long
+insert_li20 (unsigned long insn,
+	    long value,
+	    ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	    const char **errmsg ATTRIBUTE_UNUSED)
+{
+  return insn
+	 | ((value & 0xf0000) >> 5)
+	 | ((value & 0x0f800) << 5)
+	 | (value & 0x7ff);
+}
+
+static long
+extract_li20 (unsigned long insn,
+	     ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	     int *invalid ATTRIBUTE_UNUSED)
+{
+  long ext = ((insn & 0x4000) == 0x4000) ? 0xfff00000 : 0x00000000;
+  
+  return ext
+         | (((insn >> 11) & 0xf) << 16) 
+         | (((insn >> 17) & 0xf) << 12)
+         | (((insn >> 16) & 0x1) << 11)
+         | (insn & 0x7ff);
+}
+
 /* The MB and ME fields in an M form instruction expressed as a single
    operand which is itself a bitmask.  The extraction function always
    marks it as invalid, since we never want to recognize an
@@ -1305,6 +1586,166 @@ insert_rbx (unsigned long insn,
   return insn | ((value & 0x1f) << 11);
 }
 
+/* The SCI8 field is made up of SCL and {U,N}I8 fields.  */
+static unsigned long
+insert_sci8 (unsigned long insn,
+	    long value,
+	    ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	    const char **errmsg)
+{
+  int fill = 0;
+  int scale_factor = 0;
+  long ui8 = value;
+
+  if ((value & 0xff000000) == (unsigned int) value)
+    {
+      scale_factor = 3;
+      ui8 = value >> 24;
+      fill = 0;
+    }
+  else if ((value & 0xff0000) == (unsigned int) value)
+    {
+      scale_factor = 2;
+      ui8 = value >> 16;
+      fill = 0;
+    }
+  else if ((value & 0xff00) == (unsigned int) value)
+    {
+      scale_factor = 1;
+      ui8 = value >> 8;
+      fill = 0;
+    }
+  else if ((value & 0xff) == value)
+    {
+      scale_factor = 0;
+      ui8 = value;
+      fill = 0;
+    }
+  else if ((value & 0xffffff00) == 0xffffff00)
+    {
+      scale_factor = 0;
+      ui8 = (value & 0xff);
+      fill = 1;
+    }
+  else if ((value & 0xffff00ff) == 0xffff00ff)
+    {
+      scale_factor = 1;
+      ui8 = (value & 0xff00) >> 8;
+      fill = 1;
+    }
+  else if ((value & 0xff00ffff) == 0xff00ffff)
+    {
+      scale_factor = 2;
+      ui8 = (value & 0xff0000) >> 16;
+      fill = 1;
+    }
+  else if ((value & 0x00ffffff) == 0x00ffffff)
+    {
+      scale_factor = 3;
+      ui8 = (value & 0xff000000) >> 24;
+      fill = 1;
+    }
+  else
+    *errmsg = _("illegal immediate value");
+
+  return insn | (fill << 10) | (scale_factor << 8) | (ui8 & 0xff);
+}
+
+static long
+extract_sci8 (unsigned long insn,
+	     ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	     int *invalid ATTRIBUTE_UNUSED)
+{
+  int scale_factor, fill;
+  scale_factor = (insn & 0x300) >> 8;
+  fill = (insn & 0x00000400) >> 10;
+
+  if (fill == 0)
+    return (insn & 0xff) << (scale_factor << 3);
+
+  /* Fill is one.  */
+  if (scale_factor == 0)
+    return (insn & 0xff) | 0xffffff00;
+  else if (scale_factor == 1)
+    return 0xffff00ff | ((insn & 0xff) << (scale_factor << 3));
+  else if (scale_factor == 2)
+    return 0xff00ffff | (insn & 0xff << (scale_factor << 3));
+  else /* scale_factor 3 */
+    return 0x00ffffff | (insn & 0xff << (scale_factor << 3));
+}
+
+static unsigned long
+insert_sci8n (unsigned long insn,
+	    long value,
+	    ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	    const char **errmsg)
+{
+  insn = insert_sci8 (insn, -(value & 0xff) & 0xff, 0, errmsg);
+  /* Set the F bit.  */
+  return insn | 0x400;
+}
+
+static long
+extract_sci8n (unsigned long insn,
+	     ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	     int *invalid ATTRIBUTE_UNUSED)
+{
+  int scale_factor;
+  scale_factor = (insn & 0x300) >> 8;
+  return -(((insn & 0xff) ^ 0x80) - 0x80) << (scale_factor << 3);
+}
+
+static unsigned long
+insert_sd4h (unsigned long insn,
+	    long value,
+	    ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	    const char **errmsg ATTRIBUTE_UNUSED)
+{
+  return insn | ((value & 0x1e) << 7);
+}
+
+static long
+extract_sd4h (unsigned long insn,
+	     ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	     int *invalid ATTRIBUTE_UNUSED)
+{
+  return ((insn >> 8) & 0xf) << 1;
+}
+
+static unsigned long
+insert_sd4w (unsigned long insn,
+	    long value,
+	    ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	    const char **errmsg ATTRIBUTE_UNUSED)
+{
+  return insn | ((value & 0x3c) << 6);
+}
+
+static long
+extract_sd4w (unsigned long insn,
+	     ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	     int *invalid ATTRIBUTE_UNUSED)
+{
+  return ((insn >> 8) & 0xf) << 2;
+}
+
+static unsigned long
+insert_oimm (unsigned long insn,
+	    long value,
+	    ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	    const char **errmsg ATTRIBUTE_UNUSED)
+{
+  return insn | (((value - 1) & 0x1f) << 4);
+}
+
+static long
+extract_oimm (unsigned long insn,
+	     ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	     int *invalid ATTRIBUTE_UNUSED)
+{
+  return ((insn >> 4) & 0x1f) + 1;
+}
+
 /* The SH field in an MD form instruction.  This is split.  */
 
 static unsigned long
@@ -1345,6 +1786,7 @@ extract_spr (unsigned long insn,
 }
 
 /* Some dialects have 8 SPRG registers instead of the standard 4.  */
+#define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405 | PPC_OPCODE_VLE)
 
 static unsigned long
 insert_sprg (unsigned long insn,
@@ -1354,7 +1796,7 @@ insert_sprg (unsigned long insn,
 {
   if (value > 7
       || (value > 3
-	  && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_405)) == 0))
+	  && (dialect & ALLOW8_SPRG) == 0))
     *errmsg = _("invalid sprg number");
 
   /* If this is mfsprg4..7 then use spr 260..263 which can be read in
@@ -1374,7 +1816,7 @@ extract_sprg (unsigned long insn,
 
   /* mfsprg can use 260..263 and 272..279.  mtsprg only uses spr 272..279
      If not BOOKE or 405, then both use only 272..275.  */
-  if ((val - 0x10 > 3 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_405)) == 0)
+  if ((val - 0x10 > 3 && (dialect & ALLOW8_SPRG) == 0)
       || (val - 0x10 > 7 && (insn & 0x100) != 0)
       || val <= 3
       || (val & 8) != 0)
@@ -1541,6 +1983,89 @@ extract_dm (unsigned long insn,
     *invalid = 1;
   return (value) ? 1 : 0;
 }
+
+/* The VLESIMM field in an I16A form instruction.  This is split.  */
+
+static unsigned long
+insert_vlesi (unsigned long insn,
+	    long value,
+	    ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	    const char **errmsg ATTRIBUTE_UNUSED)
+{
+  return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
+}
+
+static long
+extract_vlesi (unsigned long insn,
+	     ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	     int *invalid ATTRIBUTE_UNUSED)
+{
+  long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
+  if (value & 0x8000)
+    value |= 0xffff0000;
+  return value;
+}
+
+static unsigned long
+insert_vlensi (unsigned long insn,
+	    long value,
+	    ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	    const char **errmsg ATTRIBUTE_UNUSED)
+{
+  value = -value;
+  return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
+}
+
+static long
+extract_vlensi (unsigned long insn,
+	     ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	     int *invalid ATTRIBUTE_UNUSED)
+{
+  long value = ((insn >> 10) & 0xf800) | (insn & 0x7ff);
+  if (value & 0x8000)
+    value |= 0xffff0000;
+  *invalid = 1;
+  return -value;
+}
+
+/* The VLEUIMM field in an I16A form instruction.  This is split.  */
+
+static unsigned long
+insert_vleui (unsigned long insn,
+	    long value,
+	    ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	    const char **errmsg ATTRIBUTE_UNUSED)
+{
+  return insn | ((value & 0xf800) << 10) | (value & 0x7ff);
+}
+
+static long
+extract_vleui (unsigned long insn,
+	     ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	     int *invalid ATTRIBUTE_UNUSED)
+{
+  return ((insn >> 10) & 0xf800) | (insn & 0x7ff);
+}
+
+/* The VLEUIMML field in an I16L form instruction.  This is split.  */
+
+static unsigned long
+insert_vleil (unsigned long insn,
+	    long value,
+	    ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	    const char **errmsg ATTRIBUTE_UNUSED)
+{
+  return insn | ((value & 0xf800) << 5) | (value & 0x7ff);
+}
+
+static long
+extract_vleil (unsigned long insn,
+	     ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+	     int *invalid ATTRIBUTE_UNUSED)
+{
+  return ((insn >> 5) & 0xf800) | (insn & 0x7ff);
+}
+
 
 /* Macros used to form opcodes.  */
 
@@ -1560,6 +2085,11 @@ extract_dm (unsigned long insn,
 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
 #define OPL_MASK OPL (0x3f,1)
 
+/* The main opcode combined with an update code in D form instruction.
+   Used for extended mnemonics for VLE memory instructions.  */
+#define OPVUP(x,vup) (OP (x) | ((((unsigned long)(vup)) & 0xff) << 8))
+#define OPVUP_MASK OPVUP (0x3f,  0xff)
+
 /* An A form instruction.  */
 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
 #define A_MASK A (0x3f, 0x1f, 1)
@@ -1580,6 +2110,43 @@ extract_dm (unsigned long insn,
 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
 #define B_MASK B (0x3f, 1, 1)
 
+/* A BD8 form instruction.  This is a 16-bit instruction.  */
+#define BD8(op, aa, lk) (((((unsigned long)(op)) & 0x3f) << 10) | (((aa) & 1) << 9) | (((lk) & 1) << 8))
+#define BD8_MASK BD8 (0x3f, 1, 1)
+
+/* Another BD8 form instruction.  This is a 16-bit instruction.  */
+#define BD8IO(op) ((((unsigned long)(op)) & 0x1f) << 11)
+#define BD8IO_MASK BD8IO (0x1f)
+
+/* A BD8 form instruction for simplified mnemonics.  */
+#define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8))
+/* A mask that excludes BO32 and BI32.  */
+#define EBD8IO1_MASK 0xf800
+/* A mask that includes BO32 and excludes BI32.  */
+#define EBD8IO2_MASK 0xfc00
+/* A mask that include BO32 AND BI32.  */
+#define EBD8IO3_MASK 0xff00
+
+/* A BD15 form instruction.  */
+#define BD15(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 0xf) << 22) | ((lk) & 1))
+#define BD15_MASK BD15 (0x3f, 0xf, 1)
+
+/* A BD15 form instruction for extended conditional branch mnemonics.  */
+#define EBD15(op, aa, bo, lk) (((op) & 0x3f) << 26) | (((aa) & 0xf) << 22) | (((bo) & 0x3) << 20) | ((lk) & 1)
+#define EBD15_MASK 0xfff00001
+
+/* A BD15 form instruction for extended conditional branch mnemonics with BI.  */
+#define EBD15BI(op, aa, bo, bi, lk) (((op) & 0x3f) << 26) \
+				    | (((aa) & 0xf) << 22) \
+				    | (((bo) & 0x3) << 20) \
+				    | (((bi) & 0x3) << 16) \
+				    | ((lk) & 1)
+#define EBD15BI_MASK  0xfff30001
+
+/* A BD24 form instruction.  */
+#define BD24(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 25) | ((lk) & 1))
+#define BD24_MASK BD24 (0x3f, 1, 1)
+
 /* A B form instruction setting the BO field.  */
 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
@@ -1608,11 +2175,17 @@ extract_dm (unsigned long insn,
 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
 
-/* An Context form instruction.  */
+/* A VLE C form instruction.  */
+#define C_LK(x, lk) (((((unsigned long)(x)) & 0x7fff) << 1) | ((lk) & 1))
+#define C_LK_MASK C_LK(0x7fff, 1)
+#define C(x) ((((unsigned long)(x)) & 0xffff))
+#define C_MASK C(0xffff)
+
+/* A Context form instruction.  */
 #define CTX(op, xop)   (OP (op) | (((unsigned long)(xop)) & 0x7))
 #define CTX_MASK CTX(0x3f, 0x7)
 
-/* An User Context form instruction.  */
+/* A User Context form instruction.  */
 #define UCTX(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
 #define UCTX_MASK UCTX(0x3f, 0x1f)
 
@@ -1627,10 +2200,30 @@ extract_dm (unsigned long insn,
 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
 #define EVSEL_MASK EVSEL(0x3f, 0xff)
 
+/* An IA16 form instruction.  */
+#define IA16(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
+#define IA16_MASK IA16(0x3f, 0x1f)
+
+/* An I16A form instruction.  */
+#define I16A(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
+#define I16A_MASK I16A(0x3f, 0x1f)
+
+/* An I16L form instruction.  */
+#define I16L(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f) << 11)
+#define I16L_MASK I16L(0x3f, 0x1f)
+
+/* An IM7 form instruction.  */
+#define IM7(op) ((((unsigned long)(op)) & 0x1f) << 11)
+#define IM7_MASK IM7(0x1f)
+
 /* An M form instruction.  */
 #define M(op, rc) (OP (op) | ((rc) & 1))
 #define M_MASK M (0x3f, 1)
 
+/* An LI20 form instruction.  */
+#define LI20(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1) << 15)
+#define LI20_MASK LI20(0x3f, 0x1)
+
 /* An M form instruction with the ME field specified.  */
 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
 
@@ -1661,19 +2254,43 @@ extract_dm (unsigned long insn,
 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
 
-/* An VX form instruction.  */
+/* An SCI8 form instruction.  */
+#define SCI8(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11))
+#define SCI8_MASK SCI8(0x3f, 0x1f)
+
+/* An SCI8 form instruction.  */
+#define SCI8BF(op, fop, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 11) | (((fop) & 7) << 23))
+#define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f)
+
+/* An SD4 form instruction.  This is a 16-bit instruction.  */
+#define SD4(op) ((((unsigned long)(op)) & 0xf) << 12) 
+#define SD4_MASK SD4(0xf)
+
+/* An SE_IM5 form instruction.  This is a 16-bit instruction.  */
+#define SE_IM5(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x1) << 9))
+#define SE_IM5_MASK SE_IM5(0x3f, 1)
+
+/* An SE_R form instruction.  This is a 16-bit instruction.  */
+#define SE_R(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3f) << 4))
+#define SE_R_MASK SE_R(0x3f, 0x3f)
+
+/* An SE_RR form instruction.  This is a 16-bit instruction.  */
+#define SE_RR(op, xop) (((((unsigned long)(op)) & 0x3f) << 10) | (((xop) & 0x3) << 8))
+#define SE_RR_MASK SE_RR(0x3f, 3)
+
+/* A VX form instruction.  */
 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
 
-/* The mask for an VX form instruction.  */
+/* The mask for a VX form instruction.  */
 #define VX_MASK	VX(0x3f, 0x7ff)
 
-/* An VA form instruction.  */
+/* A VA form instruction.  */
 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
 
-/* The mask for an VA form instruction.  */
+/* The mask for a VA form instruction.  */
 #define VXA_MASK VXA(0x3f, 0x3f)
 
-/* An VXR form instruction.  */
+/* A VXR form instruction.  */
 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
 
 /* The mask for a VXR form instruction.  */
@@ -1682,6 +2299,12 @@ extract_dm (unsigned long insn,
 /* An X form instruction.  */
 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
 
+/* An EX form instruction.  */
+#define EX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
+
+/* The mask for an EX form instruction.  */
+#define EX_MASK EX (0x3f, 0x7ff)
+
 /* An XX2 form instruction.  */
 #define XX2(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2))
 
@@ -1950,6 +2573,16 @@ extract_dm (unsigned long insn,
 
 #define BOU	(0x14)
 
+/* The BO16 encodings used in extended VLE conditional branch mnemonics.  */
+#define BO16F	(0x0)
+#define BO16T	(0x1)
+
+/* The BO32 encodings used in extended VLE conditional branch mnemonics.  */
+#define BO32F	(0x0)
+#define BO32T	(0x1)
+#define BO32DNZ	(0x2)
+#define BO32DZ	(0x3)
+
 /* The BI condition bit encodings used in extended conditional branch
    mnemonics.  */
 #define CBLT	(0)
@@ -2009,11 +2642,11 @@ extract_dm (unsigned long insn,
 #define MFDEC1	PPC_OPCODE_POWER
 #define MFDEC2	PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN
 #define BOOKE	PPC_OPCODE_BOOKE
-#define NO371	PPC_OPCODE_BOOKE | PPC_OPCODE_EFS
+#define NO371	PPC_OPCODE_BOOKE | PPC_OPCODE_EFS | PPC_OPCODE_VLE
 #define PPCE300 PPC_OPCODE_E300
-#define PPCSPE	PPC_OPCODE_SPE
-#define PPCISEL PPC_OPCODE_ISEL
-#define PPCEFS	PPC_OPCODE_EFS
+#define PPCSPE	PPC_OPCODE_SPE | PPC_OPCODE_VLE
+#define PPCISEL PPC_OPCODE_ISEL | PPC_OPCODE_VLE
+#define PPCEFS	PPC_OPCODE_EFS | PPC_OPCODE_VLE
 #define PPCBRLK PPC_OPCODE_BRLOCK
 #define PPCPMR	PPC_OPCODE_PMR
 #define PPCCHLK PPC_OPCODE_CACHELCK
@@ -2021,14 +2654,15 @@ extract_dm (unsigned long insn,
 #define E500MC  PPC_OPCODE_E500MC
 #define PPCA2	PPC_OPCODE_A2
 #define TITAN   PPC_OPCODE_TITAN  
-#define MULHW   PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN
+#define MULHW   PPC_OPCODE_405 | PPC_OPCODE_440 | TITAN | PPC_OPCODE_VLE
 #define E500	PPC_OPCODE_E500
+#define PPCVLE	PPC_OPCODE_VLE
 
 /* The opcode table.
 
    The format of the opcode table is:
 
-   NAME		OPCODE		MASK	     FLAGS	ANTI		{OPERANDS}
+   NAME		OPCODE		MASK	     FLAGS	ANTI	DEPRECATED	{OPERANDS}
 
    NAME is the name of the instruction.
    OPCODE is the instruction opcode.
@@ -2036,6 +2670,8 @@ extract_dm (unsigned long insn,
      which bits in the actual opcode must match OPCODE.
    FLAGS are flags indicating which processors support the instruction.
    ANTI indicates which processors don't support the instruction.
+   DEPRECATED are flags that indicate what processors no longer
+     support the instruction.
    OPERANDS is the list of operands.
 
    The disassembler reads the table in order and prints the first
@@ -2047,7 +2683,36 @@ extract_dm (unsigned long insn,
    constrained otherwise by disassembler operation.  */
 
 const struct powerpc_opcode powerpc_opcodes[] = {
+
+{"se_illegal",	C(0),		C_MASK,		PPCVLE,	PPCNONE,	{}},
+{"se_isync",	C(1),		C_MASK,		PPCVLE,	PPCNONE,	{}},
+{"se_sc",	C(2),		C_MASK,		PPCVLE,	PPCNONE,	{}},
+{"se_blr",	C_LK(2,0),	C_LK_MASK,	PPCVLE,	PPCNONE,	{}},
+{"se_blrl",	C_LK(2,1),	C_LK_MASK,	PPCVLE,	PPCNONE,	{}},
+{"se_bctr",	C_LK(3,0),	C_LK_MASK,	PPCVLE,	PPCNONE,	{}},
+{"se_bctrl",	C_LK(3,1),	C_LK_MASK,	PPCVLE,	PPCNONE,	{}},
+{"se_rfi",	C(8),		C_MASK,		PPCVLE,	PPCNONE,	{}},
+{"se_rfci",	C(9),		C_MASK,		PPCVLE,	PPCNONE,	{}},
+{"se_rfdi",	C(10),		C_MASK,		PPCVLE,	PPCNONE,	{}},
+{"se_rfmci",	C(11),		C_MASK,		PPCVLE,	PPCNONE,	{}},
+{"se_not",	SE_R(0,2),	SE_R_MASK,	PPCVLE,	PPCNONE,	{RX}},
+{"se_neg",	SE_R(0,3),	SE_R_MASK,	PPCVLE,	PPCNONE,	{RX}},
+{"se_mflr",	SE_R(0,8),	SE_R_MASK,	PPCVLE,	PPCNONE,	{RX}},
+{"se_mtlr",	SE_R(0,9),	SE_R_MASK,	PPCVLE,	PPCNONE,	{RX}},
+{"se_mfctr",	SE_R(0,10),	SE_R_MASK,	PPCVLE,	PPCNONE,	{RX}},
+{"se_mtctr",	SE_R(0,11),	SE_R_MASK,	PPCVLE,	PPCNONE,	{RX}},
+{"se_extzb",	SE_R(0,12),	SE_R_MASK,	PPCVLE,	PPCNONE,	{RX}},
+{"se_extsb",	SE_R(0,13),	SE_R_MASK,	PPCVLE,	PPCNONE,	{RX}},
+{"se_extzh",	SE_R(0,14),	SE_R_MASK,	PPCVLE,	PPCNONE,	{RX}},
+{"se_extsh",	SE_R(0,15),	SE_R_MASK,	PPCVLE,	PPCNONE,	{RX}},
+{"se_mr",	SE_RR(0,1),	SE_RR_MASK,	PPCVLE,	PPCNONE,	{RX, RY}},
+{"se_mtar",	SE_RR(0,2),	SE_RR_MASK,	PPCVLE,	PPCNONE,	{ARX, RY}},
+{"se_mfar",	SE_RR(0,3),	SE_RR_MASK,	PPCVLE,	PPCNONE,	{RX, ARY}},
 {"attn",	X(0,256),	X_MASK,   POWER4|PPCA2,	PPC476,		{0}},
+{"se_add",	SE_RR(1,0),	SE_RR_MASK,	PPCVLE,	PPCNONE,	{RX, RY}},
+{"se_mullw",	SE_RR(1,1),	SE_RR_MASK,	PPCVLE,	PPCNONE,	{RX, RY}},
+{"se_sub",	SE_RR(1,2),	SE_RR_MASK,	PPCVLE,	PPCNONE,	{RX, RY}},
+{"se_subf",	SE_RR(1,3),	SE_RR_MASK,	PPCVLE,	PPCNONE,	{RX, RY}},
 {"tdlgti",	OPTO(2,TOLGT),	OPTO_MASK,   PPC64,	PPCNONE,	{RA, SI}},
 {"tdllti",	OPTO(2,TOLLT),	OPTO_MASK,   PPC64,	PPCNONE,	{RA, SI}},
 {"tdeqi",	OPTO(2,TOEQ),	OPTO_MASK,   PPC64,	PPCNONE,	{RA, SI}},
@@ -2064,6 +2729,10 @@ const struct powerpc_opcode powerpc_opco
 {"tdnei",	OPTO(2,TONE),	OPTO_MASK,   PPC64,	PPCNONE,	{RA, SI}},
 {"tdi",		OP(2),		OP_MASK,     PPC64,	PPCNONE,	{TO, RA, SI}},
 
+{"se_cmp",	SE_RR(3,0),	SE_RR_MASK,  PPCVLE,	PPCNONE,	{RX, RY}},
+{"se_cmpl",	SE_RR(3,1),	SE_RR_MASK,  PPCVLE,	PPCNONE,	{RX, RY}},
+{"se_cmph",	SE_RR(3,2),	SE_RR_MASK,  PPCVLE,	PPCNONE,	{RX, RY}},
+{"se_cmphl",	SE_RR(3,3),	SE_RR_MASK,  PPCVLE,	PPCNONE,	{RX, RY}},
 {"twlgti",	OPTO(3,TOLGT),	OPTO_MASK,   PPCCOM,	PPCNONE,	{RA, SI}},
 {"tlgti",	OPTO(3,TOLGT),	OPTO_MASK,   PWRCOM,	PPCNONE,	{RA, SI}},
 {"twllti",	OPTO(3,TOLLT),	OPTO_MASK,   PPCCOM,	PPCNONE,	{RA, SI}},
@@ -2688,32 +3357,82 @@ const struct powerpc_opcode powerpc_opco
 {"nmaclhwso.",	XO (4, 494,1,1),XO_MASK,     MULHW,	PPCNONE,	{RT, RA, RB}},
 {"dcbz_l",	X  (4,1014),	XRT_MASK,    PPCPS,	PPCNONE,	{RA, RB}},
 
+{"e_cmpi",	SCI8BF(6,0,21),	SCI8BF_MASK,	PPCVLE,	PPCNONE,	{CRD32, RA, SCLSCI8}},
+#if 0
+{"e_cmpwi",	SCI8BF(6,0,21),	SCI8BF_MASK,	PPCVLE,	PPCNONE,	{CRD32, RA, SCLSCI8}},
+#endif
+{"e_cmpli",	SCI8BF(6,1,21),	SCI8BF_MASK,	PPCVLE,	PPCNONE,	{CRD32, RA, SCLSCI8}},
+#if 0
+{"e_cmplwi",	SCI8BF(6,1,21),	SCI8BF_MASK,	PPCVLE,	PPCNONE,	{CRD32, RA, SCLSCI8}},
+#endif
+{"e_addi",	SCI8(6,16),	SCI8_MASK,	PPCVLE,	PPCNONE,	{RT, RA, SCLSCI8}},
+{"e_subi",	SCI8(6,16),	SCI8_MASK,	PPCVLE,	PPCNONE,	{RT, RA, SCLSCI8N}},
+{"e_addi.",	SCI8(6,17),	SCI8_MASK,	PPCVLE,	PPCNONE,	{RT, RA, SCLSCI8}},
+{"e_addic",	SCI8(6,18),	SCI8_MASK,	PPCVLE,	PPCNONE,	{RT, RA, SCLSCI8}},
+{"e_subic",	SCI8(6,18),	SCI8_MASK,	PPCVLE,	PPCNONE,	{RT, RA, SCLSCI8N}},
+{"e_addic.",	SCI8(6,19),	SCI8_MASK,	PPCVLE,	PPCNONE,	{RT, RA, SCLSCI8}},
+{"e_subic.",	SCI8(6,19),	SCI8_MASK,	PPCVLE,	PPCNONE,	{RT, RA, SCLSCI8N}},
+{"e_mulli",	SCI8(6,20),	SCI8_MASK,	PPCVLE,	PPCNONE,	{RT, RA, SCLSCI8}},
+{"e_subfic",	SCI8(6,22),	SCI8_MASK,	PPCVLE,	PPCNONE,	{RT, RA, SCLSCI8}},
+{"e_subfic.",	SCI8(6,23),	SCI8_MASK,	PPCVLE,	PPCNONE,	{RT, RA, SCLSCI8}},
+{"e_andi",	SCI8(6,24),	SCI8_MASK,	PPCVLE,	PPCNONE,	{RA, RS, SCLSCI8}},
+{"e_andi.",	SCI8(6,25),	SCI8_MASK,	PPCVLE,	PPCNONE,	{RA, RS, SCLSCI8}},
+{"e_nop",	SCI8(6,26),	0xffffffff,	PPCVLE,	PPCNONE,	{0}},
+{"e_ori",	SCI8(6,26),	SCI8_MASK,	PPCVLE,	PPCNONE,	{RA, RS, SCLSCI8}},
+{"e_ori.",	SCI8(6,27),	SCI8_MASK,	PPCVLE,	PPCNONE,	{RA, RS, SCLSCI8}},
+{"e_xori",	SCI8(6,28),	SCI8_MASK,	PPCVLE,	PPCNONE,	{RA, RS, SCLSCI8}},
+{"e_xori.",	SCI8(6,29),	SCI8_MASK,	PPCVLE,	PPCNONE,	{RA, RS, SCLSCI8}},
+{"e_lbzu",	OPVUP(6,0),	OPVUP_MASK,	PPCVLE,	PPCNONE,	{RT, D8, RA0}},
+{"e_lhau",	OPVUP(6,3),	OPVUP_MASK,	PPCVLE,	PPCNONE,	{RT, D8, RA0}},
+{"e_lhzu",	OPVUP(6,1),	OPVUP_MASK,	PPCVLE,	PPCNONE,	{RT, D8, RA0}},
+{"e_lmw",	OPVUP(6,8),	OPVUP_MASK,	PPCVLE,	PPCNONE,	{RT, D8, RA0}},
+{"e_lwzu",	OPVUP(6,2),	OPVUP_MASK,	PPCVLE,	PPCNONE,	{RT, D8, RA0}},
+{"e_stbu",	OPVUP(6,4),	OPVUP_MASK,	PPCVLE,	PPCNONE,	{RT, D8, RA0}},
+{"e_sthu",	OPVUP(6,5),	OPVUP_MASK,	PPCVLE,	PPCNONE,	{RT, D8, RA0}},
+{"e_stwu",	OPVUP(6,6),	OPVUP_MASK,	PPCVLE,	PPCNONE,	{RT, D8, RA0}},
+{"e_stmw",	OPVUP(6,9),	OPVUP_MASK,	PPCVLE,	PPCNONE,	{RT, D8, RA0}},
+{"e_add16i",	OP(7),		OP_MASK,	PPCVLE,	PPCNONE,	{RT, RA, SI}},
+{"e_la",	OP(7),		OP_MASK,    	PPCVLE,	PPCNONE,	{RT, D, RA0}},
+{"e_sub16i",	OP(7),		OP_MASK,	PPCVLE,	PPCNONE,	{RT, RA, NSI}},
+
 {"mulli",	OP(7),		OP_MASK,     PPCCOM,	PPCNONE,	{RT, RA, SI}},
 {"muli",	OP(7),		OP_MASK,     PWRCOM,	PPCNONE,	{RT, RA, SI}},
 
+{"se_addi",	SE_IM5(8,0),	SE_IM5_MASK,	PPCVLE,	PPCNONE,	{RX, OIMM5}},
+{"se_cmpli",	SE_IM5(8,1),	SE_IM5_MASK,	PPCVLE,	PPCNONE,	{RX, OIMM5}},
+
 {"subfic",	OP(8),		OP_MASK,     PPCCOM,	PPCNONE,	{RT, RA, SI}},
 {"sfi",		OP(8),		OP_MASK,     PWRCOM,	PPCNONE,	{RT, RA, SI}},
 
+{"se_subi",	SE_IM5(9,0),	SE_IM5_MASK,	PPCVLE,	PPCNONE,	{RX, OIMM5}},
+{"se_subi.",	SE_IM5(9,1),	SE_IM5_MASK,	PPCVLE,	PPCNONE,	{RX, OIMM5}},
 {"dozi",	OP(9),		OP_MASK,     M601,	PPCNONE,	{RT, RA, SI}},
 
 {"cmplwi",	OPL(10,0),	OPL_MASK,    PPCCOM,	PPCNONE,	{OBF, RA, UI}},
+{"se_cmpi",	SE_IM5(10,1),	SE_IM5_MASK,	PPCVLE,	PPCNONE,	{RX, UI5}},
 {"cmpldi",	OPL(10,1),	OPL_MASK,    PPC64,	PPCNONE,	{OBF, RA, UI}},
 {"cmpli",	OP(10),		OP_MASK,     PPC,	PPCNONE,	{BF, L, RA, UI}},
 {"cmpli",	OP(10),		OP_MASK,     PWRCOM,	PPC,		{BF, RA, UI}},
 
-{"cmpwi",	OPL(11,0),	OPL_MASK,    PPCCOM,	PPCNONE,	{OBF, RA, SI}},
+{"se_bmaski",	SE_IM5(11,0),	SE_IM5_MASK,	PPCVLE,	PPCNONE,	{RX, UI5}},
+{"se_andi",	SE_IM5(11,1),	SE_IM5_MASK,	PPCVLE,	PPCNONE,	{RX, UI5}},
+{"cmpwi",	OPL(11,0),	OPL_MASK, PPCCOM|PPCVLE, PPCNONE,	{OBF, RA, SI}},
 {"cmpdi",	OPL(11,1),	OPL_MASK,    PPC64,	PPCNONE,	{OBF, RA, SI}},
 {"cmpi",	OP(11),		OP_MASK,     PPC,	PPCNONE,	{BF, L, RA, SI}},
 {"cmpi",	OP(11),		OP_MASK,     PWRCOM,	PPC,		{BF, RA, SI}},
 
+{"e_lbz",	OP(12),		OP_MASK,	PPCVLE,	PPCNONE,	{RT, D, RA0}},
 {"addic",	OP(12),		OP_MASK,     PPCCOM,	PPCNONE,	{RT, RA, SI}},
 {"ai",		OP(12),		OP_MASK,     PWRCOM,	PPCNONE,	{RT, RA, SI}},
 {"subic",	OP(12),		OP_MASK,     PPCCOM,	PPCNONE,	{RT, RA, NSI}},
 
+{"e_stb",	OP(13),		OP_MASK,	PPCVLE,	PPCNONE,	{RT, D, RA0}},
+
 {"addic.",	OP(13),		OP_MASK,     PPCCOM,	PPCNONE,	{RT, RA, SI}},
 {"ai.",		OP(13),		OP_MASK,     PWRCOM,	PPCNONE,	{RT, RA, SI}},
 {"subic.",	OP(13),		OP_MASK,     PPCCOM,	PPCNONE,	{RT, RA, NSI}},
 
+{"e_lha",	OP(14),		OP_MASK,	PPCVLE,	PPCNONE,	{RT, D, RA0}},
 {"li",		OP(14),		DRA_MASK,    PPCCOM,	PPCNONE,	{RT, SI}},
 {"lil",		OP(14),		DRA_MASK,    PWRCOM,	PPCNONE,	{RT, SI}},
 {"addi",	OP(14),		OP_MASK,     PPCCOM,	PPCNONE,	{RT, RA0, SI}},
@@ -2721,12 +3440,16 @@ const struct powerpc_opcode powerpc_opco
 {"subi",	OP(14),		OP_MASK,     PPCCOM,	PPCNONE,	{RT, RA0, NSI}},
 {"la",		OP(14),		OP_MASK,     PPCCOM,	PPCNONE,	{RT, D, RA0}},
 
+
 {"lis",		OP(15),		DRA_MASK,    PPCCOM,	PPCNONE,	{RT, SISIGNOPT}},
 {"liu",		OP(15),		DRA_MASK,    PWRCOM,	PPCNONE,	{RT, SISIGNOPT}},
 {"addis",	OP(15),		OP_MASK,     PPCCOM,	PPCNONE,	{RT, RA0, SISIGNOPT}},
 {"cau",		OP(15),		OP_MASK,     PWRCOM,	PPCNONE,	{RT, RA0, SISIGNOPT}},
 {"subis",	OP(15),		OP_MASK,     PPCCOM,	PPCNONE,	{RT, RA0, NSI}},
 
+{"se_srw",	SE_RR(16,0),	SE_RR_MASK,	PPCVLE,	PPCNONE,	{RX, RY}},
+{"se_sraw",	SE_RR(16,1),	SE_RR_MASK,	PPCVLE,	PPCNONE,	{RX, RY}},
+{"se_slw",	SE_RR(16,2),	SE_RR_MASK,	PPCVLE,	PPCNONE,	{RX, RY}},
 {"bdnz-",    BBO(16,BODNZ,0,0),		BBOATBI_MASK,  PPCCOM,	 PPCNONE,	{BDM}},
 {"bdnz+",    BBO(16,BODNZ,0,0),		BBOATBI_MASK,  PPCCOM,	 PPCNONE,	{BDP}},
 {"bdnz",     BBO(16,BODNZ,0,0),		BBOATBI_MASK,  PPCCOM,	 PPCNONE,	{BD}},
@@ -2999,11 +3722,17 @@ const struct powerpc_opcode powerpc_opco
 {"bcla+",	B(16,1,1),	B_MASK,      PPCCOM,	PPCNONE,	{BOE, BI, BDPA}},
 {"bcla",	B(16,1,1),	B_MASK,      COM,	PPCNONE,	{BO, BI, BDA}},
 
+{"se_nop",	SE_RR(17,0),	0xffff,		PPCVLE,	PPCNONE,	{0}},
+{"se_or",	SE_RR(17,0),	SE_RR_MASK,	PPCVLE,	PPCNONE,	{RX, RY}},
+{"se_andc",	SE_RR(17,1),	SE_RR_MASK,	PPCVLE,	PPCNONE,	{RX, RY}},
+{"se_and",	SE_RR(17,2),	SE_RR_MASK,	PPCVLE,	PPCNONE,	{RX, RY}},
+{"se_and.",	SE_RR(17,3),	SE_RR_MASK,	PPCVLE,	PPCNONE,	{RX, RY}},
 {"svc",		SC(17,0,0),	SC_MASK,     POWER,	PPCNONE,	{SVC_LEV, FL1, FL2}},
 {"svcl",	SC(17,0,1),	SC_MASK,     POWER,	PPCNONE,	{SVC_LEV, FL1, FL2}},
 {"sc",		SC(17,1,0),	SC_MASK,     PPC,	PPCNONE,	{LEV}},
 {"svca",	SC(17,1,0),	SC_MASK,     PWRCOM,	PPCNONE,	{SV}},
 {"svcla",	SC(17,1,1),	SC_MASK,     POWER,	PPCNONE,	{SV}},
+{"se_li",	IM7(9),		IM7_MASK,	PPCVLE,	PPCNONE,	{RX, UI7}},
 
 {"b",		B(18,0,0),	B_MASK,      COM,	PPCNONE,	{LI}},
 {"bl",		B(18,0,1),	B_MASK,      COM,	PPCNONE,	{LI}},
@@ -3435,12 +4164,15 @@ const struct powerpc_opcode powerpc_opco
 {"bcctrl",  XLLK(19,528,1),		XLBH_MASK,     PPCCOM,	 PPCNONE,	{BO, BI, BH}},
 {"bccl",    XLLK(19,528,1),		XLBB_MASK,     PWRCOM,	 PPCNONE,	{BO, BI}},
 
+{"e_lwz",	OP(20),		OP_MASK,	PPCVLE,	PPCNONE,	{RT, D, RA0}},
 {"rlwimi",	M(20,0),	M_MASK,      PPCCOM,	PPCNONE,	{RA, RS, SH, MBE, ME}},
 {"rlimi",	M(20,0),	M_MASK,      PWRCOM,	PPCNONE,	{RA, RS, SH, MBE, ME}},
 
 {"rlwimi.",	M(20,1),	M_MASK,      PPCCOM,	PPCNONE,	{RA, RS, SH, MBE, ME}},
 {"rlimi.",	M(20,1),	M_MASK,      PWRCOM,	PPCNONE,	{RA, RS, SH, MBE, ME}},
 
+{"e_stw",	OP(21),		OP_MASK,	PPCVLE,	PPCNONE,	{RT, D, RA0}},
+
 {"rotlwi",	MME(21,31,0),	MMBME_MASK,  PPCCOM,	PPCNONE,	{RA, RS, SH}},
 {"clrlwi",	MME(21,31,0),	MSHME_MASK,  PPCCOM,	PPCNONE,	{RA, RS, MB}},
 {"rlwinm",	M(21,0),	M_MASK,      PPCCOM,	PPCNONE,	{RA, RS, SH, MBE, ME}},
@@ -3450,9 +4182,13 @@ const struct powerpc_opcode powerpc_opco
 {"rlwinm.",	M(21,1),	M_MASK,      PPCCOM,	PPCNONE,	{RA, RS, SH, MBE, ME}},
 {"rlinm.",	M(21,1),	M_MASK,      PWRCOM,	PPCNONE,	{RA, RS, SH, MBE, ME}},
 
+{"e_lhz",	OP(22),		OP_MASK,	PPCVLE,	PPCNONE,	{RT, D, RA0}},
+
 {"rlmi",	M(22,0),	M_MASK,      M601,	PPCNONE,	{RA, RS, RB, MBE, ME}},
 {"rlmi.",	M(22,1),	M_MASK,      M601,	PPCNONE,	{RA, RS, RB, MBE, ME}},
 
+{"e_sth",	OP(23),		OP_MASK,	PPCVLE,	PPCNONE,	{RT, D, RA0}},
+
 {"rotlw",	MME(23,31,0),	MMBME_MASK,  PPCCOM,	PPCNONE,	{RA, RS, RB}},
 {"rlwnm",	M(23,0),	M_MASK,      PPCCOM,	PPCNONE,	{RA, RS, RB, MBE, ME}},
 {"rlnm",	M(23,0),	M_MASK,      PWRCOM,	PPCNONE,	{RA, RS, RB, MBE, ME}},
@@ -3460,25 +4196,95 @@ const struct powerpc_opcode powerpc_opco
 {"rlwnm.",	M(23,1),	M_MASK,      PPCCOM,	PPCNONE,	{RA, RS, RB, MBE, ME}},
 {"rlnm.",	M(23,1),	M_MASK,      PWRCOM,	PPCNONE,	{RA, RS, RB, MBE, ME}},
 
+{"se_bclri",	SE_IM5(24,0),	SE_IM5_MASK,	PPCVLE,	PPCNONE,	{RX, UI5}},
+{"se_bgeni",	SE_IM5(24,1),	SE_IM5_MASK,	PPCVLE,	PPCNONE,	{RX, UI5}},
 {"nop",		OP(24),		0xffffffff,  PPCCOM,	PPCNONE,	{0}},
 {"ori",		OP(24),		OP_MASK,     PPCCOM,	PPCNONE,	{RA, RS, UI}},
 {"oril",	OP(24),		OP_MASK,     PWRCOM,	PPCNONE,	{RA, RS, UI}},
 
+{"se_bseti",	SE_IM5(25,0),	SE_IM5_MASK,	PPCVLE,	PPCNONE,	{RX, UI5}},
+{"se_btsti",	SE_IM5(25,1),	SE_IM5_MASK,	PPCVLE,	PPCNONE,	{RX, UI5}},
 {"oris",	OP(25),		OP_MASK,     PPCCOM,	PPCNONE,	{RA, RS, UI}},
 {"oriu",	OP(25),		OP_MASK,     PWRCOM,	PPCNONE,	{RA, RS, UI}},
 
+{"se_srwi",	SE_IM5(26,0),	SE_IM5_MASK,	PPCVLE,	PPCNONE,	{RX, UI5}},
+{"se_srawi",	SE_IM5(26,1),	SE_IM5_MASK,	PPCVLE,	PPCNONE,	{RX, UI5}},
 {"xori",	OP(26),		OP_MASK,     PPCCOM,	PPCNONE,	{RA, RS, UI}},
 {"xoril",	OP(26),		OP_MASK,     PWRCOM,	PPCNONE,	{RA, RS, UI}},
 
+{"se_slwi",	SE_IM5(27,0),	SE_IM5_MASK,	PPCVLE,	PPCNONE,	{RX, UI5}},
 {"xoris",	OP(27),		OP_MASK,     PPCCOM,	PPCNONE,	{RA, RS, UI}},
 {"xoriu",	OP(27),		OP_MASK,     PWRCOM,	PPCNONE,	{RA, RS, UI}},
 
+
+{"e_lis",	I16L(28,28),	I16L_MASK,	PPCVLE,	PPCNONE,	{RD, VLEUIMML}},
+{"e_and2is.",	I16L(28,29),	I16L_MASK,	PPCVLE,	PPCNONE,	{RD, VLEUIMML}},
+{"e_or2is",	I16L(28,26),	I16L_MASK,	PPCVLE,	PPCNONE,	{RD, VLEUIMML}},
+{"e_and2i.",	I16L(28,25),	I16L_MASK,	PPCVLE,	PPCNONE,	{RD, VLEUIMML}},
+{"e_or2i",	I16L(28,24),	I16L_MASK,	PPCVLE,	PPCNONE,	{RD, VLEUIMML}},
+{"e_cmphl16i",	IA16(28,23),	IA16_MASK,	PPCVLE,	PPCNONE,	{RA, VLEUIMM}},
+{"e_cmph16i",	IA16(28,22),	IA16_MASK,	PPCVLE,	PPCNONE,	{RA, VLESIMM}},
+{"e_cmpl16i",	I16A(28,21),	I16A_MASK,	PPCVLE,	PPCNONE,	{RA, VLEUIMM}},
+{"e_cmplwi",	I16A(28,21),	I16A_MASK,	PPCVLE,	PPCNONE,	{RA, VLESIMM}},
+{"e_mull2i",	I16A(28,20),	I16A_MASK,	PPCVLE,	PPCNONE,	{RA, VLESIMM}},
+{"e_cmp16i",	IA16(28,19),	IA16_MASK,	PPCVLE,	PPCNONE,	{RA, VLESIMM}},
+{"e_cmpwi",	IA16(28,19),	IA16_MASK,	PPCVLE,	PPCNONE,	{RA, VLESIMM}},
+{"e_sub2is",	I16A(28,18),	I16A_MASK,	PPCVLE,	PPCNONE,	{RA, VLENSIMM}},
+{"e_add2is",	I16A(28,18),	I16A_MASK,	PPCVLE,	PPCNONE,	{RA, VLESIMM}},
+{"e_sub2i.",	I16A(28,17),	I16A_MASK,	PPCVLE,	PPCNONE,	{RA, VLENSIMM}},
+{"e_add2i.",	I16A(28,17),	I16A_MASK,	PPCVLE,	PPCNONE,	{RA, VLESIMM}},
+{"e_li",	LI20(28,0),	LI20_MASK,	PPCVLE,	PPCNONE,	{RT, IMM20}},
+
 {"andi.",	OP(28),		OP_MASK,     PPCCOM,	PPCNONE,	{RA, RS, UI}},
 {"andil.",	OP(28),		OP_MASK,     PWRCOM,	PPCNONE,	{RA, RS, UI}},
 
+{"e_rlwimi",	M(29,0),	M_MASK,	     PPCVLE,	PPCNONE,	{RA, RS, SH, MB, ME}},
+{"e_rlwinm",	M(29,1),	M_MASK,	     PPCVLE,	PPCNONE,	{RA, RT, SH, MBE, ME}},
+
 {"andis.",	OP(29),		OP_MASK,     PPCCOM,	PPCNONE,	{RA, RS, UI}},
 {"andiu.",	OP(29),		OP_MASK,     PWRCOM,	PPCNONE,	{RA, RS, UI}},
 
+{"e_b",		BD24(30,0,0),	BD24_MASK,	PPCVLE,	PPCNONE,	{B24}},
+{"e_bl",	BD24(30,0,1),	BD24_MASK,	PPCVLE,	PPCNONE,	{B24}},
+
+{"e_bdnz",	EBD15(30,8,BO32DNZ,0),	EBD15_MASK,	PPCVLE,	PPCNONE,	{B15}},
+{"e_bdnzl",	EBD15(30,8,BO32DNZ,1),	EBD15_MASK,	PPCVLE,	PPCNONE,	{B15}},
+{"e_bdz",	EBD15(30,8,BO32DZ,0),	EBD15_MASK,	PPCVLE,	PPCNONE,	{B15}},
+{"e_bdzl",	EBD15(30,8,BO32DZ,1),	EBD15_MASK,	PPCVLE,	PPCNONE,	{B15}},
+
+{"e_bge",	EBD15BI(30,8,BO32F,CBLT,0),	EBD15BI_MASK,	PPCVLE,	PPCNONE,	{CRS,B15}},
+{"e_bgel",	EBD15BI(30,8,BO32F,CBLT,1),	EBD15BI_MASK,	PPCVLE,	PPCNONE,	{CRS,B15}},
+{"e_bnl",	EBD15BI(30,8,BO32F,CBLT,0),	EBD15BI_MASK,	PPCVLE,	PPCNONE,	{CRS,B15}},
+{"e_bnll",	EBD15BI(30,8,BO32F,CBLT,1),	EBD15BI_MASK,	PPCVLE,	PPCNONE,	{CRS,B15}},
+{"e_blt",	EBD15BI(30,8,BO32T,CBLT,0),	EBD15BI_MASK,	PPCVLE,	PPCNONE,	{CRS,B15}},
+{"e_bltl",	EBD15BI(30,8,BO32T,CBLT,1),	EBD15BI_MASK,	PPCVLE,	PPCNONE,	{CRS,B15}},
+{"e_bgt",	EBD15BI(30,8,BO32T,CBGT,0),	EBD15BI_MASK,	PPCVLE,	PPCNONE,	{CRS,B15}},
+{"e_bgtl",	EBD15BI(30,8,BO32T,CBGT,1),	EBD15BI_MASK,	PPCVLE,	PPCNONE,	{CRS,B15}},
+{"e_ble",	EBD15BI(30,8,BO32F,CBGT,0),	EBD15BI_MASK,	PPCVLE,	PPCNONE,	{CRS,B15}},
+{"e_blel",	EBD15BI(30,8,BO32F,CBGT,1),	EBD15BI_MASK,	PPCVLE,	PPCNONE,	{CRS,B15}},
+{"e_bng",	EBD15BI(30,8,BO32F,CBGT,0),	EBD15BI_MASK,	PPCVLE,	PPCNONE,	{CRS,B15}},
+{"e_bngl",	EBD15BI(30,8,BO32F,CBGT,1),	EBD15BI_MASK,	PPCVLE,	PPCNONE,	{CRS,B15}},
+{"e_bne",	EBD15BI(30,8,BO32F,CBEQ,0),	EBD15BI_MASK,	PPCVLE,	PPCNONE,	{CRS,B15}},
+{"e_bnel",	EBD15BI(30,8,BO32F,CBEQ,1),	EBD15BI_MASK,	PPCVLE,	PPCNONE,	{CRS,B15}},
+{"e_beq",	EBD15BI(30,8,BO32T,CBEQ,0),	EBD15BI_MASK,	PPCVLE,	PPCNONE,	{CRS,B15}},
+{"e_beql",	EBD15BI(30,8,BO32T,CBEQ,1),	EBD15BI_MASK,	PPCVLE,	PPCNONE,	{CRS,B15}},
+{"e_bso",	EBD15BI(30,8,BO32T,CBSO,0),	EBD15BI_MASK,	PPCVLE,	PPCNONE,	{CRS,B15}},
+{"e_bsol",	EBD15BI(30,8,BO32T,CBSO,1),	EBD15BI_MASK,	PPCVLE,	PPCNONE,	{CRS,B15}},
+{"e_bun",	EBD15BI(30,8,BO32T,CBSO,0),	EBD15BI_MASK,	PPCVLE,	PPCNONE,	{CRS,B15}},
+{"e_bunl",	EBD15BI(30,8,BO32T,CBSO,1),	EBD15BI_MASK,	PPCVLE,	PPCNONE,	{CRS,B15}},
+{"e_bns",	EBD15BI(30,8,BO32F,CBSO,0),	EBD15BI_MASK,	PPCVLE,	PPCNONE,	{CRS,B15}},
+{"e_bnsl",	EBD15BI(30,8,BO32F,CBSO,1),	EBD15BI_MASK,	PPCVLE,	PPCNONE,	{CRS,B15}},
+{"e_bnu",	EBD15BI(30,8,BO32F,CBSO,0),	EBD15BI_MASK,	PPCVLE,	PPCNONE,	{CRS,B15}},
+{"e_bnul",	EBD15BI(30,8,BO32F,CBSO,1),	EBD15BI_MASK,	PPCVLE,	PPCNONE,	{CRS,B15}},
+
+{"e_bc",	BD15(30,8,0),	BD15_MASK,	PPCVLE,	PPCNONE,	{BO32, BI32, B15}},
+{"e_bcl",	BD15(30,8,1),	BD15_MASK,	PPCVLE,	PPCNONE,	{BO32, BI32, B15}},
+
+{"e_bf",	EBD15(30,8,BO32F,0),	EBD15_MASK,	PPCVLE,	PPCNONE,	{BI32,B15}},
+{"e_bfl",	EBD15(30,8,BO32F,1),	EBD15_MASK,	PPCVLE,	PPCNONE,	{BI32,B15}},
+{"e_bt",	EBD15(30,8,BO32T,0),	EBD15_MASK,	PPCVLE,	PPCNONE,	{BI32,B15}},
+{"e_btl",	EBD15(30,8,BO32T,1),	EBD15_MASK,	PPCVLE,	PPCNONE,	{BI32,B15}},
+
 {"rotldi",	MD(30,0,0),	MDMB_MASK,   PPC64,	PPCNONE,	{RA, RS, SH6}},
 {"clrldi",	MD(30,0,0),	MDSH_MASK,   PPC64,	PPCNONE,	{RA, RS, MB6}},
 {"rldicl",	MD(30,0,0),	MD_MASK,     PPC64,	PPCNONE,	{RA, RS, SH6, MB6}},
@@ -3503,64 +4309,88 @@ const struct powerpc_opcode powerpc_opco
 {"rldcr",	MDS(30,9,0),	MDS_MASK,    PPC64,	PPCNONE,	{RA, RS, RB, ME6}},
 {"rldcr.",	MDS(30,9,1),	MDS_MASK,    PPC64,	PPCNONE,	{RA, RS, RB, ME6}},
 
-{"cmpw",	XOPL(31,0,0),	XCMPL_MASK,  PPCCOM,	PPCNONE,	{OBF, RA, RB}},
+{"cmpw",	XOPL(31,0,0),	XCMPL_MASK, PPCCOM|PPCVLE, PPCNONE,	{OBF, RA, RB}},
 {"cmpd",	XOPL(31,0,1),	XCMPL_MASK,  PPC64,	PPCNONE,	{OBF, RA, RB}},
-{"cmp",		X(31,0),	XCMP_MASK,   PPC,	PPCNONE,	{BF, L, RA, RB}},
+{"cmp",		X(31,0),	XCMP_MASK, PPC|PPCVLE,	PPCNONE,	{BF, L, RA, RB}},
 {"cmp",		X(31,0),	XCMPL_MASK,  PWRCOM,	PPC,		{BF, RA, RB}},
 
-{"twlgt",	XTO(31,4,TOLGT), XTO_MASK,   PPCCOM,	PPCNONE,	{RA, RB}},
+{"e_cmph",	X(31,14),	X_MASK,		PPCVLE,	PPCNONE,	{CRD, RA, RB}},
+{"e_cmphl",	X(31,46),	X_MASK,		PPCVLE,	PPCNONE,	{CRD, RA, RB}},
+{"e_crand",	XL(31,257),	XL_MASK,	PPCVLE,	PPCNONE,	{BT, BA, BB}},
+{"e_crandc",	XL(31,129),	XL_MASK,	PPCVLE,	PPCNONE,	{BT, BA, BB}},
+{"e_crset",	XL(31,289),	XL_MASK,	PPCVLE,	PPCNONE,	{BT, BAT, BBA}},
+{"e_creqv",	XL(31,289),	XL_MASK,	PPCVLE,	PPCNONE,	{BT, BA, BB}},
+{"e_crnand",	XL(31,225),	XL_MASK,	PPCVLE,	PPCNONE,	{BT, BA, BB}},
+{"e_crnot",	XL(31,33),	XL_MASK,	PPCVLE,	PPCNONE,	{BT, BA, BBA}},
+{"e_crnor",	XL(31,33),	XL_MASK,	PPCVLE,	PPCNONE,	{BT, BA, BB}},
+{"e_crmove",	XL(31,449),	XL_MASK,	PPCVLE,	PPCNONE,	{BT, BA, BBA}},
+{"e_cror",	XL(31,449),	XL_MASK,	PPCVLE,	PPCNONE,	{BT, BA, BB}},
+{"e_crorc",	XL(31,417),	XL_MASK,	PPCVLE,	PPCNONE,	{BT, BA, BB}},
+{"e_crclr",	XL(31,193),	XL_MASK,	PPCVLE,	PPCNONE,	{BT, BAT, BBA}},
+{"e_crxor",	XL(31,193),	XL_MASK,	PPCVLE,	PPCNONE,	{BT, BA, BB}},
+{"e_mcrf",	XL(31,16),	XL_MASK,	PPCVLE,	PPCNONE,	{CRD, CR}},
+{"e_rlw",	EX(31,560),	EX_MASK,	PPCVLE,	PPCNONE,	{RA, RS, RB}},
+{"e_rlw.",	EX(31,561),	EX_MASK,	PPCVLE,	PPCNONE,	{RA, RS, RB}},
+{"e_rlwi",	EX(31,624),	EX_MASK,	PPCVLE,	PPCNONE,	{RA, RS, SH}},
+{"e_rlwi.",	EX(31,625),	EX_MASK,	PPCVLE,	PPCNONE,	{RA, RS, SH}},
+{"e_slwi",	EX(31,112),	EX_MASK,	PPCVLE,	PPCNONE,	{RA, RS, SH}},
+{"e_slwi.",	EX(31,113),	EX_MASK,	PPCVLE,	PPCNONE,	{RA, RS, SH}},
+{"e_srwi",	EX(31,1136),	EX_MASK,	PPCVLE,	PPCNONE,	{RA, RS, SH}},
+{"e_srwi.",	EX(31,1137),	EX_MASK,	PPCVLE,	PPCNONE,	{RA, RS, SH}},
+
+{"twlgt",	XTO(31,4,TOLGT), XTO_MASK,   PPCCOM|PPCVLE,	PPCNONE,	{RA, RB}},
 {"tlgt",	XTO(31,4,TOLGT), XTO_MASK,   PWRCOM,	PPCNONE,	{RA, RB}},
-{"twllt",	XTO(31,4,TOLLT), XTO_MASK,   PPCCOM,	PPCNONE,	{RA, RB}},
+{"twllt",	XTO(31,4,TOLLT), XTO_MASK,   PPCCOM|PPCVLE,	PPCNONE,	{RA, RB}},
 {"tllt",	XTO(31,4,TOLLT), XTO_MASK,   PWRCOM,	PPCNONE,	{RA, RB}},
-{"tweq",	XTO(31,4,TOEQ),	 XTO_MASK,   PPCCOM,	PPCNONE,	{RA, RB}},
+{"tweq",	XTO(31,4,TOEQ),	 XTO_MASK,   PPCCOM|PPCVLE,	PPCNONE,	{RA, RB}},
 {"teq",		XTO(31,4,TOEQ),	 XTO_MASK,   PWRCOM,	PPCNONE,	{RA, RB}},
-{"twlge",	XTO(31,4,TOLGE), XTO_MASK,   PPCCOM,	PPCNONE,	{RA, RB}},
+{"twlge",	XTO(31,4,TOLGE), XTO_MASK,   PPCCOM|PPCVLE,	PPCNONE,	{RA, RB}},
 {"tlge",	XTO(31,4,TOLGE), XTO_MASK,   PWRCOM,	PPCNONE,	{RA, RB}},
-{"twlnl",	XTO(31,4,TOLNL), XTO_MASK,   PPCCOM,	PPCNONE,	{RA, RB}},
+{"twlnl",	XTO(31,4,TOLNL), XTO_MASK,   PPCCOM|PPCVLE,	PPCNONE,	{RA, RB}},
 {"tlnl",	XTO(31,4,TOLNL), XTO_MASK,   PWRCOM,	PPCNONE,	{RA, RB}},
-{"twlle",	XTO(31,4,TOLLE), XTO_MASK,   PPCCOM,	PPCNONE,	{RA, RB}},
+{"twlle",	XTO(31,4,TOLLE), XTO_MASK,   PPCCOM|PPCVLE,	PPCNONE,	{RA, RB}},
 {"tlle",	XTO(31,4,TOLLE), XTO_MASK,   PWRCOM,	PPCNONE,	{RA, RB}},
-{"twlng",	XTO(31,4,TOLNG), XTO_MASK,   PPCCOM,	PPCNONE,	{RA, RB}},
+{"twlng",	XTO(31,4,TOLNG), XTO_MASK,   PPCCOM|PPCVLE,	PPCNONE,	{RA, RB}},
 {"tlng",	XTO(31,4,TOLNG), XTO_MASK,   PWRCOM,	PPCNONE,	{RA, RB}},
-{"twgt",	XTO(31,4,TOGT),	 XTO_MASK,   PPCCOM,	PPCNONE,	{RA, RB}},
+{"twgt",	XTO(31,4,TOGT),	 XTO_MASK,   PPCCOM|PPCVLE,	PPCNONE,	{RA, RB}},
 {"tgt",		XTO(31,4,TOGT),	 XTO_MASK,   PWRCOM,	PPCNONE,	{RA, RB}},
-{"twge",	XTO(31,4,TOGE),	 XTO_MASK,   PPCCOM,	PPCNONE,	{RA, RB}},
+{"twge",	XTO(31,4,TOGE),	 XTO_MASK,   PPCCOM|PPCVLE,	PPCNONE,	{RA, RB}},
 {"tge",		XTO(31,4,TOGE),	 XTO_MASK,   PWRCOM,	PPCNONE,	{RA, RB}},
-{"twnl",	XTO(31,4,TONL),	 XTO_MASK,   PPCCOM,	PPCNONE,	{RA, RB}},
+{"twnl",	XTO(31,4,TONL),	 XTO_MASK,   PPCCOM|PPCVLE,	PPCNONE,	{RA, RB}},
 {"tnl",		XTO(31,4,TONL),	 XTO_MASK,   PWRCOM,	PPCNONE,	{RA, RB}},
-{"twlt",	XTO(31,4,TOLT),	 XTO_MASK,   PPCCOM,	PPCNONE,	{RA, RB}},
+{"twlt",	XTO(31,4,TOLT),	 XTO_MASK,   PPCCOM|PPCVLE,	PPCNONE,	{RA, RB}},
 {"tlt",		XTO(31,4,TOLT),	 XTO_MASK,   PWRCOM,	PPCNONE,	{RA, RB}},
-{"twle",	XTO(31,4,TOLE),	 XTO_MASK,   PPCCOM,	PPCNONE,	{RA, RB}},
+{"twle",	XTO(31,4,TOLE),	 XTO_MASK,   PPCCOM|PPCVLE,	PPCNONE,	{RA, RB}},
 {"tle",		XTO(31,4,TOLE),	 XTO_MASK,   PWRCOM,	PPCNONE,	{RA, RB}},
-{"twng",	XTO(31,4,TONG),	 XTO_MASK,   PPCCOM,	PPCNONE,	{RA, RB}},
+{"twng",	XTO(31,4,TONG),	 XTO_MASK,   PPCCOM|PPCVLE,	PPCNONE,	{RA, RB}},
 {"tng",		XTO(31,4,TONG),	 XTO_MASK,   PWRCOM,	PPCNONE,	{RA, RB}},
-{"twne",	XTO(31,4,TONE),	 XTO_MASK,   PPCCOM,	PPCNONE,	{RA, RB}},
+{"twne",	XTO(31,4,TONE),	 XTO_MASK,   PPCCOM|PPCVLE,	PPCNONE,	{RA, RB}},
 {"tne",		XTO(31,4,TONE),	 XTO_MASK,   PWRCOM,	PPCNONE,	{RA, RB}},
-{"trap",	XTO(31,4,TOU),	 0xffffffff, PPCCOM,	PPCNONE,	{0}},
-{"tw",		X(31,4),	 X_MASK,     PPCCOM,	PPCNONE,	{TO, RA, RB}},
+{"trap",	XTO(31,4,TOU),	 0xffffffff, PPCCOM|PPCVLE,	PPCNONE,	{0}},
+{"tw",		X(31,4),	 X_MASK, PPCCOM|PPCVLE,	PPCNONE,	{TO, RA, RB}},
 {"t",		X(31,4),	 X_MASK,     PWRCOM,	PPCNONE,	{TO, RA, RB}},
 
 {"lvsl",	X(31,6),	X_MASK,      PPCVEC,	PPCNONE,	{VD, RA, RB}},
 {"lvebx",	X(31,7),	X_MASK,      PPCVEC,	PPCNONE,	{VD, RA, RB}},
 {"lbfcmx",	APU(31,7,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
 
-{"subfc",	XO(31,8,0,0),	XO_MASK,     PPCCOM,	PPCNONE,	{RT, RA, RB}},
+{"subfc",	XO(31,8,0,0),	XO_MASK, PPCCOM|PPCVLE,	PPCNONE,	{RT, RA, RB}},
 {"sf",		XO(31,8,0,0),	XO_MASK,     PWRCOM,	PPCNONE,	{RT, RA, RB}},
-{"subc",	XO(31,8,0,0),	XO_MASK,     PPCCOM,	PPCNONE,	{RT, RB, RA}},
-{"subfc.",	XO(31,8,0,1),	XO_MASK,     PPCCOM,	PPCNONE,	{RT, RA, RB}},
+{"subc",	XO(31,8,0,0),	XO_MASK, PPCCOM|PPCVLE,	PPCNONE,	{RT, RB, RA}},
+{"subfc.",	XO(31,8,0,1),	XO_MASK, PPCCOM|PPCVLE,	PPCNONE,	{RT, RA, RB}},
 {"sf.",		XO(31,8,0,1),	XO_MASK,     PWRCOM,	PPCNONE,	{RT, RA, RB}},
-{"subc.",	XO(31,8,0,1),	XO_MASK,     PPCCOM,	PPCNONE,	{RT, RB, RA}},
+{"subc.",	XO(31,8,0,1),	XO_MASK, PPCCOM|PPCVLE,	PPCNONE,	{RT, RB, RA}},
 
-{"mulhdu",	XO(31,9,0,0),	XO_MASK,     PPC64,	PPCNONE,	{RT, RA, RB}},
-{"mulhdu.",	XO(31,9,0,1),	XO_MASK,     PPC64,	PPCNONE,	{RT, RA, RB}},
+{"mulhdu",	XO(31,9,0,0),	XO_MASK,  PPC64|PPCVLE,	PPCNONE,	{RT, RA, RB}},
+{"mulhdu.",	XO(31,9,0,1),	XO_MASK,  PPC64|PPCVLE,	PPCNONE,	{RT, RA, RB}},
 
-{"addc",	XO(31,10,0,0),	XO_MASK,     PPCCOM,	PPCNONE,	{RT, RA, RB}},
+{"addc",	XO(31,10,0,0),	XO_MASK,  PPCCOM|PPCVLE, PPCNONE,	{RT, RA, RB}},
 {"a",		XO(31,10,0,0),	XO_MASK,     PWRCOM,	PPCNONE,	{RT, RA, RB}},
-{"addc.",	XO(31,10,0,1),	XO_MASK,     PPCCOM,	PPCNONE,	{RT, RA, RB}},
+{"addc.",	XO(31,10,0,1),	XO_MASK,  PPCCOM|PPCVLE, PPCNONE,	{RT, RA, RB}},
 {"a.",		XO(31,10,0,1),	XO_MASK,     PWRCOM,	PPCNONE,	{RT, RA, RB}},
 
-{"mulhwu",	XO(31,11,0,0),	XO_MASK,     PPC,	PPCNONE,	{RT, RA, RB}},
-{"mulhwu.",	XO(31,11,0,1),	XO_MASK,     PPC,	PPCNONE,	{RT, RA, RB}},
+{"mulhwu",	XO(31,11,0,0),	XO_MASK,  PPC|PPCVLE,	PPCNONE,	{RT, RA, RB}},
+{"mulhwu.",	XO(31,11,0,1),	XO_MASK,  PPC|PPCVLE,	PPCNONE,	{RT, RA, RB}},
 
 {"isellt",	X(31,15),	X_MASK,      PPCISEL,	PPCNONE,	{RT, RA, RB}},
 
@@ -3570,43 +4400,43 @@ const struct powerpc_opcode powerpc_opco
 {"tlbilx",	X(31,18),	X_MASK,   E500MC|PPCA2,	PPCNONE,	{T, RA0, RB}},
 
 {"mfcr",	XFXM(31,19,0,0), XFXFXM_MASK, POWER4,	PPCNONE,	{RT, FXM4}},
-{"mfcr",	XFXM(31,19,0,0), XRARB_MASK, COM,	POWER4,		{RT}},
-{"mfocrf",	XFXM(31,19,0,1), XFXFXM_MASK, COM,	PPCNONE,	{RT, FXM}},
+{"mfcr",	XFXM(31,19,0,0), XRARB_MASK,  COM|PPCVLE,  POWER4,	{RT}},
+{"mfocrf",	XFXM(31,19,0,1), XFXFXM_MASK, COM|PPCVLE, PPCNONE,	{RT, FXM}},
 
-{"lwarx",	X(31,20),	XEH_MASK,    PPC,	PPCNONE,	{RT, RA0, RB, EH}},
+{"lwarx",	X(31,20),	XEH_MASK, PPC|PPCVLE,	PPCNONE,	{RT, RA0, RB, EH}},
 
-{"ldx",		X(31,21),	X_MASK,      PPC64,	PPCNONE,	{RT, RA0, RB}},
+{"ldx",		X(31,21),	X_MASK, PPC64|PPCVLE,	PPCNONE,	{RT, RA0, RB}},
 
-{"icbt",	X(31,22),	X_MASK, BOOKE|PPCE300|PPCA2|PPC476, PPCNONE, {CT, RA, RB}},
+{"icbt",	X(31,22),	X_MASK, BOOKE|PPCE300|PPCA2|PPC476|PPCVLE, PPCNONE, {CT, RA, RB}},
 
-{"lwzx",	X(31,23),	X_MASK,      PPCCOM,	PPCNONE,	{RT, RA0, RB}},
+{"lwzx",	X(31,23),	X_MASK,  PPCCOM|PPCVLE,	PPCNONE,	{RT, RA0, RB}},
 {"lx",		X(31,23),	X_MASK,      PWRCOM,	PPCNONE,	{RT, RA, RB}},
 
-{"slw",		XRC(31,24,0),	X_MASK,      PPCCOM,	PPCNONE,	{RA, RS, RB}},
+{"slw",		XRC(31,24,0),	X_MASK,  PPCCOM|PPCVLE,	PPCNONE,	{RA, RS, RB}},
 {"sl",		XRC(31,24,0),	X_MASK,      PWRCOM,	PPCNONE,	{RA, RS, RB}},
-{"slw.",	XRC(31,24,1),	X_MASK,      PPCCOM,	PPCNONE,	{RA, RS, RB}},
+{"slw.",	XRC(31,24,1),	X_MASK,  PPCCOM|PPCVLE,	PPCNONE,	{RA, RS, RB}},
 {"sl.",		XRC(31,24,1),	X_MASK,      PWRCOM,	PPCNONE,	{RA, RS, RB}},
 
-{"cntlzw",	XRC(31,26,0),	XRB_MASK,    PPCCOM,	PPCNONE,	{RA, RS}},
+{"cntlzw",	XRC(31,26,0),	XRB_MASK, PPCCOM|PPCVLE, PPCNONE,	{RA, RS}},
 {"cntlz",	XRC(31,26,0),	XRB_MASK,    PWRCOM,	PPCNONE,	{RA, RS}},
-{"cntlzw.",	XRC(31,26,1),	XRB_MASK,    PPCCOM,	PPCNONE,	{RA, RS}},
+{"cntlzw.",	XRC(31,26,1),	XRB_MASK, PPCCOM|PPCVLE, PPCNONE,	{RA, RS}},
 {"cntlz.",	XRC(31,26,1),	XRB_MASK,    PWRCOM,	PPCNONE,	{RA, RS}},
 
 {"sld",		XRC(31,27,0),	X_MASK,      PPC64,	PPCNONE,	{RA, RS, RB}},
 {"sld.",	XRC(31,27,1),	X_MASK,      PPC64,	PPCNONE,	{RA, RS, RB}},
 
-{"and",		XRC(31,28,0),	X_MASK,      COM,	PPCNONE,	{RA, RS, RB}},
-{"and.",	XRC(31,28,1),	X_MASK,      COM,	PPCNONE,	{RA, RS, RB}},
+{"and",		XRC(31,28,0),	X_MASK,   COM|PPCVLE,	PPCNONE,	{RA, RS, RB}},
+{"and.",	XRC(31,28,1),	X_MASK,   COM|PPCVLE,	PPCNONE,	{RA, RS, RB}},
 
 {"maskg",	XRC(31,29,0),	X_MASK,      M601,	PPCA2,		{RA, RS, RB}},
 {"maskg.",	XRC(31,29,1),	X_MASK,      M601,	PPCA2,		{RA, RS, RB}},
 
-{"ldepx",	X(31,29),	X_MASK,   E500MC|PPCA2,	PPCNONE,	{RT, RA, RB}},
-{"lwepx",	X(31,31),	X_MASK,   E500MC|PPCA2,	PPCNONE,	{RT, RA, RB}},
+{"ldepx",	X(31,29), X_MASK,  E500MC|PPCA2|PPCVLE,	PPCNONE,	{RT, RA, RB}},
+{"lwepx",	X(31,31), X_MASK,  E500MC|PPCA2|PPCVLE,	PPCNONE,	{RT, RA, RB}},
 
-{"cmplw",	XOPL(31,32,0),	XCMPL_MASK,  PPCCOM,	PPCNONE,	{OBF, RA, RB}},
+{"cmplw",	XOPL(31,32,0),	XCMPL_MASK, PPCCOM|PPCVLE, PPCNONE,	{OBF, RA, RB}},
 {"cmpld",	XOPL(31,32,1),	XCMPL_MASK,  PPC64,	PPCNONE,	{OBF, RA, RB}},
-{"cmpl",	X(31,32),	XCMP_MASK,   PPC,	PPCNONE,	{BF, L, RA, RB}},
+{"cmpl",	X(31,32),	XCMP_MASK, PPC|PPCVLE,	PPCNONE,	{BF, L, RA, RB}},
 {"cmpl",	X(31,32),	XCMPL_MASK,  PWRCOM,	PPC,		{BF, RA, RB}},
 
 {"lvsr",	X(31,38),	X_MASK,      PPCVEC,	PPCNONE,	{VD, RA, RB}},
@@ -3623,33 +4453,33 @@ const struct powerpc_opcode powerpc_opco
 
 {"isel",	XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, PPCNONE,	{RT, RA, RB, CRB}},
 
-{"subf",	XO(31,40,0,0),	XO_MASK,     PPC,	PPCNONE,	{RT, RA, RB}},
-{"sub",		XO(31,40,0,0),	XO_MASK,     PPC,	PPCNONE,	{RT, RB, RA}},
-{"subf.",	XO(31,40,0,1),	XO_MASK,     PPC,	PPCNONE,	{RT, RA, RB}},
-{"sub.",	XO(31,40,0,1),	XO_MASK,     PPC,	PPCNONE,	{RT, RB, RA}},
+{"subf",	XO(31,40,0,0),	XO_MASK, PPC|PPCVLE,	PPCNONE,	{RT, RA, RB}},
+{"sub",		XO(31,40,0,0),	XO_MASK, PPC|PPCVLE,	PPCNONE,	{RT, RB, RA}},
+{"subf.",	XO(31,40,0,1),	XO_MASK, PPC|PPCVLE,	PPCNONE,	{RT, RA, RB}},
+{"sub.",	XO(31,40,0,1),	XO_MASK, PPC|PPCVLE,	PPCNONE,	{RT, RB, RA}},
 
 {"eratilx",	X(31,51),	X_MASK,	     PPCA2,	PPCNONE,	{ERAT_T, RA, RB}},
 
 {"lbarx",	X(31,52),	XEH_MASK,    POWER7,	PPCNONE,	{RT, RA0, RB, EH}},
 
-{"ldux",	X(31,53),	X_MASK,      PPC64,	PPCNONE,	{RT, RAL, RB}},
+{"ldux",	X(31,53),	X_MASK,   PPC64|PPCVLE,	PPCNONE,	{RT, RAL, RB}},
 
-{"dcbst",	X(31,54),	XRT_MASK,    PPC,	PPCNONE,	{RA, RB}},
+{"dcbst",	X(31,54),	XRT_MASK, PPC|PPCVLE,	PPCNONE,	{RA, RB}},
 
-{"lwzux",	X(31,55),	X_MASK,      PPCCOM,	PPCNONE,	{RT, RAL, RB}},
+{"lwzux",	X(31,55),	X_MASK,  PPCCOM|PPCVLE,	PPCNONE,	{RT, RAL, RB}},
 {"lux",		X(31,55),	X_MASK,      PWRCOM,	PPCNONE,	{RT, RA, RB}},
 
-{"cntlzd",	XRC(31,58,0),	XRB_MASK,    PPC64,	PPCNONE,	{RA, RS}},
-{"cntlzd.",	XRC(31,58,1),	XRB_MASK,    PPC64,	PPCNONE,	{RA, RS}},
+{"cntlzd",	XRC(31,58,0),	XRB_MASK, PPC64|PPCVLE,	PPCNONE,	{RA, RS}},
+{"cntlzd.",	XRC(31,58,1),	XRB_MASK, PPC64|PPCVLE,	PPCNONE,	{RA, RS}},
 
-{"andc",	XRC(31,60,0),	X_MASK,      COM,	PPCNONE,	{RA, RS, RB}},
-{"andc.",	XRC(31,60,1),	X_MASK,      COM,	PPCNONE,	{RA, RS, RB}},
+{"andc",	XRC(31,60,0),	X_MASK,  COM|PPCVLE,	PPCNONE,	{RA, RS, RB}},
+{"andc.",	XRC(31,60,1),	X_MASK,  COM|PPCVLE,	PPCNONE,	{RA, RS, RB}},
 
 {"waitrsv",	X(31,62)|(1<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}},
 {"waitimpl",	X(31,62)|(2<<21), 0xffffffff, POWER7|E500MC|PPCA2, PPCNONE, {0}},
-{"wait",	X(31,62),	  XWC_MASK,   POWER7|E500MC|PPCA2, PPCNONE, {WC}},
+{"wait",	X(31,62),	  XWC_MASK,   POWER7|E500MC|PPCA2|PPCVLE, PPCNONE, {WC}},
 
-{"dcbstep",	XRT(31,63,0),	XRT_MASK, E500MC|PPCA2,	PPCNONE,	{RA, RB}},
+{"dcbstep",	XRT(31,63,0), XRT_MASK, E500MC|PPCA2|PPCVLE, PPCNONE,	{RA, RB}},
 
 {"tdlgt",	XTO(31,68,TOLGT), XTO_MASK,  PPC64,	PPCNONE,	{RA, RB}},
 {"tdllt",	XTO(31,68,TOLLT), XTO_MASK,  PPC64,	PPCNONE,	{RA, RB}},
@@ -3665,36 +4495,36 @@ const struct powerpc_opcode powerpc_opco
 {"tdle",	XTO(31,68,TOLE),  XTO_MASK,  PPC64,	PPCNONE,	{RA, RB}},
 {"tdng",	XTO(31,68,TONG),  XTO_MASK,  PPC64,	PPCNONE,	{RA, RB}},
 {"tdne",	XTO(31,68,TONE),  XTO_MASK,  PPC64,	PPCNONE,	{RA, RB}},
-{"td",		X(31,68),	X_MASK,      PPC64,	PPCNONE,	{TO, RA, RB}},
+{"td",		X(31,68),	X_MASK,  PPC64|PPCVLE,	PPCNONE,	{TO, RA, RB}},
 
 {"lwfcmx",	APU(31,71,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
-{"mulhd",	XO(31,73,0,0),	XO_MASK,     PPC64,	PPCNONE,	{RT, RA, RB}},
-{"mulhd.",	XO(31,73,0,1),	XO_MASK,     PPC64,	PPCNONE,	{RT, RA, RB}},
+{"mulhd",	XO(31,73,0,0),	XO_MASK, PPC64|PPCVLE,	PPCNONE,	{RT, RA, RB}},
+{"mulhd.",	XO(31,73,0,1),	XO_MASK, PPC64|PPCVLE,	PPCNONE,	{RT, RA, RB}},
 
-{"mulhw",	XO(31,75,0,0),	XO_MASK,     PPC,	PPCNONE,	{RT, RA, RB}},
-{"mulhw.",	XO(31,75,0,1),	XO_MASK,     PPC,	PPCNONE,	{RT, RA, RB}},
+{"mulhw",	XO(31,75,0,0),	XO_MASK, PPC|PPCVLE,	PPCNONE,	{RT, RA, RB}},
+{"mulhw.",	XO(31,75,0,1),	XO_MASK, PPC|PPCVLE,	PPCNONE,	{RT, RA, RB}},
 
 {"dlmzb",	XRC(31,78,0), X_MASK, PPC403|PPC440|TITAN, PPCNONE,	{RA, RS, RB}},
 {"dlmzb.",	XRC(31,78,1), X_MASK, PPC403|PPC440|TITAN, PPCNONE,	{RA, RS, RB}},
 
 {"mtsrd",	X(31,82),  XRB_MASK|(1<<20), PPC64,	PPCNONE,	{SR, RS}},
 
-{"mfmsr",	X(31,83),	XRARB_MASK,  COM,	PPCNONE,	{RT}},
+{"mfmsr",	X(31,83),	XRARB_MASK, COM|PPCVLE,	PPCNONE,	{RT}},
 
-{"ldarx",	X(31,84),	XEH_MASK,    PPC64,	PPCNONE,	{RT, RA0, RB, EH}},
+{"ldarx",	X(31,84),	XEH_MASK, PPC64|PPCVLE,	PPCNONE,	{RT, RA0, RB, EH}},
 
 {"dcbfl",	XOPL(31,86,1),	XRT_MASK,    POWER5,	PPC476,		{RA, RB}},
-{"dcbf",	X(31,86),	XLRT_MASK,   PPC,	PPCNONE,	{RA, RB, L}},
+{"dcbf",	X(31,86),	XLRT_MASK, PPC|PPCVLE,	PPCNONE,	{RA, RB, L}},
 
-{"lbzx",	X(31,87),	X_MASK,      COM,	PPCNONE,	{RT, RA0, RB}},
+{"lbzx",	X(31,87),	X_MASK,  COM|PPCVLE,	PPCNONE,	{RT, RA0, RB}},
 
-{"lbepx",	X(31,95),	X_MASK,   E500MC|PPCA2,	PPCNONE,	{RT, RA, RB}},
+{"lbepx",	X(31,95),	X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE,	{RT, RA, RB}},
 
 {"lvx",		X(31,103),	X_MASK,      PPCVEC,	PPCNONE,	{VD, RA, RB}},
 {"lqfcmx",	APU(31,103,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
 
-{"neg",		XO(31,104,0,0),	XORB_MASK,   COM,	PPCNONE,	{RT, RA}},
-{"neg.",	XO(31,104,0,1),	XORB_MASK,   COM,	PPCNONE,	{RT, RA}},
+{"neg",		XO(31,104,0,0),	XORB_MASK,  COM|PPCVLE,	PPCNONE,	{RT, RA}},
+{"neg.",	XO(31,104,0,1),	XORB_MASK,  COM|PPCVLE,	PPCNONE,	{RT, RA}},
 
 {"mul",		XO(31,107,0,0),	XO_MASK,     M601,	PPCNONE,	{RT, RA, RB}},
 {"mul.",	XO(31,107,0,1),	XO_MASK,     M601,	PPCNONE,	{RT, RA, RB}},
@@ -3705,50 +4535,50 @@ const struct powerpc_opcode powerpc_opco
 
 {"clf",		X(31,118),	XTO_MASK,    POWER,	PPCNONE,	{RA, RB}},
 
-{"lbzux",	X(31,119),	X_MASK,      COM,	PPCNONE,	{RT, RAL, RB}},
+{"lbzux",	X(31,119),	X_MASK,   COM|PPCVLE,	PPCNONE,	{RT, RAL, RB}},
 
-{"popcntb",	X(31,122),	XRB_MASK,    POWER5,	PPCNONE,	{RA, RS}},
+{"popcntb",	X(31,122),	XRB_MASK, POWER5|PPCVLE, PPCNONE,	{RA, RS}},
 
 {"not",		XRC(31,124,0),	X_MASK,      COM,	PPCNONE,	{RA, RS, RBS}},
-{"nor",		XRC(31,124,0),	X_MASK,      COM,	PPCNONE,	{RA, RS, RB}},
+{"nor",		XRC(31,124,0),	X_MASK,   COM|PPCVLE,	PPCNONE,	{RA, RS, RB}},
 {"not.",	XRC(31,124,1),	X_MASK,      COM,	PPCNONE,	{RA, RS, RBS}},
-{"nor.",	XRC(31,124,1),	X_MASK,      COM,	PPCNONE,	{RA, RS, RB}},
+{"nor.",	XRC(31,124,1),	X_MASK,   COM|PPCVLE,	PPCNONE,	{RA, RS, RB}},
 
-{"dcbfep",	XRT(31,127,0),	XRT_MASK, E500MC|PPCA2,	PPCNONE,	{RA, RB}},
+{"dcbfep",	XRT(31,127,0),	XRT_MASK, E500MC|PPCA2|PPCVLE,	PPCNONE,	{RA, RB}},
 
-{"wrtee",	X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RS}},
+{"wrtee",	X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RS}},
 
-{"dcbtstls",	X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE,	{CT, RA, RB}},
+{"dcbtstls",	X(31,134), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA, RB}},
 
 {"stvebx",	X(31,135),	X_MASK,      PPCVEC,	PPCNONE,	{VS, RA, RB}},
 {"stbfcmx",	APU(31,135,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
 
-{"subfe",	XO(31,136,0,0),	XO_MASK,     PPCCOM,	PPCNONE,	{RT, RA, RB}},
+{"subfe",	XO(31,136,0,0),	XO_MASK, PPCCOM|PPCVLE,	PPCNONE,	{RT, RA, RB}},
 {"sfe",		XO(31,136,0,0),	XO_MASK,     PWRCOM,	PPCNONE,	{RT, RA, RB}},
-{"subfe.",	XO(31,136,0,1),	XO_MASK,     PPCCOM,	PPCNONE,	{RT, RA, RB}},
+{"subfe.",	XO(31,136,0,1),	XO_MASK, PPCCOM|PPCVLE,	PPCNONE,	{RT, RA, RB}},
 {"sfe.",	XO(31,136,0,1),	XO_MASK,     PWRCOM,	PPCNONE,	{RT, RA, RB}},
 
-{"adde",	XO(31,138,0,0),	XO_MASK,     PPCCOM,	PPCNONE,	{RT, RA, RB}},
+{"adde",	XO(31,138,0,0),	XO_MASK, PPCCOM|PPCVLE,	PPCNONE,	{RT, RA, RB}},
 {"ae",		XO(31,138,0,0),	XO_MASK,     PWRCOM,	PPCNONE,	{RT, RA, RB}},
-{"adde.",	XO(31,138,0,1),	XO_MASK,     PPCCOM,	PPCNONE,	{RT, RA, RB}},
+{"adde.",	XO(31,138,0,1),	XO_MASK, PPCCOM|PPCVLE,	PPCNONE,	{RT, RA, RB}},
 {"ae.",		XO(31,138,0,1),	XO_MASK,     PWRCOM,	PPCNONE,	{RT, RA, RB}},
 
 {"dcbtstlse",	X(31,142),	X_MASK,      PPCCHLK,	PPCNONE,	{CT, RA, RB}},
 
 {"mtcr",	XFXM(31,144,0xff,0), XRARB_MASK, COM,	PPCNONE,	{RS}},
-{"mtcrf",	XFXM(31,144,0,0), XFXFXM_MASK, COM,	PPCNONE,	{FXM, RS}},
-{"mtocrf",	XFXM(31,144,0,1), XFXFXM_MASK, COM,	PPCNONE,	{FXM, RS}},
+{"mtcrf",	XFXM(31,144,0,0), XFXFXM_MASK, COM|PPCVLE, PPCNONE,	{FXM, RS}},
+{"mtocrf",	XFXM(31,144,0,1), XFXFXM_MASK, COM|PPCVLE, PPCNONE,	{FXM, RS}},
 
-{"mtmsr",	X(31,146),	XRLARB_MASK, COM,	PPCNONE,	{RS, A_L}},
+{"mtmsr",	X(31,146),XRLARB_MASK,     COM|PPCVLE,	PPCNONE,	{RS, A_L}},
 
 {"eratsx",	XRC(31,147,0),	X_MASK,	     PPCA2,	PPCNONE,	{RT, RA0, RB}},
 {"eratsx.",	XRC(31,147,1),	X_MASK,	     PPCA2,	PPCNONE,	{RT, RA0, RB}},
 
-{"stdx",	X(31,149),	X_MASK,      PPC64,	PPCNONE,	{RS, RA0, RB}},
+{"stdx",	X(31,149),	X_MASK,  PPC64|PPCVLE,	PPCNONE,	{RS, RA0, RB}},
 
-{"stwcx.",	XRC(31,150,1),	X_MASK,      PPC,	PPCNONE,	{RS, RA0, RB}},
+{"stwcx.",	XRC(31,150,1),	X_MASK,  PPC|PPCVLE,	PPCNONE,	{RS, RA0, RB}},
 
-{"stwx",	X(31,151),	X_MASK,      PPCCOM,	PPCNONE,	{RS, RA0, RB}},
+{"stwx",	X(31,151),	X_MASK,  PPCCOM|PPCVLE,	PPCNONE,	{RS, RA0, RB}},
 {"stx",		X(31,151),	X_MASK,      PWRCOM,	PPCNONE,	{RS, RA, RB}},
 
 {"slq",		XRC(31,152,0),	X_MASK,      M601,	PPCNONE,	{RA, RS, RB}},
@@ -3759,13 +4589,13 @@ const struct powerpc_opcode powerpc_opco
 
 {"prtyw",	X(31,154),	XRB_MASK, POWER6|PPCA2|PPC476, PPCNONE,	{RA, RS}},
 
-{"stdepx",	X(31,157),	X_MASK,   E500MC|PPCA2,	PPCNONE,	{RS, RA, RB}},
+{"stdepx",	X(31,157),	X_MASK,   E500MC|PPCA2|PPCVLE,	PPCNONE,	{RS, RA, RB}},
 
-{"stwepx",	X(31,159),	X_MASK,   E500MC|PPCA2,	PPCNONE,	{RS, RA, RB}},
+{"stwepx",	X(31,159),	X_MASK,   E500MC|PPCA2|PPCVLE,	PPCNONE,	{RS, RA, RB}},
 
-{"wrteei",	X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE,	{E}},
+{"wrteei",	X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE,	{E}},
 
-{"dcbtls",	X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE,	{CT, RA, RB}},
+{"dcbtls",	X(31,166), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE,	{CT, RA, RB}},
 
 {"stvehx",	X(31,167),	X_MASK,      PPCVEC,	PPCNONE,	{VS, RA, RB}},
 {"sthfcmx",	APU(31,167,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
@@ -3776,11 +4606,11 @@ const struct powerpc_opcode powerpc_opco
 
 {"eratre",	X(31,179),	X_MASK,	     PPCA2,	PPCNONE,	{RT, RA, WS}},
 
-{"stdux",	X(31,181),	X_MASK,      PPC64,	PPCNONE,	{RS, RAS, RB}},
+{"stdux",	X(31,181),	X_MASK, PPC64|PPCVLE,	PPCNONE,	{RS, RAS, RB}},
 
 {"wchkall",	X(31,182),	X_MASK,      PPCA2,	PPCNONE,	{OBF}},
 
-{"stwux",	X(31,183),	X_MASK,      PPCCOM,	PPCNONE,	{RS, RAS, RB}},
+{"stwux",	X(31,183),	X_MASK, PPCCOM|PPCVLE,	PPCNONE,	{RS, RAS, RB}},
 {"stux",	X(31,183),	X_MASK,      PWRCOM,	PPCNONE,	{RS, RA0, RB}},
 
 {"sliq",	XRC(31,184,0),	X_MASK,      M601,	PPCNONE,	{RA, RS, SH}},
@@ -3791,17 +4621,17 @@ const struct powerpc_opcode powerpc_opco
 {"stvewx",	X(31,199),	X_MASK,      PPCVEC,	PPCNONE,	{VS, RA, RB}},
 {"stwfcmx",	APU(31,199,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
 
-{"subfze",	XO(31,200,0,0),	XORB_MASK,   PPCCOM,	PPCNONE,	{RT, RA}},
+{"subfze",	XO(31,200,0,0),	XORB_MASK, PPCCOM|PPCVLE, PPCNONE,	{RT, RA}},
 {"sfze",	XO(31,200,0,0),	XORB_MASK,   PWRCOM,	PPCNONE,	{RT, RA}},
-{"subfze.",	XO(31,200,0,1),	XORB_MASK,   PPCCOM,	PPCNONE,	{RT, RA}},
+{"subfze.",	XO(31,200,0,1),	XORB_MASK, PPCCOM|PPCVLE, PPCNONE,	{RT, RA}},
 {"sfze.",	XO(31,200,0,1),	XORB_MASK,   PWRCOM,	PPCNONE,	{RT, RA}},
 
-{"addze",	XO(31,202,0,0),	XORB_MASK,   PPCCOM,	PPCNONE,	{RT, RA}},
+{"addze",	XO(31,202,0,0),	XORB_MASK, PPCCOM|PPCVLE, PPCNONE,	{RT, RA}},
 {"aze",		XO(31,202,0,0),	XORB_MASK,   PWRCOM,	PPCNONE,	{RT, RA}},
-{"addze.",	XO(31,202,0,1),	XORB_MASK,   PPCCOM,	PPCNONE,	{RT, RA}},
+{"addze.",	XO(31,202,0,1),	XORB_MASK, PPCCOM|PPCVLE, PPCNONE,	{RT, RA}},
 {"aze.",	XO(31,202,0,1),	XORB_MASK,   PWRCOM,	PPCNONE,	{RT, RA}},
 
-{"msgsnd",	XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2, PPCNONE,	{RB}},
+{"msgsnd",	XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|PPCVLE, PPCNONE,	{RB}},
 
 {"mtsr",	X(31,210), XRB_MASK|(1<<20), COM,	NON32,  	{SR, RS}},
 
@@ -3809,9 +4639,9 @@ const struct powerpc_opcode powerpc_opco
 
 {"ldawx.",	XRC(31,212,1),	X_MASK,	     PPCA2,	PPCNONE,	{RT, RA0, RB}},
 
-{"stdcx.",	XRC(31,214,1),	X_MASK,      PPC64,	PPCNONE,	{RS, RA0, RB}},
+{"stdcx.",	XRC(31,214,1),	X_MASK,  PPC64|PPCVLE,	PPCNONE,	{RS, RA0, RB}},
 
-{"stbx",	X(31,215),	X_MASK,      COM,	PPCNONE,	{RS, RA0, RB}},
+{"stbx",	X(31,215),	X_MASK,  COM|PPCVLE,	PPCNONE,	{RS, RA0, RB}},
 
 {"sllq",	XRC(31,216,0),	X_MASK,      M601,	PPCNONE,	{RA, RS, RB}},
 {"sllq.",	XRC(31,216,1),	X_MASK,      M601,	PPCNONE,	{RA, RS, RB}},
@@ -3819,41 +4649,41 @@ const struct powerpc_opcode powerpc_opco
 {"sleq",	XRC(31,217,0),	X_MASK,      M601,	PPCNONE,	{RA, RS, RB}},
 {"sleq.",	XRC(31,217,1),	X_MASK,      M601,	PPCNONE,	{RA, RS, RB}},
 
-{"stbepx",	X(31,223),	X_MASK,   E500MC|PPCA2,	PPCNONE,	{RS, RA, RB}},
+{"stbepx",	X(31,223),	X_MASK,   E500MC|PPCA2|PPCVLE,	PPCNONE,	{RS, RA, RB}},
 
-{"icblc",	X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE,	{CT, RA, RB}},
+{"icblc",	X(31,230), X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE, {CT, RA, RB}},
 
 {"stvx",	X(31,231),	X_MASK,      PPCVEC,	PPCNONE,	{VS, RA, RB}},
 {"stqfcmx",	APU(31,231,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
 
-{"subfme",	XO(31,232,0,0),	XORB_MASK,   PPCCOM,	PPCNONE,	{RT, RA}},
+{"subfme",	XO(31,232,0,0),	XORB_MASK, PPCCOM|PPCVLE, PPCNONE,	{RT, RA}},
 {"sfme",	XO(31,232,0,0),	XORB_MASK,   PWRCOM,	PPCNONE,	{RT, RA}},
-{"subfme.",	XO(31,232,0,1),	XORB_MASK,   PPCCOM,	PPCNONE,	{RT, RA}},
+{"subfme.",	XO(31,232,0,1),	XORB_MASK, PPCCOM|PPCVLE, PPCNONE,	{RT, RA}},
 {"sfme.",	XO(31,232,0,1),	XORB_MASK,   PWRCOM,	PPCNONE,	{RT, RA}},
 
-{"mulld",	XO(31,233,0,0),	XO_MASK,     PPC64,	PPCNONE,	{RT, RA, RB}},
-{"mulld.",	XO(31,233,0,1),	XO_MASK,     PPC64,	PPCNONE,	{RT, RA, RB}},
+{"mulld",	XO(31,233,0,0),	XO_MASK,  PPC64|PPCVLE,	PPCNONE,	{RT, RA, RB}},
+{"mulld.",	XO(31,233,0,1),	XO_MASK,  PPC64|PPCVLE,	PPCNONE,	{RT, RA, RB}},
 
-{"addme",	XO(31,234,0,0),	XORB_MASK,   PPCCOM,	PPCNONE,	{RT, RA}},
+{"addme",	XO(31,234,0,0),	XORB_MASK, PPCCOM|PPCVLE, PPCNONE,	{RT, RA}},
 {"ame",		XO(31,234,0,0),	XORB_MASK,   PWRCOM,	PPCNONE,	{RT, RA}},
-{"addme.",	XO(31,234,0,1),	XORB_MASK,   PPCCOM,	PPCNONE,	{RT, RA}},
+{"addme.",	XO(31,234,0,1),	XORB_MASK, PPCCOM|PPCVLE, PPCNONE,	{RT, RA}},
 {"ame.",	XO(31,234,0,1),	XORB_MASK,   PWRCOM,	PPCNONE,	{RT, RA}},
 
-{"mullw",	XO(31,235,0,0),	XO_MASK,     PPCCOM,	PPCNONE,	{RT, RA, RB}},
+{"mullw",	XO(31,235,0,0),	XO_MASK, PPCCOM|PPCVLE,	PPCNONE,	{RT, RA, RB}},
 {"muls",	XO(31,235,0,0),	XO_MASK,     PWRCOM,	PPCNONE,	{RT, RA, RB}},
-{"mullw.",	XO(31,235,0,1),	XO_MASK,     PPCCOM,	PPCNONE,	{RT, RA, RB}},
+{"mullw.",	XO(31,235,0,1),	XO_MASK, PPCCOM|PPCVLE,	PPCNONE,	{RT, RA, RB}},
 {"muls.",	XO(31,235,0,1),	XO_MASK,     PWRCOM,	PPCNONE,	{RT, RA, RB}},
 
 {"icblce",	X(31,238),	X_MASK,      PPCCHLK,	E500MC|PPCA2,	{CT, RA, RB}},
-{"msgclr",	XRTRA(31,238,0,0),XRTRA_MASK,E500MC|PPCA2, PPCNONE,	{RB}},
+{"msgclr",	XRTRA(31,238,0,0),XRTRA_MASK,E500MC|PPCA2|PPCVLE, PPCNONE,	{RB}},
 {"mtsrin",	X(31,242),	XRA_MASK,    PPC,	NON32,  	{RS, RB}},
 {"mtsri",	X(31,242),	XRA_MASK,    POWER,	NON32,		{RS, RB}},
 
 {"dcbtstt",	XRT(31,246,0x10), XRT_MASK,  POWER7,	PPCNONE,	{RA, RB}},
 {"dcbtst",	X(31,246),	X_MASK,      POWER4,	PPCNONE,	{RA, RB, CT}},
-{"dcbtst",	X(31,246),	X_MASK,      PPC,	POWER4,		{CT, RA, RB}},
+{"dcbtst",	X(31,246),	X_MASK,   PPC|PPCVLE,	POWER4,		{CT, RA, RB}},
 
-{"stbux",	X(31,247),	X_MASK,      COM,	PPCNONE,	{RS, RAS, RB}},
+{"stbux",	X(31,247),	X_MASK,   COM|PPCVLE,	PPCNONE,	{RS, RAS, RB}},
 
 {"slliq",	XRC(31,248,0),	X_MASK,      M601,	PPCNONE,	{RA, RS, SH}},
 {"slliq.",	XRC(31,248,1),	X_MASK,      M601,	PPCNONE,	{RA, RS, SH}},
@@ -3862,7 +4692,7 @@ const struct powerpc_opcode powerpc_opco
 
 {"dcbtstep",	XRT(31,255,0),	X_MASK,   E500MC|PPCA2,	PPCNONE,	{RT, RA, RB}},
 
-{"mfdcrx",	X(31,259),	X_MASK, BOOKE|PPCA2|PPC476, TITAN,	{RS, RA}},
+{"mfdcrx",	X(31,259),	X_MASK, BOOKE|PPCA2|PPC476|PPCVLE, TITAN,	{RS, RA}},
 {"mfdcrx.",	XRC(31,259,1),	X_MASK,      PPCA2,	PPCNONE,	{RS, RA}},
 
 {"icbt",	X(31,262),	XRT_MASK,    PPC403,	PPCNONE,	{RA, RB}},
@@ -3871,9 +4701,9 @@ const struct powerpc_opcode powerpc_opco
 {"doz",		XO(31,264,0,0),	XO_MASK,     M601,	PPCNONE,	{RT, RA, RB}},
 {"doz.",	XO(31,264,0,1),	XO_MASK,     M601,	PPCNONE,	{RT, RA, RB}},
 
-{"add",		XO(31,266,0,0),	XO_MASK,     PPCCOM,	PPCNONE,	{RT, RA, RB}},
+{"add",		XO(31,266,0,0),	XO_MASK, PPCCOM|PPCVLE,	PPCNONE,	{RT, RA, RB}},
 {"cax",		XO(31,266,0,0),	XO_MASK,     PWRCOM,	PPCNONE,	{RT, RA, RB}},
-{"add.",	XO(31,266,0,1),	XO_MASK,     PPCCOM,	PPCNONE,	{RT, RA, RB}},
+{"add.",	XO(31,266,0,1),	XO_MASK, PPCCOM|PPCVLE,	PPCNONE,	{RT, RA, RB}},
 {"cax.",	XO(31,266,0,1),	XO_MASK,     PWRCOM,	PPCNONE,	{RT, RA, RB}},
 
 {"ehpriv",	X(31,270),	0xffffffff, E500MC|PPCA2, PPCNONE,	{0}},
@@ -3887,32 +4717,32 @@ const struct powerpc_opcode powerpc_opco
 
 {"dcbtt",	XRT(31,278,0x10), XRT_MASK,  POWER7,	PPCNONE,	{RA, RB}},
 {"dcbt",	X(31,278),	X_MASK,      POWER4,	PPCNONE,	{RA, RB, CT}},
-{"dcbt",	X(31,278),	X_MASK,      PPC,	POWER4,		{CT, RA, RB}},
+{"dcbt",	X(31,278),	X_MASK,     PPC|PPCVLE,	POWER4,		{CT, RA, RB}},
 
-{"lhzx",	X(31,279),	X_MASK,      COM,	PPCNONE,	{RT, RA0, RB}},
+{"lhzx",	X(31,279),	X_MASK,   COM|PPCVLE,	PPCNONE,	{RT, RA0, RB}},
 
 {"cdtbcd",	X(31,282),	XRB_MASK,    POWER6,	PPCNONE,	{RA, RS}},
 
-{"eqv",		XRC(31,284,0),	X_MASK,      COM,	PPCNONE,	{RA, RS, RB}},
-{"eqv.",	XRC(31,284,1),	X_MASK,      COM,	PPCNONE,	{RA, RS, RB}},
+{"eqv",		XRC(31,284,0),	X_MASK,   COM|PPCVLE,	PPCNONE,	{RA, RS, RB}},
+{"eqv.",	XRC(31,284,1),	X_MASK,   COM|PPCVLE,	PPCNONE,	{RA, RS, RB}},
 
-{"lhepx",	X(31,287),	X_MASK,   E500MC|PPCA2,	PPCNONE,	{RT, RA, RB}},
+{"lhepx",	X(31,287),	X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE,	{RT, RA, RB}},
 
-{"mfdcrux",	X(31,291),	X_MASK,      PPC464,	PPCNONE,	{RS, RA}},
+{"mfdcrux",	X(31,291),	X_MASK,   PPC464|PPCVLE, PPCNONE,	{RS, RA}},
 
 {"tlbie",	X(31,306),	XRTLRA_MASK, PPC,	TITAN,  	{RB, L}},
 {"tlbi",	X(31,306),	XRT_MASK,    POWER,	PPCNONE,	{RA0, RB}},
 
 {"eciwx",	X(31,310),	X_MASK,      PPC,	TITAN,  	{RT, RA, RB}},
 
-{"lhzux",	X(31,311),	X_MASK,      COM,	PPCNONE,	{RT, RAL, RB}},
+{"lhzux",	X(31,311),	X_MASK,    COM|PPCVLE,	PPCNONE,	{RT, RAL, RB}},
 
 {"cbcdtd",	X(31,314),	XRB_MASK,    POWER6,	PPCNONE,	{RA, RS}},
 
-{"xor",		XRC(31,316,0),	X_MASK,      COM,	PPCNONE,	{RA, RS, RB}},
-{"xor.",	XRC(31,316,1),	X_MASK,      COM,	PPCNONE,	{RA, RS, RB}},
+{"xor",		XRC(31,316,0),	X_MASK,    COM|PPCVLE,	PPCNONE,	{RA, RS, RB}},
+{"xor.",	XRC(31,316,1),	X_MASK,    COM|PPCVLE,	PPCNONE,	{RA, RS, RB}},
 
-{"dcbtep",	XRT(31,319,0),	X_MASK,   E500MC|PPCA2,	PPCNONE,	{RT, RA, RB}},
+{"dcbtep",	XRT(31,319,0),	X_MASK, E500MC|PPCA2|PPCVLE, PPCNONE,	{RT, RA, RB}},
 
 {"mfexisr",	XSPR(31,323, 64), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
 {"mfexier",	XSPR(31,323, 66), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
@@ -3948,7 +4778,7 @@ const struct powerpc_opcode powerpc_opco
 {"mfdmasa3",	XSPR(31,323,219), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
 {"mfdmacc3",	XSPR(31,323,220), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
 {"mfdmasr",	XSPR(31,323,224), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
-{"mfdcr",	X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, TITAN,	{RT, SPR}},
+{"mfdcr",	X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, TITAN,	{RT, SPR}},
 {"mfdcr.",	XRC(31,323,1),	X_MASK,      PPCA2,	PPCNONE,	{RT, SPR}},
 
 {"dcread",	X(31,326),	X_MASK,  PPC476|TITAN,	PPCNONE,	{RT, RA, RB}},
@@ -3958,15 +4788,15 @@ const struct powerpc_opcode powerpc_opco
 
 {"lxvdsx",	X(31,332),	XX1_MASK,    PPCVSX,	PPCNONE,	{XT6, RA, RB}},
 
-{"mfpmr",	X(31,334),	X_MASK, PPCPMR|PPCE300,	PPCNONE,	{RT, PMR}},
+{"mfpmr",	X(31,334),  X_MASK, PPCPMR|PPCE300|PPCVLE, PPCNONE,	{RT, PMR}},
 
 {"mfmq",	XSPR(31,339,  0), XSPR_MASK, M601,	PPCNONE,	{RT}},
-{"mfxer",	XSPR(31,339,  1), XSPR_MASK, COM,	PPCNONE,	{RT}},
+{"mfxer",	XSPR(31,339,  1), XSPR_MASK, COM|PPCVLE,	PPCNONE,	{RT}},
 {"mfrtcu",	XSPR(31,339,  4), XSPR_MASK, COM,	TITAN,  	{RT}},
 {"mfrtcl",	XSPR(31,339,  5), XSPR_MASK, COM,	TITAN,  	{RT}},
 {"mfdec",	XSPR(31,339,  6), XSPR_MASK, MFDEC1,	PPCNONE,	{RT}},
-{"mflr",	XSPR(31,339,  8), XSPR_MASK, COM,	PPCNONE,	{RT}},
-{"mfctr",	XSPR(31,339,  9), XSPR_MASK, COM,	PPCNONE,	{RT}},
+{"mflr",	XSPR(31,339,  8), XSPR_MASK, COM|PPCVLE,	PPCNONE,	{RT}},
+{"mfctr",	XSPR(31,339,  9), XSPR_MASK, COM|PPCVLE,	PPCNONE,	{RT}},
 {"mftid",	XSPR(31,339, 17), XSPR_MASK, POWER,	PPCNONE,	{RT}},
 {"mfdsisr",	XSPR(31,339, 18), XSPR_MASK, COM,	TITAN,  	{RT}},
 {"mfdar",	XSPR(31,339, 19), XSPR_MASK, COM,	TITAN,  	{RT}},
@@ -3976,12 +4806,12 @@ const struct powerpc_opcode powerpc_opco
 {"mfsrr0",	XSPR(31,339, 26), XSPR_MASK, COM,	PPCNONE,	{RT}},
 {"mfsrr1",	XSPR(31,339, 27), XSPR_MASK, COM,	PPCNONE,	{RT}},
 {"mfcfar",	XSPR(31,339, 28), XSPR_MASK, POWER6,	PPCNONE,	{RT}},
-{"mfpid",	XSPR(31,339, 48), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mfcsrr0",	XSPR(31,339, 58), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mfcsrr1",	XSPR(31,339, 59), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mfdear",	XSPR(31,339, 61), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mfesr",	XSPR(31,339, 62), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mfivpr",	XSPR(31,339, 63), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
+{"mfpid",	XSPR(31,339, 48), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mfcsrr0",	XSPR(31,339, 58), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mfcsrr1",	XSPR(31,339, 59), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mfdear",	XSPR(31,339, 61), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mfesr",	XSPR(31,339, 62), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mfivpr",	XSPR(31,339, 63), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
 {"mfcmpa",	XSPR(31,339,144), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
 {"mfcmpb",	XSPR(31,339,145), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
 {"mfcmpc",	XSPR(31,339,146), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
@@ -3999,53 +4829,53 @@ const struct powerpc_opcode powerpc_opco
 {"mfictrl",	XSPR(31,339,158), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
 {"mfbar",	XSPR(31,339,159), XSPR_MASK, PPC860,	PPCNONE,	{RT}},
 {"mfvrsave",	XSPR(31,339,256), XSPR_MASK, PPCVEC,	PPCNONE,	{RT}},
-{"mfusprg0",	XSPR(31,339,256), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mfsprg",	XSPR(31,339,256), XSPRG_MASK, PPC,	PPCNONE,	{RT, SPRG}},
-{"mfsprg4",	XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, PPCNONE,	{RT}},
-{"mfsprg5",	XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, PPCNONE,	{RT}},
-{"mfsprg6",	XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, PPCNONE,	{RT}},
-{"mfsprg7",	XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, PPCNONE,	{RT}},
-{"mftb",	XSPR(31,339,268), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mftbl",	XSPR(31,339,268), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mftbu",	XSPR(31,339,269), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mfsprg0",	XSPR(31,339,272), XSPR_MASK, PPC,	PPCNONE,	{RT}},
-{"mfsprg1",	XSPR(31,339,273), XSPR_MASK, PPC,	PPCNONE,	{RT}},
-{"mfsprg2",	XSPR(31,339,274), XSPR_MASK, PPC,	PPCNONE,	{RT}},
-{"mfsprg3",	XSPR(31,339,275), XSPR_MASK, PPC,	PPCNONE,	{RT}},
+{"mfusprg0",	XSPR(31,339,256), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mfsprg",	XSPR(31,339,256), XSPRG_MASK, PPC|PPCVLE,	PPCNONE,	{RT, SPRG}},
+{"mfsprg4",	XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE,	{RT}},
+{"mfsprg5",	XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE,	{RT}},
+{"mfsprg6",	XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE,	{RT}},
+{"mfsprg7",	XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE,	{RT}},
+{"mftb",	XSPR(31,339,268), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mftbl",	XSPR(31,339,268), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mftbu",	XSPR(31,339,269), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mfsprg0",	XSPR(31,339,272), XSPR_MASK, PPC|PPCVLE,	PPCNONE,	{RT}},
+{"mfsprg1",	XSPR(31,339,273), XSPR_MASK, PPC|PPCVLE,	PPCNONE,	{RT}},
+{"mfsprg2",	XSPR(31,339,274), XSPR_MASK, PPC|PPCVLE,	PPCNONE,	{RT}},
+{"mfsprg3",	XSPR(31,339,275), XSPR_MASK, PPC|PPCVLE,	PPCNONE,	{RT}},
 {"mfasr",	XSPR(31,339,280), XSPR_MASK, PPC64,	PPCNONE,	{RT}},
 {"mfear",	XSPR(31,339,282), XSPR_MASK, PPC,	TITAN,  	{RT}},
-{"mfpir",	XSPR(31,339,286), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mfpvr",	XSPR(31,339,287), XSPR_MASK, PPC,	PPCNONE,	{RT}},
-{"mfdbsr",	XSPR(31,339,304), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mfdbcr0",	XSPR(31,339,308), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mfdbcr1",	XSPR(31,339,309), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mfdbcr2",	XSPR(31,339,310), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mfiac1",	XSPR(31,339,312), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mfiac2",	XSPR(31,339,313), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mfiac3",	XSPR(31,339,314), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mfiac4",	XSPR(31,339,315), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mfdac1",	XSPR(31,339,316), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mfdac2",	XSPR(31,339,317), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mfdvc1",	XSPR(31,339,318), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mfdvc2",	XSPR(31,339,319), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mftsr",	XSPR(31,339,336), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mftcr",	XSPR(31,339,340), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mfivor0",	XSPR(31,339,400), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mfivor1",	XSPR(31,339,401), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mfivor2",	XSPR(31,339,402), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mfivor3",	XSPR(31,339,403), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mfivor4",	XSPR(31,339,404), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mfivor5",	XSPR(31,339,405), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mfivor6",	XSPR(31,339,406), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mfivor7",	XSPR(31,339,407), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mfivor8",	XSPR(31,339,408), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mfivor9",	XSPR(31,339,409), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mfivor10",	XSPR(31,339,410), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mfivor11",	XSPR(31,339,411), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mfivor12",	XSPR(31,339,412), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mfivor13",	XSPR(31,339,413), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mfivor14",	XSPR(31,339,414), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
-{"mfivor15",	XSPR(31,339,415), XSPR_MASK, BOOKE,	PPCNONE,	{RT}},
+{"mfpir",	XSPR(31,339,286), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mfpvr",	XSPR(31,339,287), XSPR_MASK, PPC|PPCVLE,	PPCNONE,	{RT}},
+{"mfdbsr",	XSPR(31,339,304), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mfdbcr0",	XSPR(31,339,308), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mfdbcr1",	XSPR(31,339,309), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mfdbcr2",	XSPR(31,339,310), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mfiac1",	XSPR(31,339,312), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mfiac2",	XSPR(31,339,313), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mfiac3",	XSPR(31,339,314), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mfiac4",	XSPR(31,339,315), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mfdac1",	XSPR(31,339,316), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mfdac2",	XSPR(31,339,317), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mfdvc1",	XSPR(31,339,318), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mfdvc2",	XSPR(31,339,319), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mftsr",	XSPR(31,339,336), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mftcr",	XSPR(31,339,340), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mfivor0",	XSPR(31,339,400), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mfivor1",	XSPR(31,339,401), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mfivor2",	XSPR(31,339,402), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mfivor3",	XSPR(31,339,403), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mfivor4",	XSPR(31,339,404), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mfivor5",	XSPR(31,339,405), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mfivor6",	XSPR(31,339,406), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mfivor7",	XSPR(31,339,407), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mfivor8",	XSPR(31,339,408), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mfivor9",	XSPR(31,339,409), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mfivor10",	XSPR(31,339,410), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mfivor11",	XSPR(31,339,411), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mfivor12",	XSPR(31,339,412), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mfivor13",	XSPR(31,339,413), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mfivor14",	XSPR(31,339,414), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
+{"mfivor15",	XSPR(31,339,415), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RT}},
 {"mfspefscr",	XSPR(31,339,512), XSPR_MASK, PPCSPE,	PPCNONE,	{RT}},
 {"mfbbear",	XSPR(31,339,513), XSPR_MASK, PPCBRLK,	PPCNONE,	{RT}},
 {"mfbbtar",	XSPR(31,339,514), XSPR_MASK, PPCBRLK,	PPCNONE,	{RT}},
@@ -4156,13 +4986,13 @@ const struct powerpc_opcode powerpc_opco
 {"mfpbl2",	XSPR(31,339,1022), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
 {"mfthrm3",	XSPR(31,339,1022), XSPR_MASK, PPC750,	PPCNONE,	{RT}},
 {"mfpbu2",	XSPR(31,339,1023), XSPR_MASK, PPC403,	PPCNONE,	{RT}},
-{"mfspr",	X(31,339),	X_MASK,      COM,	PPCNONE,	{RT, SPR}},
+{"mfspr",	X(31,339),	X_MASK,   COM|PPCVLE,	PPCNONE,	{RT, SPR}},
 
-{"lwax",	X(31,341),	X_MASK,      PPC64,	PPCNONE,	{RT, RA0, RB}},
+{"lwax",	X(31,341),	X_MASK,   PPC64|PPCVLE,	PPCNONE,	{RT, RA0, RB}},
 
 {"dst",		XDSS(31,342,0),	XDSS_MASK,   PPCVEC,	PPCNONE,	{RA, RB, STRM}},
 
-{"lhax",	X(31,343),	X_MASK,      COM,	PPCNONE,	{RT, RA0, RB}},
+{"lhax",	X(31,343),	X_MASK,    COM|PPCVLE,	PPCNONE,	{RT, RA0, RB}},
 
 {"lvxl",	X(31,359),	X_MASK,      PPCVEC,	PPCNONE,	{VD, RA, RB}},
 
@@ -4178,18 +5008,18 @@ const struct powerpc_opcode powerpc_opco
 {"mftbu",	XSPR(31,371,269), XSPR_MASK, PPC,	NO371,		{RT}},
 {"mftb",	X(31,371),	X_MASK,      PPC|PPCA2,	NO371|POWER7,	{RT, TBR}},
 
-{"lwaux",	X(31,373),	X_MASK,      PPC64,	PPCNONE,	{RT, RAL, RB}},
+{"lwaux",	X(31,373),	X_MASK,   PPC64|PPCVLE,	PPCNONE,	{RT, RAL, RB}},
 
 {"dstst",	XDSS(31,374,0),	XDSS_MASK,   PPCVEC,	PPCNONE,	{RA, RB, STRM}},
 
-{"lhaux",	X(31,375),	X_MASK,      COM,	PPCNONE,	{RT, RAL, RB}},
+{"lhaux",	X(31,375),	X_MASK,   COM|PPCVLE,	PPCNONE,	{RT, RAL, RB}},
 
 {"popcntw",	X(31,378),	XRB_MASK, POWER7|PPCA2,	PPCNONE,	{RA, RS}},
 
 {"mtdcrx",	X(31,387),	X_MASK, BOOKE|PPCA2|PPC476, TITAN,	{RA, RS}},
-{"mtdcrx.",	XRC(31,387,1),	X_MASK,      PPCA2,	PPCNONE,	{RA, RS}},
+{"mtdcrx.",	XRC(31,387,1),	X_MASK,  PPCA2|PPCVLE,	PPCNONE,	{RA, RS}},
 
-{"dcblc",	X(31,390),	X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE,	{CT, RA, RB}},
+{"dcblc",	X(31,390),	X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE,	{CT, RA, RB}},
 {"stdfcmx",	APU(31,391,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
 
 {"divdeu",	XO(31,393,0,0),	XO_MASK,  POWER7|PPCA2,	PPCNONE,	{RT, RA, RB}},
@@ -4204,14 +5034,14 @@ const struct powerpc_opcode powerpc_opco
 {"icswx",	XRC(31,406,0),	X_MASK,   POWER7|PPCA2,	PPCNONE,	{RS, RA, RB}},
 {"icswx.",	XRC(31,406,1),	X_MASK,   POWER7|PPCA2,	PPCNONE,	{RS, RA, RB}},
 
-{"sthx",	X(31,407),	X_MASK,      COM,	PPCNONE,	{RS, RA0, RB}},
+{"sthx",	X(31,407),	X_MASK,   COM|PPCVLE,	PPCNONE,	{RS, RA0, RB}},
 
-{"orc",		XRC(31,412,0),	X_MASK,      COM,	PPCNONE,	{RA, RS, RB}},
-{"orc.",	XRC(31,412,1),	X_MASK,      COM,	PPCNONE,	{RA, RS, RB}},
+{"orc",		XRC(31,412,0),	X_MASK,   COM|PPCVLE,	PPCNONE,	{RA, RS, RB}},
+{"orc.",	XRC(31,412,1),	X_MASK,   COM|PPCVLE,	PPCNONE,	{RA, RS, RB}},
 
-{"sthepx",	X(31,415),	X_MASK,   E500MC|PPCA2,	PPCNONE,	{RS, RA, RB}},
+{"sthepx",	X(31,415),	X_MASK,   E500MC|PPCA2|PPCVLE,	PPCNONE,	{RS, RA, RB}},
 
-{"mtdcrux",	X(31,419),	X_MASK,      PPC464,	PPCNONE,	{RA, RS}},
+{"mtdcrux",	X(31,419),	X_MASK,  PPC464|PPCVLE,	PPCNONE,	{RA, RS}},
 
 {"divde",	XO(31,425,0,0),	XO_MASK,  POWER7|PPCA2,	PPCNONE,	{RT, RA, RB}},
 {"divde.",	XO(31,425,0,1),	XO_MASK,  POWER7|PPCA2,	PPCNONE,	{RT, RA, RB}},
@@ -4222,14 +5052,14 @@ const struct powerpc_opcode powerpc_opco
 
 {"ecowx",	X(31,438),	X_MASK,      PPC,	TITAN,  	{RT, RA, RB}},
 
-{"sthux",	X(31,439),	X_MASK,      COM,	PPCNONE,	{RS, RAS, RB}},
+{"sthux",	X(31,439),	X_MASK,    COM|PPCVLE,	PPCNONE,	{RS, RAS, RB}},
 
 {"mdors",	0x7f9ce378,	0xffffffff,  E500MC,	PPCNONE,	{0}},
 
-{"mr",		XRC(31,444,0),	X_MASK,      COM,	PPCNONE,	{RA, RS, RBS}},
-{"or",		XRC(31,444,0),	X_MASK,      COM,	PPCNONE,	{RA, RS, RB}},
-{"mr.",		XRC(31,444,1),	X_MASK,      COM,	PPCNONE,	{RA, RS, RBS}},
-{"or.",		XRC(31,444,1),	X_MASK,      COM,	PPCNONE,	{RA, RS, RB}},
+{"mr",		XRC(31,444,0),	X_MASK,   COM|PPCVLE,	PPCNONE,	{RA, RS, RBS}},
+{"or",		XRC(31,444,0),	X_MASK,   COM|PPCVLE,	PPCNONE,	{RA, RS, RB}},
+{"mr.",		XRC(31,444,1),	X_MASK,   COM|PPCVLE,	PPCNONE,	{RA, RS, RBS}},
+{"or.",		XRC(31,444,1),	X_MASK,   COM|PPCVLE,	PPCNONE,	{RA, RS, RB}},
 
 {"mtexisr",	XSPR(31,451, 64), XSPR_MASK, PPC403,	PPCNONE,	{RS}},
 {"mtexier",	XSPR(31,451, 66), XSPR_MASK, PPC403,	PPCNONE,	{RS}},
@@ -4265,24 +5095,24 @@ const struct powerpc_opcode powerpc_opco
 {"mtdmasa3",	XSPR(31,451,219), XSPR_MASK, PPC403,	PPCNONE,	{RS}},
 {"mtdmacc3",	XSPR(31,451,220), XSPR_MASK, PPC403,	PPCNONE,	{RS}},
 {"mtdmasr",	XSPR(31,451,224), XSPR_MASK, PPC403,	PPCNONE,	{RS}},
-{"mtdcr",	X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, TITAN,	{SPR, RS}},
+{"mtdcr",	X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, TITAN,	{SPR, RS}},
 {"mtdcr.",	XRC(31,451,1), X_MASK,       PPCA2,	PPCNONE,	{SPR, RS}},
 
 {"dccci",	X(31,454), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}},
-{"dci",		X(31,454),	XRARB_MASK, PPCA2|PPC476, PPCNONE,	{CT}},
+{"dci",		X(31,454),	XRARB_MASK, PPCA2|PPC476|PPCVLE, PPCNONE,	{CT}},
 
-{"divdu",	XO(31,457,0,0),	XO_MASK,     PPC64,	PPCNONE,	{RT, RA, RB}},
-{"divdu.",	XO(31,457,0,1),	XO_MASK,     PPC64,	PPCNONE,	{RT, RA, RB}},
+{"divdu",	XO(31,457,0,0),	XO_MASK,  PPC64|PPCVLE,	PPCNONE,	{RT, RA, RB}},
+{"divdu.",	XO(31,457,0,1),	XO_MASK,  PPC64|PPCVLE,	PPCNONE,	{RT, RA, RB}},
 
-{"divwu",	XO(31,459,0,0),	XO_MASK,     PPC,	PPCNONE,	{RT, RA, RB}},
-{"divwu.",	XO(31,459,0,1),	XO_MASK,     PPC,	PPCNONE,	{RT, RA, RB}},
+{"divwu",	XO(31,459,0,0),	XO_MASK,  PPC|PPCVLE,	PPCNONE,	{RT, RA, RB}},
+{"divwu.",	XO(31,459,0,1),	XO_MASK,  PPC|PPCVLE,	PPCNONE,	{RT, RA, RB}},
 
-{"mtpmr",	X(31,462),	X_MASK, PPCPMR|PPCE300,	PPCNONE,	{PMR, RS}},
+{"mtpmr",	X(31,462),  X_MASK, PPCPMR|PPCE300|PPCVLE, PPCNONE,	{PMR, RS}},
 
 {"mtmq",	XSPR(31,467,  0), XSPR_MASK, M601,	PPCNONE,	{RS}},
-{"mtxer",	XSPR(31,467,  1), XSPR_MASK, COM,	PPCNONE,	{RS}},
-{"mtlr",	XSPR(31,467,  8), XSPR_MASK, COM,	PPCNONE,	{RS}},
-{"mtctr", 	XSPR(31,467,  9), XSPR_MASK, COM,	PPCNONE,	{RS}},
+{"mtxer",	XSPR(31,467,  1), XSPR_MASK, COM|PPCVLE,	PPCNONE,	{RS}},
+{"mtlr",	XSPR(31,467,  8), XSPR_MASK, COM|PPCVLE,	PPCNONE,	{RS}},
+{"mtctr", 	XSPR(31,467,  9), XSPR_MASK, COM|PPCVLE,	PPCNONE,	{RS}},
 {"mttid",	XSPR(31,467, 17), XSPR_MASK, POWER,	PPCNONE,	{RS}},
 {"mtdsisr",	XSPR(31,467, 18), XSPR_MASK, COM,	TITAN,  	{RS}},
 {"mtdar",	XSPR(31,467, 19), XSPR_MASK, COM,	TITAN,  	{RS}},
@@ -4291,16 +5121,16 @@ const struct powerpc_opcode powerpc_opco
 {"mtdec",	XSPR(31,467, 22), XSPR_MASK, COM,	PPCNONE,	{RS}},
 {"mtsdr0",	XSPR(31,467, 24), XSPR_MASK, POWER,	PPCNONE,	{RS}},
 {"mtsdr1",	XSPR(31,467, 25), XSPR_MASK, COM,	TITAN,  	{RS}},
-{"mtsrr0",	XSPR(31,467, 26), XSPR_MASK, COM,	PPCNONE,	{RS}},
-{"mtsrr1",	XSPR(31,467, 27), XSPR_MASK, COM,	PPCNONE,	{RS}},
+{"mtsrr0",	XSPR(31,467, 26), XSPR_MASK, COM|PPCVLE,PPCNONE,	{RS}},
+{"mtsrr1",	XSPR(31,467, 27), XSPR_MASK, COM|PPCVLE,PPCNONE,	{RS}},
 {"mtcfar",	XSPR(31,467, 28), XSPR_MASK, POWER6,	PPCNONE,	{RS}},
-{"mtpid",	XSPR(31,467, 48), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
-{"mtdecar",	XSPR(31,467, 54), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
-{"mtcsrr0",	XSPR(31,467, 58), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
-{"mtcsrr1",	XSPR(31,467, 59), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
-{"mtdear",	XSPR(31,467, 61), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
-{"mtesr",	XSPR(31,467, 62), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
-{"mtivpr",	XSPR(31,467, 63), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
+{"mtpid",	XSPR(31,467, 48), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
+{"mtdecar",	XSPR(31,467, 54), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
+{"mtcsrr0",	XSPR(31,467, 58), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
+{"mtcsrr1",	XSPR(31,467, 59), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
+{"mtdear",	XSPR(31,467, 61), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
+{"mtesr",	XSPR(31,467, 62), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
+{"mtivpr",	XSPR(31,467, 63), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
 {"mtcmpa",	XSPR(31,467,144), XSPR_MASK, PPC860,	PPCNONE,	{RS}},
 {"mtcmpb",	XSPR(31,467,145), XSPR_MASK, PPC860,	PPCNONE,	{RS}},
 {"mtcmpc",	XSPR(31,467,146), XSPR_MASK, PPC860,	PPCNONE,	{RS}},
@@ -4318,50 +5148,50 @@ const struct powerpc_opcode powerpc_opco
 {"mtictrl",	XSPR(31,467,158), XSPR_MASK, PPC860,	PPCNONE,	{RS}},
 {"mtbar",	XSPR(31,467,159), XSPR_MASK, PPC860,	PPCNONE,	{RS}},
 {"mtvrsave",	XSPR(31,467,256), XSPR_MASK, PPCVEC,	PPCNONE,	{RS}},
-{"mtusprg0",	XSPR(31,467,256), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
-{"mtsprg",	XSPR(31,467,256), XSPRG_MASK,PPC,	PPCNONE,	{SPRG, RS}},
-{"mtsprg0",	XSPR(31,467,272), XSPR_MASK, PPC,	PPCNONE,	{RS}},
-{"mtsprg1",	XSPR(31,467,273), XSPR_MASK, PPC,	PPCNONE,	{RS}},
-{"mtsprg2",	XSPR(31,467,274), XSPR_MASK, PPC,	PPCNONE,	{RS}},
-{"mtsprg3",	XSPR(31,467,275), XSPR_MASK, PPC,	PPCNONE,	{RS}},
-{"mtsprg4",	XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, PPCNONE,	{RS}},
-{"mtsprg5",	XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, PPCNONE,	{RS}},
-{"mtsprg6",	XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, PPCNONE,	{RS}},
-{"mtsprg7",	XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, PPCNONE,	{RS}},
+{"mtusprg0",	XSPR(31,467,256), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
+{"mtsprg",	XSPR(31,467,256), XSPRG_MASK,PPC|PPCVLE,	PPCNONE,	{SPRG, RS}},
+{"mtsprg0",	XSPR(31,467,272), XSPR_MASK, PPC|PPCVLE,	PPCNONE,	{RS}},
+{"mtsprg1",	XSPR(31,467,273), XSPR_MASK, PPC|PPCVLE,	PPCNONE,	{RS}},
+{"mtsprg2",	XSPR(31,467,274), XSPR_MASK, PPC|PPCVLE,	PPCNONE,	{RS}},
+{"mtsprg3",	XSPR(31,467,275), XSPR_MASK, PPC|PPCVLE,	PPCNONE,	{RS}},
+{"mtsprg4",	XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE,	{RS}},
+{"mtsprg5",	XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE,	{RS}},
+{"mtsprg6",	XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE,	{RS}},
+{"mtsprg7",	XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE|PPCVLE, PPCNONE,	{RS}},
 {"mtasr",	XSPR(31,467,280), XSPR_MASK, PPC64,	PPCNONE,	{RS}},
 {"mtear",	XSPR(31,467,282), XSPR_MASK, PPC,	TITAN,  	{RS}},
 {"mttbl",	XSPR(31,467,284), XSPR_MASK, PPC,	PPCNONE,	{RS}},
 {"mttbu",	XSPR(31,467,285), XSPR_MASK, PPC,	PPCNONE,	{RS}},
-{"mtdbsr",	XSPR(31,467,304), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
-{"mtdbcr0",	XSPR(31,467,308), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
-{"mtdbcr1",	XSPR(31,467,309), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
-{"mtdbcr2",	XSPR(31,467,310), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
-{"mtiac1",	XSPR(31,467,312), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
-{"mtiac2",	XSPR(31,467,313), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
-{"mtiac3",	XSPR(31,467,314), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
-{"mtiac4",	XSPR(31,467,315), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
-{"mtdac1",	XSPR(31,467,316), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
-{"mtdac2",	XSPR(31,467,317), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
-{"mtdvc1",	XSPR(31,467,318), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
-{"mtdvc2",	XSPR(31,467,319), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
-{"mttsr",	XSPR(31,467,336), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
-{"mttcr",	XSPR(31,467,340), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
-{"mtivor0",	XSPR(31,467,400), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
-{"mtivor1",	XSPR(31,467,401), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
-{"mtivor2",	XSPR(31,467,402), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
-{"mtivor3",	XSPR(31,467,403), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
-{"mtivor4",	XSPR(31,467,404), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
-{"mtivor5",	XSPR(31,467,405), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
-{"mtivor6",	XSPR(31,467,406), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
-{"mtivor7",	XSPR(31,467,407), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
-{"mtivor8",	XSPR(31,467,408), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
-{"mtivor9",	XSPR(31,467,409), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
-{"mtivor10",	XSPR(31,467,410), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
-{"mtivor11",	XSPR(31,467,411), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
-{"mtivor12",	XSPR(31,467,412), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
-{"mtivor13",	XSPR(31,467,413), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
-{"mtivor14",	XSPR(31,467,414), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
-{"mtivor15",	XSPR(31,467,415), XSPR_MASK, BOOKE,	PPCNONE,	{RS}},
+{"mtdbsr",	XSPR(31,467,304), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
+{"mtdbcr0",	XSPR(31,467,308), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
+{"mtdbcr1",	XSPR(31,467,309), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
+{"mtdbcr2",	XSPR(31,467,310), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
+{"mtiac1",	XSPR(31,467,312), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
+{"mtiac2",	XSPR(31,467,313), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
+{"mtiac3",	XSPR(31,467,314), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
+{"mtiac4",	XSPR(31,467,315), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
+{"mtdac1",	XSPR(31,467,316), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
+{"mtdac2",	XSPR(31,467,317), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
+{"mtdvc1",	XSPR(31,467,318), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
+{"mtdvc2",	XSPR(31,467,319), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
+{"mttsr",	XSPR(31,467,336), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
+{"mttcr",	XSPR(31,467,340), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
+{"mtivor0",	XSPR(31,467,400), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
+{"mtivor1",	XSPR(31,467,401), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
+{"mtivor2",	XSPR(31,467,402), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
+{"mtivor3",	XSPR(31,467,403), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
+{"mtivor4",	XSPR(31,467,404), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
+{"mtivor5",	XSPR(31,467,405), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
+{"mtivor6",	XSPR(31,467,406), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
+{"mtivor7",	XSPR(31,467,407), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
+{"mtivor8",	XSPR(31,467,408), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
+{"mtivor9",	XSPR(31,467,409), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
+{"mtivor10",	XSPR(31,467,410), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
+{"mtivor11",	XSPR(31,467,411), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
+{"mtivor12",	XSPR(31,467,412), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
+{"mtivor13",	XSPR(31,467,413), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
+{"mtivor14",	XSPR(31,467,414), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
+{"mtivor15",	XSPR(31,467,415), XSPR_MASK, BOOKE|PPCVLE,	PPCNONE,	{RS}},
 {"mtspefscr",	XSPR(31,467,512), XSPR_MASK, PPCSPE,	PPCNONE,	{RS}},
 {"mtbbear",	XSPR(31,467,513), XSPR_MASK, PPCBRLK,	PPCNONE,	{RS}},
 {"mtbbtar",	XSPR(31,467,514), XSPR_MASK, PPCBRLK,	PPCNONE,	{RS}},
@@ -4373,9 +5203,10 @@ const struct powerpc_opcode powerpc_opco
 {"mtivor35",	XSPR(31,467,531), XSPR_MASK, PPCPMR,	PPCNONE,	{RS}},
 {"mtdbatu",	XSPR(31,467,536), XSPRBAT_MASK, PPC,	TITAN,  	{SPRBAT, RS}},
 {"mtdbatl",	XSPR(31,467,537), XSPRBAT_MASK, PPC,	TITAN,  	{SPRBAT, RS}},
-{"mtmcsrr0",	XSPR(31,467,570), XSPR_MASK, PPCRFMCI,	PPCNONE,	{RS}},
-{"mtmcsrr1",	XSPR(31,467,571), XSPR_MASK, PPCRFMCI,	PPCNONE,	{RS}},
+{"mtmcsrr0",	XSPR(31,467,570), XSPR_MASK, PPCRFMCI|PPCVLE,	PPCNONE,	{RS}},
+{"mtmcsrr1",	XSPR(31,467,571), XSPR_MASK, PPCRFMCI|PPCVLE,	PPCNONE,	{RS}},
 {"mtmcsr",	XSPR(31,467,572), XSPR_MASK, PPCRFMCI,	PPCNONE,	{RS}},
+{"mtmas1",	XSPR(31,467,625), XSPR_MASK, PPCVLE,	PPCNONE,	{RS}},
 {"mtivndx",	XSPR(31,467,880), XSPR_MASK, TITAN,	PPCNONE,	{RS}},
 {"mtdvndx",	XSPR(31,467,881), XSPR_MASK, TITAN,	PPCNONE,	{RS}},
 {"mtivlim",	XSPR(31,467,882), XSPR_MASK, TITAN,	PPCNONE,	{RS}},
@@ -4439,29 +5270,29 @@ const struct powerpc_opcode powerpc_opco
 {"mtpbl2",	XSPR(31,467,1022), XSPR_MASK, PPC403,	PPCNONE,	{RS}},
 {"mtthrm3",	XSPR(31,467,1022), XSPR_MASK, PPC750,	PPCNONE,	{RS}},
 {"mtpbu2",	XSPR(31,467,1023), XSPR_MASK, PPC403,	PPCNONE,	{RS}},
-{"mtspr",	X(31,467),	  X_MASK,    COM,	PPCNONE,	{SPR, RS}},
+{"mtspr",	X(31,467),	  X_MASK,  COM|PPCVLE,	PPCNONE,	{SPR, RS}},
 
-{"dcbi",	X(31,470),	XRT_MASK,    PPC,	PPCNONE,	{RA, RB}},
+{"dcbi",	X(31,470),	XRT_MASK,  PPC|PPCVLE,	PPCNONE,	{RA, RB}},
 
-{"nand",	XRC(31,476,0),	X_MASK,      COM,	PPCNONE,	{RA, RS, RB}},
-{"nand.",	XRC(31,476,1),	X_MASK,      COM,	PPCNONE,	{RA, RS, RB}},
+{"nand",	XRC(31,476,0),	X_MASK,    COM|PPCVLE,	PPCNONE,	{RA, RS, RB}},
+{"nand.",	XRC(31,476,1),	X_MASK,    COM|PPCVLE,	PPCNONE,	{RA, RS, RB}},
 
 {"dsn", 	X(31,483),	XRT_MASK,    E500MC,	PPCNONE,	{RA, RB}},
 
 {"dcread",	X(31,486),	X_MASK,  PPC403|PPC440,	PPCA2|PPC476,	{RT, RA, RB}},
 
-{"icbtls",	X(31,486),	X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE,	{CT, RA, RB}},
+{"icbtls",	X(31,486),	X_MASK, PPCCHLK|PPC476|TITAN|PPCVLE, PPCNONE,	{CT, RA, RB}},
 
 {"stvxl",	X(31,487),	X_MASK,      PPCVEC,	PPCNONE,	{VS, RA, RB}},
 
 {"nabs",	XO(31,488,0,0),	XORB_MASK,   M601,	PPCNONE,	{RT, RA}},
 {"nabs.",	XO(31,488,0,1),	XORB_MASK,   M601,	PPCNONE,	{RT, RA}},
 
-{"divd",	XO(31,489,0,0),	XO_MASK,     PPC64,	PPCNONE,	{RT, RA, RB}},
-{"divd.",	XO(31,489,0,1),	XO_MASK,     PPC64,	PPCNONE,	{RT, RA, RB}},
+{"divd",	XO(31,489,0,0),	XO_MASK,  PPC64|PPCVLE,	PPCNONE,	{RT, RA, RB}},
+{"divd.",	XO(31,489,0,1),	XO_MASK,  PPC64|PPCVLE,	PPCNONE,	{RT, RA, RB}},
 
-{"divw",	XO(31,491,0,0),	XO_MASK,     PPC,	PPCNONE,	{RT, RA, RB}},
-{"divw.",	XO(31,491,0,1),	XO_MASK,     PPC,	PPCNONE,	{RT, RA, RB}},
+{"divw",	XO(31,491,0,0),	XO_MASK,    PPC|PPCVLE,	PPCNONE,	{RT, RA, RB}},
+{"divw.",	XO(31,491,0,1),	XO_MASK,    PPC|PPCVLE,	PPCNONE,	{RT, RA, RB}},
 
 {"icbtlse",	X(31,494),	X_MASK,      PPCCHLK,	PPCNONE,	{CT, RA, RB}},
 
@@ -4473,7 +5304,7 @@ const struct powerpc_opcode powerpc_opco
 
 {"cmpb",	X(31,508),	X_MASK, POWER6|PPCA2|PPC476, PPCNONE,	{RA, RS, RB}},
 
-{"mcrxr",	X(31,512), XRARB_MASK|(3<<21), COM,	POWER7,		{BF}},
+{"mcrxr",	X(31,512), XRARB_MASK|(3<<21), COM|PPCVLE, POWER7,	{BF}},
 
 {"lbdx",	X(31,515),	X_MASK,      E500MC,	PPCNONE,	{RT, RA, RB}},
 
@@ -4482,40 +5313,40 @@ const struct powerpc_opcode powerpc_opco
 {"lvlx",	X(31,519),	X_MASK,      CELL,	PPCNONE,	{VD, RA0, RB}},
 {"lbfcmux",	APU(31,519,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
 
-{"subfco",	XO(31,8,1,0),	XO_MASK,     PPCCOM,	PPCNONE,	{RT, RA, RB}},
+{"subfco",	XO(31,8,1,0),	XO_MASK, PPCCOM|PPCVLE,	PPCNONE,	{RT, RA, RB}},
 {"sfo",		XO(31,8,1,0),	XO_MASK,     PWRCOM,	PPCNONE,	{RT, RA, RB}},
-{"subco",	XO(31,8,1,0),	XO_MASK,     PPCCOM,	PPCNONE,	{RT, RB, RA}},
-{"subfco.",	XO(31,8,1,1),	XO_MASK,     PPCCOM,	PPCNONE,	{RT, RA, RB}},
+{"subco",	XO(31,8,1,0),	XO_MASK, PPCCOM|PPCVLE,	PPCNONE,	{RT, RB, RA}},
+{"subfco.",	XO(31,8,1,1),	XO_MASK, PPCCOM|PPCVLE,	PPCNONE,	{RT, RA, RB}},
 {"sfo.",	XO(31,8,1,1),	XO_MASK,     PWRCOM,	PPCNONE,	{RT, RA, RB}},
-{"subco.",	XO(31,8,1,1),	XO_MASK,     PPCCOM,	PPCNONE,	{RT, RB, RA}},
+{"subco.",	XO(31,8,1,1),	XO_MASK, PPCCOM|PPCVLE,	PPCNONE,	{RT, RB, RA}},
 
-{"addco",	XO(31,10,1,0),	XO_MASK,     PPCCOM,	PPCNONE,	{RT, RA, RB}},
+{"addco",	XO(31,10,1,0),	XO_MASK, PPCCOM|PPCVLE,	PPCNONE,	{RT, RA, RB}},
 {"ao",		XO(31,10,1,0),	XO_MASK,     PWRCOM,	PPCNONE,	{RT, RA, RB}},
-{"addco.",	XO(31,10,1,1),	XO_MASK,     PPCCOM,	PPCNONE,	{RT, RA, RB}},
+{"addco.",	XO(31,10,1,1),	XO_MASK, PPCCOM|PPCVLE,	PPCNONE,	{RT, RA, RB}},
 {"ao.",		XO(31,10,1,1),	XO_MASK,     PWRCOM,	PPCNONE,	{RT, RA, RB}},
 
 {"clcs",	X(31,531),	XRB_MASK,    M601,	PPCNONE,	{RT, RA}},
 
 {"ldbrx",	X(31,532),	X_MASK, CELL|POWER7|PPCA2, PPCNONE,	{RT, RA0, RB}},
 
-{"lswx",	X(31,533),	X_MASK,      PPCCOM,	E500|E500MC,	{RT, RAX, RBX}},
+{"lswx",	X(31,533),	X_MASK,  PPCCOM|PPCVLE,	E500|E500MC,	{RT, RA0, RBX}},
 {"lsx",		X(31,533),	X_MASK,      PWRCOM,	PPCNONE,	{RT, RA, RB}},
 
-{"lwbrx",	X(31,534),	X_MASK,      PPCCOM,	PPCNONE,	{RT, RA0, RB}},
+{"lwbrx",	X(31,534),	X_MASK,  PPCCOM|PPCVLE,	PPCNONE,	{RT, RA0, RB}},
 {"lbrx",	X(31,534),	X_MASK,      PWRCOM,	PPCNONE,	{RT, RA, RB}},
 
 {"lfsx",	X(31,535),	X_MASK,      COM,	PPCEFS,		{FRT, RA0, RB}},
 
-{"srw",		XRC(31,536,0),	X_MASK,      PPCCOM,	PPCNONE,	{RA, RS, RB}},
+{"srw",		XRC(31,536,0),	X_MASK,  PPCCOM|PPCVLE,	PPCNONE,	{RA, RS, RB}},
 {"sr",		XRC(31,536,0),	X_MASK,      PWRCOM,	PPCNONE,	{RA, RS, RB}},
-{"srw.",	XRC(31,536,1),	X_MASK,      PPCCOM,	PPCNONE,	{RA, RS, RB}},
+{"srw.",	XRC(31,536,1),	X_MASK,  PPCCOM|PPCVLE,	PPCNONE,	{RA, RS, RB}},
 {"sr.",		XRC(31,536,1),	X_MASK,      PWRCOM,	PPCNONE,	{RA, RS, RB}},
 
 {"rrib",	XRC(31,537,0),	X_MASK,      M601,	PPCNONE,	{RA, RS, RB}},
 {"rrib.",	XRC(31,537,1),	X_MASK,      M601,	PPCNONE,	{RA, RS, RB}},
 
-{"srd",		XRC(31,539,0),	X_MASK,      PPC64,	PPCNONE,	{RA, RS, RB}},
-{"srd.",	XRC(31,539,1),	X_MASK,      PPC64,	PPCNONE,	{RA, RS, RB}},
+{"srd",		XRC(31,539,0),	X_MASK,  PPC64|PPCVLE,	PPCNONE,	{RA, RS, RB}},
+{"srd.",	XRC(31,539,1),	X_MASK,  PPC64|PPCVLE,	PPCNONE,	{RA, RS, RB}},
 
 {"maskir",	XRC(31,541,0),	X_MASK,      M601,	PPCNONE,	{RA, RS, RB}},
 {"maskir.",	XRC(31,541,1),	X_MASK,      M601,	PPCNONE,	{RA, RS, RB}},
@@ -4527,12 +5358,12 @@ const struct powerpc_opcode powerpc_opco
 {"lvrx",	X(31,551),	X_MASK,      CELL,	PPCNONE,	{VD, RA0, RB}},
 {"lhfcmux",	APU(31,551,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
 
-{"subfo",	XO(31,40,1,0),	XO_MASK,     PPC,	PPCNONE,	{RT, RA, RB}},
-{"subo",	XO(31,40,1,0),	XO_MASK,     PPC,	PPCNONE,	{RT, RB, RA}},
-{"subfo.",	XO(31,40,1,1),	XO_MASK,     PPC,	PPCNONE,	{RT, RA, RB}},
-{"subo.",	XO(31,40,1,1),	XO_MASK,     PPC,	PPCNONE,	{RT, RB, RA}},
+{"subfo",	XO(31,40,1,0),	XO_MASK,  PPC|PPCVLE,	PPCNONE,	{RT, RA, RB}},
+{"subo",	XO(31,40,1,0),	XO_MASK,  PPC|PPCVLE,	PPCNONE,	{RT, RB, RA}},
+{"subfo.",	XO(31,40,1,1),	XO_MASK,  PPC|PPCVLE,	PPCNONE,	{RT, RA, RB}},
+{"subo.",	XO(31,40,1,1),	XO_MASK,  PPC|PPCVLE,	PPCNONE,	{RT, RB, RA}},
 
-{"tlbsync",	X(31,566),	0xffffffff,  PPC,	PPCNONE,	{0}},
+{"tlbsync",	X(31,566),	0xffffffff, PPC|PPCVLE,	PPCNONE,	{0}},
 
 {"lfsux",	X(31,567),	X_MASK,      COM,	PPCEFS,		{FRT, RAS, RB}},
 
@@ -4544,13 +5375,13 @@ const struct powerpc_opcode powerpc_opco
 
 {"mfsr",	X(31,595), XRB_MASK|(1<<20), COM,	NON32,  	{RT, SR}},
 
-{"lswi",	X(31,597),	X_MASK,      PPCCOM,	E500|E500MC,	{RT, RA0, NBI}},
+{"lswi",	X(31,597),	X_MASK,  PPCCOM|PPCVLE,	E500|E500MC,	{RT, RA0, NBI}},
 {"lsi",		X(31,597),	X_MASK,      PWRCOM,	PPCNONE,	{RT, RA0, NB}},
 
 {"lwsync",	XSYNC(31,598,1), 0xffffffff, PPC,	E500,		{0}},
 {"ptesync",	XSYNC(31,598,2), 0xffffffff, PPC64,	PPCNONE,	{0}},
-{"sync",	X(31,598),	XSYNC_MASK,  PPCCOM,	BOOKE|PPC476,	{LS}},
-{"msync",	X(31,598),	0xffffffff, BOOKE|PPCA2|PPC476, PPCNONE, {0}},
+{"sync",	X(31,598),	XSYNC_MASK,  PPCCOM|PPCVLE, BOOKE|PPC476,	{LS}},
+{"msync",	X(31,598),	0xffffffff, BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {0}},
 {"sync",	X(31,598),	0xffffffff, BOOKE|PPC476, PPCNONE, {0}},
 {"lwsync",	X(31,598),	0xffffffff, E500,	PPCNONE,	{0}},
 {"dcs",		X(31,598),	0xffffffff,  PWRCOM,	PPCNONE,	{0}},
@@ -4558,14 +5389,14 @@ const struct powerpc_opcode powerpc_opco
 {"lfdx",	X(31,599),	X_MASK,      COM,	PPCEFS,		{FRT, RA0, RB}},
 
 {"mffgpr",	XRC(31,607,0),	XRA_MASK,    POWER6,	POWER7,		{FRT, RB}},
-{"lfdepx",	X(31,607),	X_MASK,   E500MC|PPCA2,	PPCNONE,	{FRT, RA, RB}},
+{"lfdepx",	X(31,607),	X_MASK,   E500MC|PPCA2|PPCVLE,	PPCNONE,	{FRT, RA, RB}},
 
 {"lddx",	X(31,611),	X_MASK,      E500MC,	PPCNONE,	{RT, RA, RB}},
 
 {"lqfcmux",	APU(31,615,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
 
-{"nego",	XO(31,104,1,0),	XORB_MASK,   COM,	PPCNONE,	{RT, RA}},
-{"nego.",	XO(31,104,1,1),	XORB_MASK,   COM,	PPCNONE,	{RT, RA}},
+{"nego",	XO(31,104,1,0),	XORB_MASK, COM|PPCVLE,	PPCNONE,	{RT, RA}},
+{"nego.",	XO(31,104,1,1),	XORB_MASK, COM|PPCVLE,	PPCNONE,	{RT, RA}},
 
 {"mulo",	XO(31,107,1,0),	XO_MASK,     M601,	PPCNONE,	{RT, RA, RB}},
 {"mulo.",	XO(31,107,1,1),	XO_MASK,     M601,	PPCNONE,	{RT, RA, RB}},
@@ -4581,24 +5412,24 @@ const struct powerpc_opcode powerpc_opco
 {"stvlx",	X(31,647),	X_MASK,      CELL,	PPCNONE,	{VS, RA0, RB}},
 {"stbfcmux",	APU(31,647,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
 
-{"subfeo",	XO(31,136,1,0),	XO_MASK,     PPCCOM,	PPCNONE,	{RT, RA, RB}},
+{"subfeo",	XO(31,136,1,0),	XO_MASK, PPCCOM|PPCVLE,	PPCNONE,	{RT, RA, RB}},
 {"sfeo",	XO(31,136,1,0),	XO_MASK,     PWRCOM,	PPCNONE,	{RT, RA, RB}},
-{"subfeo.",	XO(31,136,1,1),	XO_MASK,     PPCCOM,	PPCNONE,	{RT, RA, RB}},
+{"subfeo.",	XO(31,136,1,1),	XO_MASK, PPCCOM|PPCVLE,	PPCNONE,	{RT, RA, RB}},
 {"sfeo.",	XO(31,136,1,1),	XO_MASK,     PWRCOM,	PPCNONE,	{RT, RA, RB}},
 
-{"addeo",	XO(31,138,1,0),	XO_MASK,     PPCCOM,	PPCNONE,	{RT, RA, RB}},
+{"addeo",	XO(31,138,1,0),	XO_MASK, PPCCOM|PPCVLE,	PPCNONE,	{RT, RA, RB}},
 {"aeo",		XO(31,138,1,0),	XO_MASK,     PWRCOM,	PPCNONE,	{RT, RA, RB}},
-{"addeo.",	XO(31,138,1,1),	XO_MASK,     PPCCOM,	PPCNONE,	{RT, RA, RB}},
+{"addeo.",	XO(31,138,1,1),	XO_MASK, PPCCOM|PPCVLE,	PPCNONE,	{RT, RA, RB}},
 {"aeo.",	XO(31,138,1,1),	XO_MASK,     PWRCOM,	PPCNONE,	{RT, RA, RB}},
 
 {"mfsrin",	X(31,659),	XRA_MASK,    PPC,	NON32,  	{RT, RB}},
 
 {"stdbrx",	X(31,660),	X_MASK, CELL|POWER7|PPCA2, PPCNONE,	{RS, RA0, RB}},
 
-{"stswx",	X(31,661),	X_MASK,      PPCCOM,	E500|E500MC,	{RS, RA0, RB}},
+{"stswx",	X(31,661),	X_MASK, PPCCOM|PPCVLE,	E500|E500MC,	{RS, RA0, RB}},
 {"stsx",	X(31,661),	X_MASK,      PWRCOM,	PPCNONE,	{RS, RA0, RB}},
 
-{"stwbrx",	X(31,662),	X_MASK,      PPCCOM,	PPCNONE,	{RS, RA0, RB}},
+{"stwbrx",	X(31,662),	X_MASK, PPCCOM|PPCVLE,	PPCNONE,	{RS, RA0, RB}},
 {"stbrx",	X(31,662),	X_MASK,      PWRCOM,	PPCNONE,	{RS, RA0, RB}},
 
 {"stfsx",	X(31,663),	X_MASK,      COM,	PPCEFS,		{FRS, RA0, RB}},
@@ -4627,17 +5458,17 @@ const struct powerpc_opcode powerpc_opco
 
 {"stxsdx",	X(31,716),	XX1_MASK,    PPCVSX,	PPCNONE,	{XS6, RA, RB}},
 
-{"subfzeo",	XO(31,200,1,0),	XORB_MASK,   PPCCOM,	PPCNONE,	{RT, RA}},
+{"subfzeo",	XO(31,200,1,0),	XORB_MASK, PPCCOM|PPCVLE, PPCNONE,	{RT, RA}},
 {"sfzeo",	XO(31,200,1,0),	XORB_MASK,   PWRCOM,	PPCNONE,	{RT, RA}},
-{"subfzeo.",	XO(31,200,1,1),	XORB_MASK,   PPCCOM,	PPCNONE,	{RT, RA}},
+{"subfzeo.",	XO(31,200,1,1),	XORB_MASK, PPCCOM|PPCVLE, PPCNONE,	{RT, RA}},
 {"sfzeo.",	XO(31,200,1,1),	XORB_MASK,   PWRCOM,	PPCNONE,	{RT, RA}},
 
-{"addzeo",	XO(31,202,1,0),	XORB_MASK,   PPCCOM,	PPCNONE,	{RT, RA}},
+{"addzeo",	XO(31,202,1,0),	XORB_MASK, PPCCOM|PPCVLE, PPCNONE,	{RT, RA}},
 {"azeo",	XO(31,202,1,0),	XORB_MASK,   PWRCOM,	PPCNONE,	{RT, RA}},
-{"addzeo.",	XO(31,202,1,1),	XORB_MASK,   PPCCOM,	PPCNONE,	{RT, RA}},
+{"addzeo.",	XO(31,202,1,1),	XORB_MASK, PPCCOM|PPCVLE, PPCNONE,	{RT, RA}},
 {"azeo.",	XO(31,202,1,1),	XORB_MASK,   PWRCOM,	PPCNONE,	{RT, RA}},
 
-{"stswi",	X(31,725),	X_MASK,      PPCCOM,	E500|E500MC,	{RS, RA0, NB}},
+{"stswi",	X(31,725),	X_MASK,   PPCCOM|PPCVLE, E500|E500MC,	{RS, RA0, NB}},
 {"stsi",	X(31,725),	X_MASK,      PWRCOM,	PPCNONE,	{RS, RA0, NB}},
 
 {"sthcx.",	XRC(31,726,1),	X_MASK,      POWER7,	PPCNONE,	{RS, RA0, RB}},
@@ -4651,23 +5482,23 @@ const struct powerpc_opcode powerpc_opco
 {"sreq.",	XRC(31,729,1),	X_MASK,      M601,	PPCNONE,	{RA, RS, RB}},
 
 {"mftgpr",	XRC(31,735,0),	XRA_MASK,    POWER6,	POWER7,		{RT, FRB}},
-{"stfdepx",	X(31,735),	X_MASK,   E500MC|PPCA2,	PPCNONE,	{FRS, RA, RB}},
+{"stfdepx",	X(31,735),	X_MASK,   E500MC|PPCA2|PPCVLE,	PPCNONE,	{FRS, RA, RB}},
 
 {"stddx",	X(31,739),	X_MASK,      E500MC,	PPCNONE,	{RS, RA, RB}},
 
 {"stqfcmux",	APU(31,743,0), 	APU_MASK,    PPC405,	PPCNONE,	{FCRT, RA, RB}},
 
-{"subfmeo",	XO(31,232,1,0),	XORB_MASK,   PPCCOM,	PPCNONE,	{RT, RA}},
+{"subfmeo",	XO(31,232,1,0),	XORB_MASK, PPCCOM|PPCVLE, PPCNONE,	{RT, RA}},
 {"sfmeo",	XO(31,232,1,0),	XORB_MASK,   PWRCOM,	PPCNONE,	{RT, RA}},
-{"subfmeo.",	XO(31,232,1,1),	XORB_MASK,   PPCCOM,	PPCNONE,	{RT, RA}},
+{"subfmeo.",	XO(31,232,1,1),	XORB_MASK, PPCCOM|PPCVLE, PPCNONE,	{RT, RA}},
 {"sfmeo.",	XO(31,232,1,1),	XORB_MASK,   PWRCOM,	PPCNONE,	{RT, RA}},
 
-{"mulldo",	XO(31,233,1,0),	XO_MASK,     PPC64,	PPCNONE,	{RT, RA, RB}},
-{"mulldo.",	XO(31,233,1,1),	XO_MASK,     PPC64,	PPCNONE,	{RT, RA, RB}},
+{"mulldo",	XO(31,233,1,0),	XO_MASK,  PPC64|PPCVLE,	PPCNONE,	{RT, RA, RB}},
+{"mulldo.",	XO(31,233,1,1),	XO_MASK,  PPC64|PPCVLE,	PPCNONE,	{RT, RA, RB}},
 
-{"addmeo",	XO(31,234,1,0),	XORB_MASK,   PPCCOM,	PPCNONE,	{RT, RA}},
+{"addmeo",	XO(31,234,1,0),	XORB_MASK, PPCCOM|PPCVLE, PPCNONE,	{RT, RA}},
 {"ameo",	XO(31,234,1,0),	XORB_MASK,   PWRCOM,	PPCNONE,	{RT, RA}},
-{"addmeo.",	XO(31,234,1,1),	XORB_MASK,   PPCCOM,	PPCNONE,	{RT, RA}},
+{"addmeo.",	XO(31,234,1,1),	XORB_MASK, PPCCOM|PPCVLE, PPCNONE,	{RT, RA}},
 {"ameo.",	XO(31,234,1,1),	XORB_MASK,   PWRCOM,	PPCNONE,	{RT, RA}},
 
 {"mullwo",	XO(31,235,1,0),	XO_MASK,     PPCCOM,	PPCNONE,	{RT, RA, RB}},
@@ -4675,7 +5506,7 @@ const struct powerpc_opcode powerpc_opco
 {"mullwo.",	XO(31,235,1,1),	XO_MASK,     PPCCOM,	PPCNONE,	{RT, RA, RB}},
 {"mulso.",	XO(31,235,1,1),	XO_MASK,     PWRCOM,	PPCNONE,	{RT, RA, RB}},
 
-{"dcba",	X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, PPCNONE, {RA, RB}},
+{"dcba",	X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RA, RB}},
 {"dcbal",	XOPL(31,758,1), XRT_MASK,    E500MC,	PPCNONE,	{RA, RB}},
 
 {"stfdux",	X(31,759),	X_MASK,      COM,	PPCEFS,		{FRS, RAS, RB}},
@@ -4689,14 +5520,14 @@ const struct powerpc_opcode powerpc_opco
 {"dozo",	XO(31,264,1,0),	XO_MASK,     M601,	PPCNONE,	{RT, RA, RB}},
 {"dozo.",	XO(31,264,1,1),	XO_MASK,     M601,	PPCNONE,	{RT, RA, RB}},
 
-{"addo",	XO(31,266,1,0),	XO_MASK,     PPCCOM,	PPCNONE,	{RT, RA, RB}},
+{"addo",	XO(31,266,1,0),	XO_MASK, PPCCOM|PPCVLE, PPCNONE,	{RT, RA, RB}},
 {"caxo",	XO(31,266,1,0),	XO_MASK,     PWRCOM,	PPCNONE,	{RT, RA, RB}},
-{"addo.",	XO(31,266,1,1),	XO_MASK,     PPCCOM,	PPCNONE,	{RT, RA, RB}},
+{"addo.",	XO(31,266,1,1),	XO_MASK, PPCCOM|PPCVLE,	PPCNONE,	{RT, RA, RB}},
 {"caxo.",	XO(31,266,1,1),	XO_MASK,     PWRCOM,	PPCNONE,	{RT, RA, RB}},
 
 {"lxvw4x",	X(31,780),	XX1_MASK,    PPCVSX,	PPCNONE,	{XT6, RA, RB}},
 
-{"tlbivax",	X(31,786),	XRT_MASK,  BOOKE|PPCA2|PPC476, PPCNONE,	{RA, RB}},
+{"tlbivax",	X(31,786),	XRT_MASK,  BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE,	{RA, RB}},
 
 {"lwzcix",	X(31,789),	X_MASK,      POWER6,	PPCNONE,	{RT, RA0, RB}},
 
@@ -4705,9 +5536,9 @@ const struct powerpc_opcode powerpc_opco
 {"lfdpx",	X(31,791),	X_MASK,      POWER6,	POWER7,		{FRTp, RA, RB}},
 {"lfqx",	X(31,791),	X_MASK,      POWER2,	PPCNONE,	{FRT, RA, RB}},
 
-{"sraw",	XRC(31,792,0),	X_MASK,      PPCCOM,	PPCNONE,	{RA, RS, RB}},
+{"sraw",	XRC(31,792,0),	X_MASK,  PPCCOM|PPCVLE,	PPCNONE,	{RA, RS, RB}},
 {"sra",		XRC(31,792,0),	X_MASK,      PWRCOM,	PPCNONE,	{RA, RS, RB}},
-{"sraw.",	XRC(31,792,1),	X_MASK,      PPCCOM,	PPCNONE,	{RA, RS, RB}},
+{"sraw.",	XRC(31,792,1),	X_MASK,  PPCCOM|PPCVLE,	PPCNONE,	{RA, RS, RB}},
 {"sra.",	XRC(31,792,1),	X_MASK,      PWRCOM,	PPCNONE,	{RA, RS, RB}},
 
 {"srad",	XRC(31,794,0),	X_MASK,      PPC64,	PPCNONE,	{RA, RS, RB}},
@@ -4727,13 +5558,13 @@ const struct powerpc_opcode powerpc_opco
 
 {"lfqux",	X(31,823),	X_MASK,      POWER2,	PPCNONE,	{FRT, RA, RB}},
 
-{"srawi",	XRC(31,824,0),	X_MASK,      PPCCOM,	PPCNONE,	{RA, RS, SH}},
+{"srawi",	XRC(31,824,0),	X_MASK,  PPCCOM|PPCVLE,	PPCNONE,	{RA, RS, SH}},
 {"srai",	XRC(31,824,0),	X_MASK,      PWRCOM,	PPCNONE,	{RA, RS, SH}},
-{"srawi.",	XRC(31,824,1),	X_MASK,      PPCCOM,	PPCNONE,	{RA, RS, SH}},
-{"srai.",	XRC(31,824,1),	X_MASK,      PWRCOM,	PPCNONE,	{RA, RS, SH}},
+{"srawi.",	XRC(31,824,1),	X_MASK,  PPCCOM|PPCVLE,	PPCNONE,	{RA, RS, SH}},
+{"srai.",	XRC(31,824,1),	X_MASK,	     PWRCOM,	PPCNONE,	{RA, RS, SH}},
 
-{"sradi",	XS(31,413,0),	XS_MASK,     PPC64,	PPCNONE,	{RA, RS, SH6}},
-{"sradi.",	XS(31,413,1),	XS_MASK,     PPC64,	PPCNONE,	{RA, RS, SH6}},
+{"sradi",	XS(31,413,0),	XS_MASK,  PPC64|PPCVLE,	PPCNONE,	{RA, RS, SH6}},
+{"sradi.",	XS(31,413,1),	XS_MASK,  PPC64|PPCVLE,	PPCNONE,	{RA, RS, SH6}},
 
 {"divo",	XO(31,331,1,0),	XO_MASK,     M601,	PPCNONE,	{RT, RA, RB}},
 {"divo.",	XO(31,331,1,1),	XO_MASK,     M601,	PPCNONE,	{RT, RA, RB}},
@@ -4747,7 +5578,7 @@ const struct powerpc_opcode powerpc_opco
 {"lbzcix",	X(31,853),	X_MASK,      POWER6,	PPCNONE,	{RT, RA0, RB}},
 
 {"eieio",	X(31,854),	0xffffffff,  PPC,   BOOKE|PPCA2|PPC476,	{0}},
-{"mbar",	X(31,854),	X_MASK, BOOKE|PPCA2|PPC476, PPCNONE,	{MO}},
+{"mbar",	X(31,854),	X_MASK, BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE,	{MO}},
 {"eieio",	XMBAR(31,854,1),0xffffffff,  E500,   PPCNONE,	{0}},
 {"eieio",	X(31,854),	0xffffffff, PPCA2|PPC476, PPCNONE,	{0}},
 
@@ -4774,13 +5605,13 @@ const struct powerpc_opcode powerpc_opco
 {"stxvw4x",	X(31,908),	XX1_MASK,    PPCVSX,	PPCNONE,	{XS6, RA, RB}},
 
 {"tlbsx",	XRC(31,914,0),	X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA, RB}},
-{"tlbsx.",	XRC(31,914,1),	X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RTO, RA, RB}},
+{"tlbsx.",	XRC(31,914,1),	X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RTO, RA, RB}},
 
 {"slbmfee",	X(31,915),	XRA_MASK,    PPC64,	PPCNONE,	{RT, RB}},
 
 {"stwcix",	X(31,917),	X_MASK,      POWER6,	PPCNONE,	{RS, RA0, RB}},
 
-{"sthbrx",	X(31,918),	X_MASK,      COM,	PPCNONE,	{RS, RA0, RB}},
+{"sthbrx",	X(31,918),	X_MASK,   COM|PPCVLE,	PPCNONE,	{RS, RA0, RB}},
 
 {"stfdpx",	X(31,919),	X_MASK,      POWER6,	POWER7,		{FRSp, RA, RB}},
 {"stfqx",	X(31,919),	X_MASK,      POWER2,	PPCNONE,	{FRS, RA, RB}},
@@ -4791,9 +5622,9 @@ const struct powerpc_opcode powerpc_opco
 {"srea",	XRC(31,921,0),	X_MASK,      M601,	PPCNONE,	{RA, RS, RB}},
 {"srea.",	XRC(31,921,1),	X_MASK,      M601,	PPCNONE,	{RA, RS, RB}},
 
-{"extsh",	XRC(31,922,0),	XRB_MASK,    PPCCOM,	PPCNONE,	{RA, RS}},
+{"extsh",	XRC(31,922,0),	XRB_MASK,  PPCCOM|PPCVLE,	PPCNONE,	{RA, RS}},
 {"exts",	XRC(31,922,0),	XRB_MASK,    PWRCOM,	PPCNONE,	{RA, RS}},
-{"extsh.",	XRC(31,922,1),	XRB_MASK,    PPCCOM,	PPCNONE,	{RA, RS}},
+{"extsh.",	XRC(31,922,1),	XRB_MASK,  PPCCOM|PPCVLE,	PPCNONE,	{RA, RS}},
 {"exts.",	XRC(31,922,1),	XRB_MASK,    PWRCOM,	PPCNONE,	{RA, RS}},
 
 {"stfddx",	X(31,931),	X_MASK,      E500MC,	PPCNONE,	{FRS, RA, RB}},
@@ -4811,7 +5642,7 @@ const struct powerpc_opcode powerpc_opco
 
 {"tlbrehi",	XTLB(31,946,0),	XTLB_MASK,   PPC403,	PPCA2,		{RT, RA}},
 {"tlbrelo",	XTLB(31,946,1),	XTLB_MASK,   PPC403,	PPCA2,		{RT, RA}},
-{"tlbre",	X(31,946),	X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}},
+{"tlbre",	X(31,946),	X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RSO, RAOPT, SHO}},
 
 {"sthcix",	X(31,949),	X_MASK,      POWER6,	PPCNONE,	{RS, RA0, RB}},
 
@@ -4823,55 +5654,55 @@ const struct powerpc_opcode powerpc_opco
 {"sraiq",	XRC(31,952,0),	X_MASK,      M601,	PPCNONE,	{RA, RS, SH}},
 {"sraiq.",	XRC(31,952,1),	X_MASK,      M601,	PPCNONE,	{RA, RS, SH}},
 
-{"extsb",	XRC(31,954,0),	XRB_MASK,    PPC,	PPCNONE,	{RA, RS}},
-{"extsb.",	XRC(31,954,1),	XRB_MASK,    PPC,	PPCNONE,	{RA, RS}},
+{"extsb",	XRC(31,954,0),	XRB_MASK, PPC|PPCVLE,	PPCNONE,	{RA, RS}},
+{"extsb.",	XRC(31,954,1),	XRB_MASK, PPC|PPCVLE,	PPCNONE,	{RA, RS}},
 
 {"iccci",	X(31,966), XRT_MASK, PPC403|PPC440|TITAN|PPCA2, PPCNONE, {RAOPT, RBOPT}},
-{"ici",		X(31,966),	XRARB_MASK,  PPCA2|PPC476, PPCNONE,	{CT}},
+{"ici",		X(31,966),	XRARB_MASK,  PPCA2|PPC476|PPCVLE, PPCNONE,	{CT}},
 
-{"divduo",	XO(31,457,1,0),	XO_MASK,     PPC64,	PPCNONE,	{RT, RA, RB}},
-{"divduo.",	XO(31,457,1,1),	XO_MASK,     PPC64,	PPCNONE,	{RT, RA, RB}},
+{"divduo",	XO(31,457,1,0),	XO_MASK,  PPC64|PPCVLE,	PPCNONE,	{RT, RA, RB}},
+{"divduo.",	XO(31,457,1,1),	XO_MASK,  PPC64|PPCVLE,	PPCNONE,	{RT, RA, RB}},
 
-{"divwuo",	XO(31,459,1,0),	XO_MASK,     PPC,	PPCNONE,	{RT, RA, RB}},
-{"divwuo.",	XO(31,459,1,1),	XO_MASK,     PPC,	PPCNONE,	{RT, RA, RB}},
+{"divwuo",	XO(31,459,1,0),	XO_MASK,  PPC|PPCVLE,	PPCNONE,	{RT, RA, RB}},
+{"divwuo.",	XO(31,459,1,1),	XO_MASK,  PPC|PPCVLE,	PPCNONE,	{RT, RA, RB}},
 
 {"stxvd2x",	X(31,972),	XX1_MASK,    PPCVSX,	PPCNONE,	{XS6, RA, RB}},
 
 {"tlbld",	X(31,978),	XRTRA_MASK,  PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}},
 {"tlbwehi",	XTLB(31,978,0),	XTLB_MASK,   PPC403,	PPCNONE,	{RT, RA}},
 {"tlbwelo",	XTLB(31,978,1),	XTLB_MASK,   PPC403,	PPCNONE,	{RT, RA}},
-{"tlbwe",	X(31,978),	X_MASK, PPC403|BOOKE|PPCA2|PPC476, PPCNONE, {RSO, RAOPT, SHO}},
+{"tlbwe",	X(31,978),	X_MASK, PPC403|BOOKE|PPCA2|PPC476|PPCVLE, PPCNONE, {RSO, RAOPT, SHO}},
 
 {"stbcix",	X(31,981),	X_MASK,      POWER6,	PPCNONE,	{RS, RA0, RB}},
 
-{"icbi",	X(31,982),	XRT_MASK,    PPC,	PPCNONE,	{RA, RB}},
+{"icbi",	X(31,982),	XRT_MASK, PPC|PPCVLE,	PPCNONE,	{RA, RB}},
 
 {"stfiwx",	X(31,983),	X_MASK,      PPC,	PPCEFS,		{FRS, RA0, RB}},
 
-{"extsw",	XRC(31,986,0),  XRB_MASK,    PPC64,	PPCNONE,	{RA, RS}},
-{"extsw.",	XRC(31,986,1),	XRB_MASK,    PPC64,	PPCNONE,	{RA, RS}},
+{"extsw",	XRC(31,986,0),  XRB_MASK, PPC64|PPCVLE,	PPCNONE,	{RA, RS}},
+{"extsw.",	XRC(31,986,1),	XRB_MASK, PPC64|PPCVLE,	PPCNONE,	{RA, RS}},
 
-{"icbiep",	XRT(31,991,0),	XRT_MASK, E500MC|PPCA2,	PPCNONE,	{RA, RB}},
+{"icbiep",	XRT(31,991,0),	XRT_MASK, E500MC|PPCA2|PPCVLE,	PPCNONE,	{RA, RB}},
 
-{"icread",	X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, PPCNONE, {RA, RB}},
+{"icread",	X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN|PPCVLE, PPCNONE, {RA, RB}},
 
 {"nabso",	XO(31,488,1,0),	XORB_MASK,   M601,	PPCNONE,	{RT, RA}},
 {"nabso.",	XO(31,488,1,1),	XORB_MASK,   M601,	PPCNONE,	{RT, RA}},
 
-{"divdo",	XO(31,489,1,0),	XO_MASK,     PPC64,	PPCNONE,	{RT, RA, RB}},
-{"divdo.",	XO(31,489,1,1),	XO_MASK,     PPC64,	PPCNONE,	{RT, RA, RB}},
+{"divdo",	XO(31,489,1,0),	XO_MASK,   PPC64|PPCVLE, PPCNONE,	{RT, RA, RB}},
+{"divdo.",	XO(31,489,1,1),	XO_MASK,   PPC64|PPCVLE, PPCNONE,	{RT, RA, RB}},
 
-{"divwo",	XO(31,491,1,0),	XO_MASK,     PPC,	PPCNONE,	{RT, RA, RB}},
-{"divwo.",	XO(31,491,1,1),	XO_MASK,     PPC,	PPCNONE,	{RT, RA, RB}},
+{"divwo",	XO(31,491,1,0),	XO_MASK,    PPC|PPCVLE,	PPCNONE,	{RT, RA, RB}},
+{"divwo.",	XO(31,491,1,1),	XO_MASK,    PPC|PPCVLE,	PPCNONE,	{RT, RA, RB}},
 
 {"tlbli",	X(31,1010),	XRTRA_MASK,  PPC,	TITAN,  	{RB}},
 
 {"stdcix",	X(31,1013),	X_MASK,      POWER6,	PPCNONE,	{RS, RA0, RB}},
 
-{"dcbz",	X(31,1014),	XRT_MASK,    PPC,	PPCNONE,	{RA, RB}},
+{"dcbz",	X(31,1014),	XRT_MASK,  PPC|PPCVLE,	PPCNONE,	{RA, RB}},
 {"dclz",	X(31,1014),	XRT_MASK,    PPC,	PPCNONE,	{RA, RB}},
 
-{"dcbzep",	XRT(31,1023,0),	XRT_MASK, E500MC|PPCA2,	PPCNONE,	{RA, RB}},
+{"dcbzep",	XRT(31,1023,0),	XRT_MASK, E500MC|PPCA2|PPCVLE,	PPCNONE,	{RA, RB}},
 
 {"dcbzl",	XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476,	{RA, RB}},
 
@@ -4888,6 +5719,7 @@ const struct powerpc_opcode powerpc_opco
 {"db12cyc",	0x7fdef378,	0xffffffff,  CELL,	PPCNONE,	{0}},
 {"db16cyc",	0x7ffffb78,	0xffffffff,  CELL,	PPCNONE,	{0}},
 
+{"se_lbz",	SD4(8),		SD4_MASK,    PPCVLE,	PPCNONE,	{RZ, SE_SD, RX}},
 {"lwz",		OP(32),		OP_MASK,     PPCCOM,	PPCNONE,	{RT, D, RA0}},
 {"l",		OP(32),		OP_MASK,     PWRCOM,	PPCNONE,	{RT, D, RA0}},
 
@@ -4897,6 +5729,7 @@ const struct powerpc_opcode powerpc_opco
 {"lbz",		OP(34),		OP_MASK,     COM,	PPCNONE,	{RT, D, RA0}},
 
 {"lbzu",	OP(35),		OP_MASK,     COM,	PPCNONE,	{RT, D, RAL}},
+{"se_stb",	SD4(9),		SD4_MASK,    PPCVLE,	PPCNONE,	{RZ, SE_SD, RX}},
 
 {"stw",		OP(36),		OP_MASK,     PPCCOM,	PPCNONE,	{RS, D, RA0}},
 {"st",		OP(36),		OP_MASK,     PWRCOM,	PPCNONE,	{RS, D, RA0}},
@@ -4907,6 +5740,7 @@ const struct powerpc_opcode powerpc_opco
 {"stb",		OP(38),		OP_MASK,     COM,	PPCNONE,	{RS, D, RA0}},
 
 {"stbu",	OP(39),		OP_MASK,     COM,	PPCNONE,	{RS, D, RAS}},
+{"se_lhz",	SD4(10),	SD4_MASK,    PPCVLE,	PPCNONE,	{RZ, SE_SDH, RX}},
 
 {"lhz",		OP(40),		OP_MASK,     COM,	PPCNONE,	{RT, D, RA0}},
 
@@ -4915,6 +5749,7 @@ const struct powerpc_opcode powerpc_opco
 {"lha",		OP(42),		OP_MASK,     COM,	PPCNONE,	{RT, D, RA0}},
 
 {"lhau",	OP(43),		OP_MASK,     COM,	PPCNONE,	{RT, D, RAL}},
+{"se_sth",	SD4(11),	SD4_MASK,    PPCVLE,	PPCNONE,	{RZ, SE_SDH, RX}},
 
 {"sth",		OP(44),		OP_MASK,     COM,	PPCNONE,	{RS, D, RA0}},
 
@@ -4926,6 +5761,7 @@ const struct powerpc_opcode powerpc_opco
 {"stmw",	OP(47),		OP_MASK,     PPCCOM,	PPCNONE,	{RS, D, RA0}},
 {"stm",		OP(47),		OP_MASK,     PWRCOM,	PPCNONE,	{RS, D, RA0}},
 
+{"se_lwz",	SD4(12),	SD4_MASK,    PPCVLE,	PPCNONE,	{RZ, SE_SDW, RX}},
 {"lfs",		OP(48),		OP_MASK,     COM,	PPCEFS,		{FRT, D, RA0}},
 
 {"lfsu",	OP(49),		OP_MASK,     COM,	PPCEFS,		{FRT, D, RAS}},
@@ -4934,6 +5770,7 @@ const struct powerpc_opcode powerpc_opco
 
 {"lfdu",	OP(51),		OP_MASK,     COM,	PPCEFS,		{FRT, D, RAS}},
 
+{"se_stw",	SD4(13),	SD4_MASK,    PPCVLE,	PPCNONE,	{RZ, SE_SDW, RX}},
 {"stfs",	OP(52),		OP_MASK,     COM,	PPCEFS,		{FRS, D, RA0}},
 
 {"stfsu",	OP(53),		OP_MASK,     COM,	PPCEFS,		{FRS, D, RAS}},
@@ -4942,14 +5779,34 @@ const struct powerpc_opcode powerpc_opco
 
 {"stfdu",	OP(55),		OP_MASK,     COM,	PPCEFS,		{FRS, D, RAS}},
 
+{"se_bge",	EBD8IO(28,0,0),	EBD8IO3_MASK,  PPCVLE,	PPCNONE,	{B8}},
+{"se_bnl",	EBD8IO(28,0,0),	EBD8IO3_MASK,  PPCVLE,	PPCNONE,	{B8}},
+{"se_ble",	EBD8IO(28,0,1),	EBD8IO3_MASK,  PPCVLE,	PPCNONE,	{B8}},
+{"se_bng",	EBD8IO(28,0,1),	EBD8IO3_MASK,  PPCVLE,	PPCNONE,	{B8}},
+{"se_bne",	EBD8IO(28,0,2),	EBD8IO3_MASK,  PPCVLE,	PPCNONE,	{B8}},
+{"se_bns",	EBD8IO(28,0,3),	EBD8IO3_MASK,  PPCVLE,	PPCNONE,	{B8}},
+{"se_bnu",	EBD8IO(28,0,3),	EBD8IO3_MASK,  PPCVLE,	PPCNONE,	{B8}},
+{"se_bf",	EBD8IO(28,0,0),	EBD8IO2_MASK,  PPCVLE,	PPCNONE,	{BI16, B8}},
+
 {"lq",		OP(56),		OP_MASK,     POWER4,	PPC476,		{RTQ, DQ, RAQ}},
 {"psq_l",	OP(56),		OP_MASK,     PPCPS,	PPCNONE,	{FRT,PSD,RA,PSW,PSQ}},
 {"lfq",		OP(56),		OP_MASK,     POWER2,	PPCNONE,	{FRT, D, RA0}},
 
+{"se_blt",	EBD8IO(28,1,0),	EBD8IO3_MASK,  PPCVLE,	PPCNONE,	{B8}},
+{"se_bgt",	EBD8IO(28,1,1),	EBD8IO3_MASK,  PPCVLE,	PPCNONE,	{B8}},
+{"se_beq",	EBD8IO(28,1,2),	EBD8IO3_MASK,  PPCVLE,	PPCNONE,	{B8}},
+{"se_bso",	EBD8IO(28,1,3),	EBD8IO3_MASK,  PPCVLE,	PPCNONE,	{B8}},
+{"se_bun",	EBD8IO(28,1,3),	EBD8IO3_MASK,  PPCVLE,	PPCNONE,	{B8}},
+{"se_bt",	EBD8IO(28,1,0),	EBD8IO2_MASK,  PPCVLE,	PPCNONE,	{BI16, B8}},
+
+{"se_bc",	BD8IO(28),	BD8IO_MASK,    PPCVLE,	PPCNONE,	{BO16, BI16, B8}},
+
 {"lfdp",	OP(57),		OP_MASK,     POWER6,	POWER7,		{FRTp, D, RA0}},
 {"psq_lu",	OP(57),		OP_MASK,     PPCPS,	PPCNONE,	{FRT,PSD,RA,PSW,PSQ}},
 {"lfqu",	OP(57),		OP_MASK,     POWER2,	PPCNONE,	{FRT, D, RA0}},
 
+{"se_b",	BD8(58,0,0),	BD8_MASK,    PPCVLE,	PPCNONE,	{B8}},
+{"se_bl",	BD8(58,0,1),	BD8_MASK,    PPCVLE,	PPCNONE,	{B8}},
 {"ld",		DSO(58,0),	DS_MASK,     PPC64,	PPCNONE,	{RT, DS, RA0}},
 {"ldu",		DSO(58,1),	DS_MASK,     PPC64,	PPCNONE,	{RT, DS, RAL}},
 {"lwa",		DSO(58,2),	DS_MASK,     PPC64,	PPCNONE,	{RT, DS, RA0}},
@@ -5491,6 +6348,18 @@ const struct powerpc_macro powerpc_macro
 {"clrrwi.",  3,	PPCCOM,	"rlwinm. %0,%1,0,0,31-(%2)"},
 {"clrlslwi", 4,	PPCCOM,	"rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
 {"clrlslwi.",4, PPCCOM,	"rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)"},
+
+{"e_extlwi",   4,	PPCVLE,	"e_rlwinm %0,%1,%3,0,(%2)-1"},
+{"e_extrwi",   4,	PPCVLE,	"e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
+{"e_inslwi",   4,	PPCVLE,	"e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
+{"e_insrwi",   4,	PPCVLE,	"e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
+{"e_rotlwi",   3,	PPCVLE,	"e_rlwinm %0,%1,%2,0,31"},
+{"e_rotrwi",   3,	PPCVLE,	"e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
+{"e_slwi",     3,	PPCVLE,	"e_rlwinm %0,%1,%2,0,31-(%2)"},
+{"e_srwi",     3,	PPCVLE,	"e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
+{"e_clrlwi",   3,	PPCVLE,	"e_rlwinm %0,%1,0,%2,31"},
+{"e_clrrwi",   3,	PPCVLE,	"e_rlwinm %0,%1,0,0,31-(%2)"},
+{"e_clrlslwi", 4,	PPCVLE,	"e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
 };
 
 const int powerpc_num_macros =

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