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Re: PATCH: Implement Intel Transactional Synchronization Extensions
On Wed, Feb 22, 2012 at 9:10 AM, H.J. Lu <email@example.com> wrote:
>>>> Further, while the patch deals with CMPXCHG8B, for some reason
>>>> it leaves out CMPXCHG16B (perhaps because the instruction, oddly
>>>> enough, is considered an SSE3 one).
>>>> Finally, albeit consistent with what is documented, I'm surprised that
>>>> MOV opcodes 0xA2 and 0xA3 aren't allowed with XRELEASE - is that
>>>> really the case?
>>>Yes, they are implemented according to TSX spec.
>> Assuming you meant "are not", did you check that this isn't just an omission
>> in the spec?
> I will let you know what I found out.
I was told that the TSX spec is correct. HLE doesn't support
CMPXCHG16B nor MOV opcodes 0xA2 and 0xA3.