diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index c95f713..c537d27 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -351,6 +351,9 @@ enum it_instruction_type IT_INSN /* The IT insn has been parsed. */ }; +/* The maximum number of operands we need. */ +#define ARM_IT_MAX_OPERANDS 6 + struct arm_it { const char * error; @@ -402,7 +405,7 @@ struct arm_it unsigned negative : 1; /* Index register was negated. */ unsigned shifted : 1; /* Shift applied to operation. */ unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */ - } operands[6]; + } operands[ARM_IT_MAX_OPERANDS]; }; static struct arm_it inst; @@ -12415,7 +12418,9 @@ neon_select_shape (enum neon_shape shape, ...) if (!matches) break; } - if (matches) + if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present)) + /* We've matched all the entries in the shape table, and we don't + have any left over operands which have not been matched. */ break; } diff --git a/gas/testsuite/gas/arm/neon-suffix-bad.l b/gas/testsuite/gas/arm/neon-suffix-bad.l index 4c44f6b..091429d 100644 --- a/gas/testsuite/gas/arm/neon-suffix-bad.l +++ b/gas/testsuite/gas/arm/neon-suffix-bad.l @@ -2,6 +2,8 @@ [^:]*:3: Error: invalid neon suffix for non neon instruction [^:]*:4: Error: invalid neon suffix for non neon instruction [^:]*:5: Error: invalid neon suffix for non neon instruction -[^:]*:8: Error: invalid neon suffix for non neon instruction +[^:]*:6: Error: invalid instruction shape -- `vcvt.f64.s32 d0,s0,#11' [^:]*:9: Error: invalid neon suffix for non neon instruction [^:]*:10: Error: invalid neon suffix for non neon instruction +[^:]*:11: Error: invalid neon suffix for non neon instruction +[^:]*:12: Error: invalid instruction shape -- `vcvt.f64.s32 d0,s0,#11' diff --git a/gas/testsuite/gas/arm/neon-suffix-bad.s b/gas/testsuite/gas/arm/neon-suffix-bad.s index 288dba7..20c60fe 100644 --- a/gas/testsuite/gas/arm/neon-suffix-bad.s +++ b/gas/testsuite/gas/arm/neon-suffix-bad.s @@ -3,10 +3,11 @@ add.f32 r0, r0, r0 faddd.f32 d0, d0, d0 faddd.f64 d0, d0, d0 +vcvt.f64.s32 d0, s0, #11 .thumb add.f32 r0, r0, r0 faddd.f32 d0, d0, d0 faddd.f64 d0, d0, d0 - +vcvt.f64.s32 d0, s0, #11