Re: ARM as ... possible bug

[Dave Pawson <dave dot pawson at gmail dot com>]

On 12 December 2011 10:36, Matthew Gretton-Dann
<matthew.gretton-dann@arm.com> wrote:
> On 12/12/11 10:15, Dave Pawson wrote:
>>
>> Thanks for the explanation Matt.
>>
>> On 12 December 2011 09:27, Matthew Gretton-Dann

>> if ConditionPassed() then
>> EncodingSpecificOperations(); NullCheckIfThumbEE(n);
>
>
> EncodingSpecificOperations() means 'execute the pseudo-code that appears
> underneath the encoding bit pattern'.
>
> So for ARM state strexd encoding this says that if the bottom bit of the
> first transfer register (Rt) is 1 then the instructions is 'UNPREDICTABLE'.

n = UInt(Rn);
if ... || n == 15 then UNPREDICTABLE;

OK. I can see it now you've explained it....


>
> Take a look at the description for ldrexd where this is documented in a
> slightly clearer manner.

Ah. Now that is explicit

"The first destination register. For an ARM instruction, <Rt> must be
even-numbered and not
R14."

I'll put a comment through to the errata email suggesting that be
added to strexd


Thanks for taking time to explain it Matt.


regards

-- 
Dave Pawson
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