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Re: [PATCH] Add Octeon2 cpu support to binutils


Andrew Pinski <andrew.pinski@caviumnetworks.com> writes:
> Index: bfd/archures.c
> ===================================================================
> RCS file: /cvs/src/src/bfd/archures.c,v
> retrieving revision 1.161
> diff -u -p -r1.161 archures.c
> --- bfd/archures.c	29 Nov 2011 20:28:53 -0000	1.161
> +++ bfd/archures.c	8 Dec 2011 01:51:54 -0000
> @@ -177,6 +177,7 @@ DESCRIPTION
>  .#define bfd_mach_mips_sb1              12310201 {* octal 'SB', 01 *}
>  .#define bfd_mach_mips_octeon		6501
>  .#define bfd_mach_mips_octeonp		6601
> +.#define bfd_mach_mips_octeon2		6502

For the record, I found this a little confusing: octeon <= octeon2 <=
octeonp, but it doesn't really matter.

> Index: opcodes/mips-dis.c
> ===================================================================
> RCS file: /cvs/src/src/opcodes/mips-dis.c,v
> retrieving revision 1.88
> diff -u -p -r1.88 mips-dis.c
> --- opcodes/mips-dis.c	29 Nov 2011 20:28:55 -0000	1.88
> +++ opcodes/mips-dis.c	8 Dec 2011 01:51:56 -0000
> @@ -609,6 +609,10 @@ const struct mips_arch_choice mips_arch_
>      ISA_MIPS64R2 | INSN_OCTEON | INSN_OCTEONP, mips_cp0_names_numeric,
>      NULL, 0, mips_hwr_names_numeric },
>  
> +  { "octeon2",   1, bfd_mach_mips_octeon2, CPU_OCTEON2,
> +    ISA_MIPS64R2 | INSN_OCTEON | INSN_OCTEON2, mips_cp0_names_numeric,
> +    NULL, 0, mips_hwr_names_numeric },

Oops, seems I wasn't paying much attention before.  I think the
previous entry should just be "ISA_MIPS64R2 | INSN_OCTEONP" and
this one should just be "ISA_MIPS64R2 | INSN_OCTEON2".  At least,
it's confusing to leave INSN_OCTEONP out of this one while still
including INSN_OCTEON.

> +{"lwux",    "d,t(b)",	0x7c00040a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,	0,		D32|IOCT2},

This one should just be "IOCT2".

> +/* lbux, ldx, lhx and lwx are the int basic instruction section.  */

/* lbux, ldx, lhx and lwx are in the basic instruction section.  */

OK with those changes, thanks.

Richard


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