Index: gas/config/tc-mips.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-mips.c,v
retrieving revision 1.493
diff -u -p -r1.493 tc-mips.c
--- gas/config/tc-mips.c	24 Oct 2011 14:25:01 -0000	1.493
+++ gas/config/tc-mips.c	11 Nov 2011 04:59:36 -0000
@@ -9118,6 +9118,53 @@ macro (struct mips_cl_insn *ip)
 	}
       break;
 
+    case M_SAA_AB:
+      s = "saa";
+      goto saa_saad;
+    case M_SAAD_AB:
+      s = "saad";
+
+      saa_saad:
+      /* The saa/saad instructions do not specify offset.  When invoked with
+	 address or symbol then load the address or value of symbol in a
+	 register using the la macro into AT, and pass the register for
+	 emitting saa/saad instruction.  This will get expanded to
+
+	    la AT, constant/label
+	    saa/saad $treg,(AT)  */
+      {
+	/* Accept zero-displacement.  */
+	if (breg
+	    && offset_expr.X_op == O_constant
+	    && offset_expr.X_add_number == 0)
+	  {
+	    macro_build (NULL, s, "t,(s)", treg, breg);
+	    break;
+	  }
+
+	used_at = 1;
+	tempreg = AT;
+	/* If the offset_expr is a constant and in the range,
+	   then just emit the {,d}addi. */
+	if (breg
+	    && offset_expr.X_op == O_constant
+	    && offset_expr.X_add_number >= -0x8000
+	    && offset_expr.X_add_number < 0x8000)
+	   macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
+			tempreg, breg, BFD_RELOC_LO16);
+	else
+	  {
+	    load_address (tempreg, &offset_expr, &used_at);
+	    if (breg)
+	      macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
+			   tempreg, tempreg, breg);
+          }
+
+	/* The address part is forwarded through the global offset_expr. */
+	macro_build (NULL, s, "t,(s)", treg, AT);
+	break;
+      }
+
    /* New code added to support COPZ instructions.
       This code builds table entries out of the macros in mip_opcodes.
       R4000 uses interlocks to handle coproc delays.
@@ -11015,7 +11062,7 @@ mips_ip (char *str, struct mips_cl_insn 
 		 we must have a left paren.  */
 	      /* This is dependent on the next operand specifier
 		 is a base register specification.  */
-	      gas_assert (args[1] == 'b'
+	      gas_assert (args[1] == 'b' || args[1] == 's'
 			  || (mips_opts.micromips
 			      && args[1] == 'm'
 			      && (args[2] == 'l' || args[2] == 'n'
Index: gas/testsuite/gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.192
diff -u -p -r1.192 mips.exp
--- gas/testsuite/gas/mips/mips.exp	5 Sep 2011 19:19:00 -0000	1.192
+++ gas/testsuite/gas/mips/mips.exp	11 Nov 2011 04:59:37 -0000
@@ -980,6 +980,7 @@ if { [istarget mips*-*-vxworks*] } {
     run_dump_test "loongson-3a-3"
 
     run_dump_test_arches "octeon"	[mips_arch_list_matching octeon]
+    run_dump_test_arches "octeon-saa-saad" [mips_arch_list_matching octeon]
     run_list_test_arches "octeon-ill" "" \
 					[mips_arch_list_matching octeon]
     run_dump_test_arches "octeon-pref"	[mips_arch_list_matching octeon]
Index: gas/testsuite/gas/mips/octeon-saa-saad.d
===================================================================
RCS file: gas/testsuite/gas/mips/octeon-saa-saad.d
diff -N gas/testsuite/gas/mips/octeon-saa-saad.d
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/octeon-saa-saad.d	11 Nov 2011 04:59:37 -0000
@@ -0,0 +1,47 @@
+#objdump: -d --show-raw-insn
+#name: MIPS-OCTEON octeon_saa_saad
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <foo>:
+.*:	70450018 	saa	a1,\(v0\)
+.*:	70860019 	saad	a2,\(a0\)
+.*:	00000000 	nop
+.*:	70450018 	saa	a1,\(v0\)
+.*:	70860019 	saad	a2,\(a0\)
+.*:	00000000 	nop
+.*:	3c010000 	lui	at,0x0
+.*:	24210000 	addiu	at,at,0
+.*:	70250018 	saa	a1,\(at\)
+.*:	3c010000 	lui	at,0x0
+.*:	24210000 	addiu	at,at,0
+.*:	70220019 	saad	v0,\(at\)
+.*:	00000000 	nop
+.*:	3c011234 	lui	at,0x1234
+.*:	34215678 	ori	at,at,0x5678
+.*:	70240018 	saa	a0,\(at\)
+.*:	3c011234 	lui	at,0x1234
+.*:	34215678 	ori	at,at,0x5678
+.*:	70240019 	saad	a0,\(at\)
+.*:	00000000 	nop
+.*:	24811234 	addiu	at,a0,4660
+.*:	70250018 	saa	a1,\(at\)
+.*:	2401003c 	li	at,60
+.*:	70260019 	saad	a2,\(at\)
+.*:	00000000 	nop
+.*:	3c010012 	lui	at,0x12
+.*:	34213456 	ori	at,at,0x3456
+.*:	00240821 	addu	at,at,a0
+.*:	70250018 	saa	a1,\(at\)
+.*:	24c11234 	addiu	at,a2,4660
+.*:	70260018 	saa	a2,\(at\)
+.*:	00000000 	nop
+.*:	24a15678 	addiu	at,a1,22136
+.*:	70240019 	saad	a0,\(at\)
+.*:	3c010056 	lui	at,0x56
+.*:	34217891 	ori	at,at,0x7891
+.*:	00250821 	addu	at,at,a1
+.*:	70250019 	saad	a1,\(at\)
+#pass
Index: gas/testsuite/gas/mips/octeon-saa-saad.s
===================================================================
RCS file: gas/testsuite/gas/mips/octeon-saa-saad.s
diff -N gas/testsuite/gas/mips/octeon-saa-saad.s
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/octeon-saa-saad.s	11 Nov 2011 04:59:37 -0000
@@ -0,0 +1,29 @@
+	.text
+foo:
+	saa $5,($2)
+	saad $6,($4)
+	nop
+
+	saa $5,0($2)
+	saad $6,0($4)
+	nop
+
+	saa $5, foo
+	saad $2, foo
+	nop
+
+	saa $4, 0x12345678
+	saad $4, 0x12345678
+	nop
+
+	saa $5, 0x1234($4)
+	saad $6, 60($0)
+	nop
+
+	saa $5, 0x123456($4)
+	saa $6, 0x1234($6)
+	nop
+
+	saad $4, 0x5678($5)
+	saad $5, 0x567891($5)
+	nop	
Index: include/opcode/mips.h
===================================================================
RCS file: /cvs/src/src/include/opcode/mips.h,v
retrieving revision 1.80
diff -u -p -r1.80 mips.h
--- include/opcode/mips.h	24 Oct 2011 14:21:41 -0000	1.80
+++ include/opcode/mips.h	11 Nov 2011 04:59:37 -0000
@@ -1065,6 +1065,8 @@ enum
   M_S_DOB,
   M_S_DAB,
   M_S_S,
+  M_SAA_AB,
+  M_SAAD_AB,
   M_SC_AB,
   M_SC_OB,
   M_SCD_AB,
Index: opcodes/mips-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-opc.c,v
retrieving revision 1.88
diff -u -p -r1.88 mips-opc.c
--- opcodes/mips-opc.c	9 Aug 2011 15:20:03 -0000	1.88
+++ opcodes/mips-opc.c	11 Nov 2011 04:59:37 -0000
@@ -1247,6 +1247,10 @@ const struct mips_opcode mips_builtin_op
 {"rzu.ob",  "X,Q",	0x78000020, 0xfc20f83f,	WR_D|RD_T|FP_D,		RD_MACC,	MX|SB1	},
 {"rzu.ob",  "D,k",	0x4bc00020, 0xffe0f83f,	WR_D|RD_S|RD_T,		0,		N54	},
 {"rzu.qh",  "X,Q",	0x78200020, 0xfc20f83f,	WR_D|RD_T|FP_D,		RD_MACC,	MX	},
+{"saa",	    "t,(s)",	0x70000018, 0xfc00ffff, SM|RD_t|RD_b,		0,		IOCT	},
+{"saa",	    "t,A(b)",	0,    (int) M_SAA_AB,	INSN_MACRO,		0,		IOCT	},
+{"saad",    "t,(s)",	0x70000019, 0xfc00ffff,	SM|RD_t|RD_b,		0,		IOCT	},
+{"saad",    "t,A(b)",	0,    (int) M_SAAD_AB,	INSN_MACRO,		0,		IOCT	},
 {"sb",      "t,o(b)",	0xa0000000, 0xfc000000,	SM|RD_t|RD_b,		0,		I1	},
 {"sb",      "t,A(b)",	0,    (int) M_SB_AB,	INSN_MACRO,		0,		I1	},
 {"sc",	    "t,o(b)",	0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,	0,		I2	},