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New port: Renesas RL78
- From: DJ Delorie <dj at redhat dot com>
- To: binutils at sourceware dot org
- Date: Mon, 24 Oct 2011 18:40:06 -0400
- Subject: New port: Renesas RL78
The Renesas RL78 is a new low-power 8/16 bit microcontroller, with an
architecture much like the original Z80. However, it has four
register banks and a 1 Mb address space with default 16 bit pointers
and segment registers to access outside the default segments (code:
first 64k, data: last 64k). The RL78 family is a direct descendant of
the 78K0R and R8C families (78K0R cpu core, R8C peripherals).
http://www.renesas.com/pr/mcu/rl78/
Target: rl78-elf
The config.guess patch was sent upstream last week, but I haven't
heard back yet. Generated files not included below.
[.]
* configure.ac (rl78-*-*) New case.
* configure: Regenerate.
* config.sub (rl78): New case.
[bfd]
* Makefile.am (ALL_MACHINES): Add cpu-rl78.lo.
(ALL_MACHINES_CFILES): Add cpu-rl78.c.
(BFD32_BACKENDS): Add elf32-rl78.lo.
(BFD32_BACKENDS_CFILES): Add elf32-rl78.c.
(Makefile.in): Regenerate.
* archures.c (bfd_architecture): Define bfd_arch_rl78.
(bfd_archures_list): Add bfd_rl78_arch.
* config.bfd: Add rl78-*-elf.
* configure.in: Add bfd_elf32_rl78_vec.
* reloc.c (bfd_reloc_code_type): Add BFD_RELOC_RL78_* relocations.
* targets.c (bfd_target_vector): Add bfd_elf32_rl78_vec.
* Makefile.in: Regenerate.
* bfd-in2.h: Regenerate.
* configure: Regenerate.
* libbfd.h: Regenerate.
* cpu-rl78.c: New file.
* elf32-rl78.c: New file.
[binutils]
* readelf.c: Include elf/rl78.h
(guess_is_rela): Handle EM_RL78.
(dump_relocations): Likewise.
(get_machine_name): Likewise.
(is_32bit_abs_reloc): Likewise.
[gas]
* Makefile.am (TARGET_CPU_CFILES): Add tc-rl78.c.
(TARGET_CPU_HFILES): Add rc-rl78.h.
(EXTRA_DIST): Add rl78-parse.c and rl78-parse.y.
(rl78-parse.c, rl78-parse.h, rl78-parse.o, rl78-defs.h): New rules.
* Makefile.in: Regenerate.
* configure.in: Add rl78 case.
* configure: Regenerate.
* configure.tgt: Add rl78 case.
* config/rl78-defs.h: New file.
* config/rl78-parse.y: New file.
* config/tc-rl78.c: New file.
* config/tc-rl78.h: New file.
[include]
* dis-asm.h (print_insn_rl78): Declare.
[include/elf]
* common.h (EM_RL78, EM_78K0R): New.
* rl78.h: New.
[include/opcode]
* rl78.h: New file.
[ld]
* Makefile.am (ALL_EMULATION_SOURCES): Add eelf32rl78.c.
(+eelf32rl78.c): New rule.
* Makefile.in: Regenerate.
* configure.tgt: Add rl78-*-* case.
* emulparams/elf32rl78.sh: New file.
[opcodes]
* Makefile.am (TARGET_LIBOPCODES_CFILES): Add rl78-decode.c and
rl78-dis.c.
(MAINTAINERCLEANFILES): Add rl78-decode.c.
(rl78-decode.c): New rule, built from rl78-decode.opc and opc2c.
* Makefile.in: Regenerate.
* configure.in: Add bfd_rl78_arch case.
* configure: Regenerate.
* disassemble.c: Define ARCH_rl78.
(disassembler): Add ARCH_rl78 case.
* rl78-decode.c: New file.
* rl78-decode.opc: New file.
* rl78-dis.c: New file.
Index: config.sub
===================================================================
RCS file: /cvs/src/src/config.sub,v
retrieving revision 1.84
diff -p -U5 -r1.84 config.sub
--- config.sub 6 Jun 2011 10:36:06 -0000 1.84
+++ config.sub 24 Oct 2011 22:25:10 -0000
@@ -289,11 +289,11 @@ case $basic_machine in
| open8 \
| or32 \
| pdp10 | pdp11 | pj | pjl \
| powerpc | powerpc64 | powerpc64le | powerpcle \
| pyramid \
- | rx \
+ | rl78 | rx \
| score \
| sh | sh[1234] | sh[24]a | sh[24]aeb | sh[23]e | sh[34]eb | sheb | shbe | shle | sh[1234]le | sh3ele \
| sh64 | sh64le \
| sparc | sparc64 | sparc64b | sparc64v | sparc86x | sparclet | sparclite \
| sparcv8 | sparcv9 | sparcv9b | sparcv9v \
@@ -398,11 +398,11 @@ case $basic_machine in
| open8-* \
| orion-* \
| pdp10-* | pdp11-* | pj-* | pjl-* | pn-* | power-* \
| powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* \
| pyramid-* \
- | romp-* | rs6000-* | rx-* \
+ | romp-* | rs6000-* | rl78-* | rx-* \
| sh-* | sh[1234]-* | sh[24]a-* | sh[24]aeb-* | sh[23]e-* | sh[34]eb-* | sheb-* | shbe-* \
| shle-* | sh[1234]le-* | sh3ele-* | sh64-* | sh64le-* \
| sparc-* | sparc64-* | sparc64b-* | sparc64v-* | sparc86x-* | sparclet-* \
| sparclite-* \
| sparcv8-* | sparcv9-* | sparcv9b-* | sparcv9v-* | sv1-* | sx?-* \
Index: configure.ac
===================================================================
RCS file: /cvs/src/src/configure.ac,v
retrieving revision 1.158
diff -p -U5 -r1.158 configure.ac
--- configure.ac 14 Aug 2011 12:28:16 -0000 1.158
+++ configure.ac 24 Oct 2011 22:25:12 -0000
@@ -499,10 +499,14 @@ case "${target}" in
noconfigdirs="$noconfigdirs target-libssp"
;;
powerpc-*-aix* | rs6000-*-aix*)
noconfigdirs="$noconfigdirs target-libssp"
;;
+ rl78-*-*)
+ # Dereferencing -1 is a compile-time error
+ noconfigdirs="$noconfigdirs target-libssp"
+ ;;
esac
# Disable libstdc++-v3 for some systems.
case "${target}" in
*-*-vxworks*)
Index: bfd/Makefile.am
===================================================================
RCS file: /cvs/src/src/bfd/Makefile.am,v
retrieving revision 1.258
diff -p -U5 -r1.258 Makefile.am
--- bfd/Makefile.am 22 Jul 2011 20:22:29 -0000 1.258
+++ bfd/Makefile.am 24 Oct 2011 22:25:12 -0000
@@ -120,10 +120,11 @@ ALL_MACHINES = \
cpu-pdp11.lo \
cpu-pj.lo \
cpu-plugin.lo \
cpu-powerpc.lo \
cpu-rs6000.lo \
+ cpu-rl78.lo \
cpu-rx.lo \
cpu-s390.lo \
cpu-score.lo \
cpu-sh.lo \
cpu-sparc.lo \
@@ -195,10 +196,11 @@ ALL_MACHINES_CFILES = \
cpu-pdp11.c \
cpu-pj.c \
cpu-plugin.c \
cpu-powerpc.c \
cpu-rs6000.c \
+ cpu-rl78.c \
cpu-rx.c \
cpu-s390.c \
cpu-score.c \
cpu-sh.c \
cpu-sparc.c \
@@ -314,10 +316,11 @@ BFD32_BACKENDS = \
elf32-mt.lo \
elf32-openrisc.lo \
elf32-or32.lo \
elf32-pj.lo \
elf32-ppc.lo \
+ elf32-rl78.lo \
elf32-rx.lo \
elf32-s390.lo \
elf32-sh-symbian.lo \
elf32-sh.lo \
elf32-sh64-com.lo \
@@ -498,10 +501,11 @@ BFD32_BACKENDS_CFILES = \
elf32-mt.c \
elf32-openrisc.c \
elf32-or32.c \
elf32-pj.c \
elf32-ppc.c \
+ elf32-rl78.c \
elf32-rx.c \
elf32-s390.c \
elf32-sh-symbian.c \
elf32-sh.c \
elf32-sh64-com.c \
Index: bfd/archures.c
===================================================================
RCS file: /cvs/src/src/bfd/archures.c,v
retrieving revision 1.158
diff -p -U5 -r1.158 archures.c
--- bfd/archures.c 1 Aug 2011 23:04:19 -0000 1.158
+++ bfd/archures.c 24 Oct 2011 22:25:13 -0000
@@ -398,10 +398,12 @@ DESCRIPTION
.#define bfd_mach_crx 1
. bfd_arch_cris, {* Axis CRIS *}
.#define bfd_mach_cris_v0_v10 255
.#define bfd_mach_cris_v32 32
.#define bfd_mach_cris_v10_v32 1032
+. bfd_arch_rl78,
+.#define bfd_mach_rl78 0x75
. bfd_arch_rx, {* Renesas RX. *}
.#define bfd_mach_rx 0x75
. bfd_arch_s390, {* IBM s390 *}
.#define bfd_mach_s390_31 31
.#define bfd_mach_s390_64 64
@@ -534,10 +536,11 @@ extern const bfd_arch_info_type bfd_pdp1
extern const bfd_arch_info_type bfd_pj_arch;
extern const bfd_arch_info_type bfd_plugin_arch;
extern const bfd_arch_info_type bfd_powerpc_archs[];
#define bfd_powerpc_arch bfd_powerpc_archs[0]
extern const bfd_arch_info_type bfd_rs6000_arch;
+extern const bfd_arch_info_type bfd_rl78_arch;
extern const bfd_arch_info_type bfd_rx_arch;
extern const bfd_arch_info_type bfd_s390_arch;
extern const bfd_arch_info_type bfd_score_arch;
extern const bfd_arch_info_type bfd_sh_arch;
extern const bfd_arch_info_type bfd_sparc_arch;
@@ -611,10 +614,11 @@ static const bfd_arch_info_type * const
&bfd_openrisc_arch,
&bfd_or32_arch,
&bfd_pdp11_arch,
&bfd_powerpc_arch,
&bfd_rs6000_arch,
+ &bfd_rl78_arch,
&bfd_rx_arch,
&bfd_s390_arch,
&bfd_score_arch,
&bfd_sh_arch,
&bfd_sparc_arch,
Index: bfd/config.bfd
===================================================================
RCS file: /cvs/src/src/bfd/config.bfd,v
retrieving revision 1.284
diff -p -U5 -r1.284 config.bfd
--- bfd/config.bfd 28 Jul 2011 22:35:13 -0000 1.284
+++ bfd/config.bfd 24 Oct 2011 22:25:14 -0000
@@ -1191,10 +1191,14 @@ case "${targ}" in
powerpcle-*-pe | powerpcle-*-winnt* | powerpcle-*-cygwin*)
targ_defvec=bfd_powerpcle_pe_vec
targ_selvecs="bfd_powerpcle_pei_vec bfd_powerpc_pei_vec bfd_powerpcle_pe_vec bfd_powerpc_pe_vec"
;;
+ rl78-*-elf)
+ targ_defvec=bfd_elf32_rl78_vec
+ ;;
+
rx-*-elf)
targ_defvec=bfd_elf32_rx_le_vec
targ_selvecs="bfd_elf32_rx_be_vec bfd_elf32_rx_le_vec bfd_elf32_rx_be_ns_vec"
;;
Index: bfd/configure.in
===================================================================
RCS file: /cvs/src/src/bfd/configure.in,v
retrieving revision 1.302
diff -p -U5 -r1.302 configure.in
--- bfd/configure.in 22 Sep 2011 08:35:49 -0000 1.302
+++ bfd/configure.in 24 Oct 2011 22:25:16 -0000
@@ -760,10 +760,11 @@ do
bfd_elf32_pj_vec) tb="$tb elf32-pj.lo elf32.lo $elf";;
bfd_elf32_pjl_vec) tb="$tb elf32-pj.lo elf32.lo $elf";;
bfd_elf32_powerpc_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;;
bfd_elf32_powerpcle_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;;
bfd_elf32_powerpc_vxworks_vec) tb="$tb elf32-ppc.lo elf-vxworks.lo elf32.lo $elf" ;;
+ bfd_elf32_rl78_vec) tb="$tb elf32-rl78.lo $elf" ;;
bfd_elf32_rx_le_vec) tb="$tb elf32-rx.lo elf32.lo $elf" ;;
bfd_elf32_rx_be_vec) tb="$tb elf32-rx.lo elf32.lo $elf" ;;
bfd_elf32_rx_be_ns_vec) tb="$tb elf32-rx.lo elf32.lo $elf" ;;
bfd_elf32_s390_vec) tb="$tb elf32-s390.lo elf32.lo $elf" ;;
bfd_elf32_bigscore_vec) tb="$tb elf32-score.lo elf32-score7.lo elf32.lo $elf"; want64=true; target_size=64;;
Index: bfd/cpu-rl78.c
===================================================================
RCS file: bfd/cpu-rl78.c
diff -N bfd/cpu-rl78.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ bfd/cpu-rl78.c 24 Oct 2011 22:25:16 -0000
@@ -0,0 +1,39 @@
+/* BFD support for the RL78 processor.
+ Copyright (C) 2011 Free Software Foundation, Inc.
+
+ This file is part of BFD, the Binary File Descriptor library.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ MA 02110-1301, USA. */
+
+#include "sysdep.h"
+#include "bfd.h"
+#include "libbfd.h"
+
+const bfd_arch_info_type bfd_rl78_arch =
+{
+ 32, /* Bits per word. */
+ 32, /* Bits per address. */
+ 8, /* Bits per byte. */
+ bfd_arch_rl78, /* Architecture. */
+ bfd_mach_rl78, /* Machine. */
+ "rl78", /* Architecture name. */
+ "rl78", /* Printable name. */
+ 4, /* Section align power. */
+ TRUE, /* The default ? */
+ bfd_default_compatible, /* Architecture comparison fn. */
+ bfd_default_scan, /* String to architecture convert fn. */
+ NULL /* Next in list. */
+};
Index: bfd/elf32-rl78.c
===================================================================
RCS file: bfd/elf32-rl78.c
diff -N bfd/elf32-rl78.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ bfd/elf32-rl78.c 24 Oct 2011 22:25:16 -0000
@@ -0,0 +1,1553 @@
+/* Renesas RL78 specific support for 32-bit ELF.
+ Copyright (C) 2011
+ Free Software Foundation, Inc.
+
+ This file is part of BFD, the Binary File Descriptor library.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+
+#include "sysdep.h"
+#include "bfd.h"
+#include "bfd_stdint.h"
+#include "libbfd.h"
+#include "elf-bfd.h"
+#include "elf/rl78.h"
+#include "libiberty.h"
+
+#define valid_16bit_address(v) ((v) <= 0x0ffff || (v) >= 0xf0000)
+
+#define RL78REL(n,sz,bit,shift,complain,pcrel) \
+ HOWTO (R_RL78_##n, shift, sz, bit, pcrel, 0, complain_overflow_ ## complain, \
+ bfd_elf_generic_reloc, "R_RL78_" #n, FALSE, 0, ~0, FALSE)
+
+/* Note that the relocations around 0x7f are internal to this file;
+ feel free to move them as needed to avoid conflicts with published
+ relocation numbers. */
+
+static reloc_howto_type rl78_elf_howto_table [] =
+{
+ RL78REL (NONE, 0, 0, 0, dont, FALSE),
+ RL78REL (DIR32, 2, 32, 0, signed, FALSE),
+ RL78REL (DIR24S, 2, 24, 0, signed, FALSE),
+ RL78REL (DIR16, 1, 16, 0, dont, FALSE),
+ RL78REL (DIR16U, 1, 16, 0, unsigned, FALSE),
+ RL78REL (DIR16S, 1, 16, 0, signed, FALSE),
+ RL78REL (DIR8, 0, 8, 0, dont, FALSE),
+ RL78REL (DIR8U, 0, 8, 0, unsigned, FALSE),
+ RL78REL (DIR8S, 0, 8, 0, signed, FALSE),
+ RL78REL (DIR24S_PCREL, 2, 24, 0, signed, TRUE),
+ RL78REL (DIR16S_PCREL, 1, 16, 0, signed, TRUE),
+ RL78REL (DIR8S_PCREL, 0, 8, 0, signed, TRUE),
+ RL78REL (DIR16UL, 1, 16, 2, unsigned, FALSE),
+ RL78REL (DIR16UW, 1, 16, 1, unsigned, FALSE),
+ RL78REL (DIR8UL, 0, 8, 2, unsigned, FALSE),
+ RL78REL (DIR8UW, 0, 8, 1, unsigned, FALSE),
+ RL78REL (DIR32_REV, 1, 16, 0, dont, FALSE),
+ RL78REL (DIR16_REV, 1, 16, 0, dont, FALSE),
+ RL78REL (DIR3U_PCREL, 0, 3, 0, dont, TRUE),
+
+ EMPTY_HOWTO (0x13),
+ EMPTY_HOWTO (0x14),
+ EMPTY_HOWTO (0x15),
+ EMPTY_HOWTO (0x16),
+ EMPTY_HOWTO (0x17),
+ EMPTY_HOWTO (0x18),
+ EMPTY_HOWTO (0x19),
+ EMPTY_HOWTO (0x1a),
+ EMPTY_HOWTO (0x1b),
+ EMPTY_HOWTO (0x1c),
+ EMPTY_HOWTO (0x1d),
+ EMPTY_HOWTO (0x1e),
+ EMPTY_HOWTO (0x1f),
+
+ EMPTY_HOWTO (0x20),
+ EMPTY_HOWTO (0x21),
+ EMPTY_HOWTO (0x22),
+ EMPTY_HOWTO (0x23),
+ EMPTY_HOWTO (0x24),
+ EMPTY_HOWTO (0x25),
+ EMPTY_HOWTO (0x26),
+ EMPTY_HOWTO (0x27),
+ EMPTY_HOWTO (0x28),
+ EMPTY_HOWTO (0x29),
+ EMPTY_HOWTO (0x2a),
+ EMPTY_HOWTO (0x2b),
+ EMPTY_HOWTO (0x2c),
+ EMPTY_HOWTO (0x2d),
+
+ EMPTY_HOWTO (0x2e),
+ EMPTY_HOWTO (0x2f),
+ EMPTY_HOWTO (0x30),
+ EMPTY_HOWTO (0x31),
+ EMPTY_HOWTO (0x32),
+ EMPTY_HOWTO (0x33),
+ EMPTY_HOWTO (0x34),
+ EMPTY_HOWTO (0x35),
+ EMPTY_HOWTO (0x36),
+ EMPTY_HOWTO (0x37),
+ EMPTY_HOWTO (0x38),
+ EMPTY_HOWTO (0x39),
+ EMPTY_HOWTO (0x3a),
+ EMPTY_HOWTO (0x3b),
+ EMPTY_HOWTO (0x3c),
+ EMPTY_HOWTO (0x3d),
+ EMPTY_HOWTO (0x3e),
+ EMPTY_HOWTO (0x3f),
+ EMPTY_HOWTO (0x40),
+
+ RL78REL (ABS32, 2, 32, 0, dont, FALSE),
+ RL78REL (ABS24S, 2, 24, 0, signed, FALSE),
+ RL78REL (ABS16, 1, 16, 0, dont, FALSE),
+ RL78REL (ABS16U, 1, 16, 0, unsigned, FALSE),
+ RL78REL (ABS16S, 1, 16, 0, signed, FALSE),
+ RL78REL (ABS8, 0, 8, 0, dont, FALSE),
+ RL78REL (ABS8U, 0, 8, 0, unsigned, FALSE),
+ RL78REL (ABS8S, 0, 8, 0, signed, FALSE),
+ RL78REL (ABS24S_PCREL, 2, 24, 0, signed, TRUE),
+ RL78REL (ABS16S_PCREL, 1, 16, 0, signed, TRUE),
+ RL78REL (ABS8S_PCREL, 0, 8, 0, signed, TRUE),
+ RL78REL (ABS16UL, 1, 16, 0, unsigned, FALSE),
+ RL78REL (ABS16UW, 1, 16, 0, unsigned, FALSE),
+ RL78REL (ABS8UL, 0, 8, 0, unsigned, FALSE),
+ RL78REL (ABS8UW, 0, 8, 0, unsigned, FALSE),
+ RL78REL (ABS32_REV, 2, 32, 0, dont, FALSE),
+ RL78REL (ABS16_REV, 1, 16, 0, dont, FALSE),
+
+#define STACK_REL_P(x) ((x) <= R_RL78_ABS16_REV && (x) >= R_RL78_ABS32)
+
+ EMPTY_HOWTO (0x52),
+ EMPTY_HOWTO (0x53),
+ EMPTY_HOWTO (0x54),
+ EMPTY_HOWTO (0x55),
+ EMPTY_HOWTO (0x56),
+ EMPTY_HOWTO (0x57),
+ EMPTY_HOWTO (0x58),
+ EMPTY_HOWTO (0x59),
+ EMPTY_HOWTO (0x5a),
+ EMPTY_HOWTO (0x5b),
+ EMPTY_HOWTO (0x5c),
+ EMPTY_HOWTO (0x5d),
+ EMPTY_HOWTO (0x5e),
+ EMPTY_HOWTO (0x5f),
+ EMPTY_HOWTO (0x60),
+ EMPTY_HOWTO (0x61),
+ EMPTY_HOWTO (0x62),
+ EMPTY_HOWTO (0x63),
+ EMPTY_HOWTO (0x64),
+ EMPTY_HOWTO (0x65),
+ EMPTY_HOWTO (0x66),
+ EMPTY_HOWTO (0x67),
+ EMPTY_HOWTO (0x68),
+ EMPTY_HOWTO (0x69),
+ EMPTY_HOWTO (0x6a),
+ EMPTY_HOWTO (0x6b),
+ EMPTY_HOWTO (0x6c),
+ EMPTY_HOWTO (0x6d),
+ EMPTY_HOWTO (0x6e),
+ EMPTY_HOWTO (0x6f),
+ EMPTY_HOWTO (0x70),
+ EMPTY_HOWTO (0x71),
+ EMPTY_HOWTO (0x72),
+ EMPTY_HOWTO (0x73),
+ EMPTY_HOWTO (0x74),
+ EMPTY_HOWTO (0x75),
+ EMPTY_HOWTO (0x76),
+ EMPTY_HOWTO (0x77),
+
+ EMPTY_HOWTO (0x78),
+ EMPTY_HOWTO (0x79),
+ EMPTY_HOWTO (0x7a),
+ EMPTY_HOWTO (0x7b),
+ EMPTY_HOWTO (0x7c),
+ EMPTY_HOWTO (0x7d),
+ EMPTY_HOWTO (0x7e),
+ EMPTY_HOWTO (0x7f),
+
+ RL78REL (SYM, 2, 32, 0, dont, FALSE),
+ RL78REL (OPneg, 2, 32, 0, dont, FALSE),
+ RL78REL (OPadd, 2, 32, 0, dont, FALSE),
+ RL78REL (OPsub, 2, 32, 0, dont, FALSE),
+ RL78REL (OPmul, 2, 32, 0, dont, FALSE),
+ RL78REL (OPdiv, 2, 32, 0, dont, FALSE),
+ RL78REL (OPshla, 2, 32, 0, dont, FALSE),
+ RL78REL (OPshra, 2, 32, 0, dont, FALSE),
+ RL78REL (OPsctsize, 2, 32, 0, dont, FALSE),
+ EMPTY_HOWTO (0x89),
+ EMPTY_HOWTO (0x8a),
+ EMPTY_HOWTO (0x8b),
+ EMPTY_HOWTO (0x8c),
+ RL78REL (OPscttop, 2, 32, 0, dont, FALSE),
+ EMPTY_HOWTO (0x8e),
+ EMPTY_HOWTO (0x8f),
+ RL78REL (OPand, 2, 32, 0, dont, FALSE),
+ RL78REL (OPor, 2, 32, 0, dont, FALSE),
+ RL78REL (OPxor, 2, 32, 0, dont, FALSE),
+ RL78REL (OPnot, 2, 32, 0, dont, FALSE),
+ RL78REL (OPmod, 2, 32, 0, dont, FALSE),
+ RL78REL (OPromtop, 2, 32, 0, dont, FALSE),
+ RL78REL (OPramtop, 2, 32, 0, dont, FALSE)
+};
+
+/* Map BFD reloc types to RL78 ELF reloc types. */
+
+struct rl78_reloc_map
+{
+ bfd_reloc_code_real_type bfd_reloc_val;
+ unsigned int rl78_reloc_val;
+};
+
+static const struct rl78_reloc_map rl78_reloc_map [] =
+{
+ { BFD_RELOC_NONE, R_RL78_NONE },
+ { BFD_RELOC_8, R_RL78_DIR8S },
+ { BFD_RELOC_16, R_RL78_DIR16S },
+ { BFD_RELOC_24, R_RL78_DIR24S },
+ { BFD_RELOC_32, R_RL78_DIR32 },
+ { BFD_RELOC_RL78_16_OP, R_RL78_DIR16 },
+ { BFD_RELOC_RL78_DIR3U_PCREL, R_RL78_DIR3U_PCREL },
+ { BFD_RELOC_8_PCREL, R_RL78_DIR8S_PCREL },
+ { BFD_RELOC_16_PCREL, R_RL78_DIR16S_PCREL },
+ { BFD_RELOC_24_PCREL, R_RL78_DIR24S_PCREL },
+ { BFD_RELOC_RL78_8U, R_RL78_DIR8U },
+ { BFD_RELOC_RL78_16U, R_RL78_DIR16U },
+ { BFD_RELOC_RL78_SYM, R_RL78_SYM },
+ { BFD_RELOC_RL78_OP_SUBTRACT, R_RL78_OPsub },
+ { BFD_RELOC_RL78_OP_NEG, R_RL78_OPneg },
+ { BFD_RELOC_RL78_OP_AND, R_RL78_OPand },
+ { BFD_RELOC_RL78_OP_SHRA, R_RL78_OPshra },
+ { BFD_RELOC_RL78_ABS8, R_RL78_ABS8 },
+ { BFD_RELOC_RL78_ABS16, R_RL78_ABS16 },
+ { BFD_RELOC_RL78_ABS16_REV, R_RL78_ABS16_REV },
+ { BFD_RELOC_RL78_ABS32, R_RL78_ABS32 },
+ { BFD_RELOC_RL78_ABS32_REV, R_RL78_ABS32_REV },
+ { BFD_RELOC_RL78_ABS16UL, R_RL78_ABS16UL },
+ { BFD_RELOC_RL78_ABS16UW, R_RL78_ABS16UW },
+ { BFD_RELOC_RL78_ABS16U, R_RL78_ABS16U }
+};
+
+static reloc_howto_type *
+rl78_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
+ bfd_reloc_code_real_type code)
+{
+ unsigned int i;
+
+ if (code == BFD_RELOC_RL78_32_OP)
+ return rl78_elf_howto_table + R_RL78_DIR32;
+
+ for (i = ARRAY_SIZE (rl78_reloc_map); --i;)
+ if (rl78_reloc_map [i].bfd_reloc_val == code)
+ return rl78_elf_howto_table + rl78_reloc_map[i].rl78_reloc_val;
+
+ return NULL;
+}
+
+static reloc_howto_type *
+rl78_reloc_name_lookup (bfd * abfd ATTRIBUTE_UNUSED, const char * r_name)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE (rl78_elf_howto_table); i++)
+ if (rl78_elf_howto_table[i].name != NULL
+ && strcasecmp (rl78_elf_howto_table[i].name, r_name) == 0)
+ return rl78_elf_howto_table + i;
+
+ return NULL;
+}
+
+/* Set the howto pointer for an RL78 ELF reloc. */
+
+static void
+rl78_info_to_howto_rela (bfd * abfd ATTRIBUTE_UNUSED,
+ arelent * cache_ptr,
+ Elf_Internal_Rela * dst)
+{
+ unsigned int r_type;
+
+ r_type = ELF32_R_TYPE (dst->r_info);
+ BFD_ASSERT (r_type < (unsigned int) R_RL78_max);
+ cache_ptr->howto = rl78_elf_howto_table + r_type;
+}
+
+static bfd_vma
+get_symbol_value (const char * name,
+ bfd_reloc_status_type * status,
+ struct bfd_link_info * info,
+ bfd * input_bfd,
+ asection * input_section,
+ int offset)
+{
+ bfd_vma value = 0;
+ struct bfd_link_hash_entry * h;
+
+ h = bfd_link_hash_lookup (info->hash, name, FALSE, FALSE, TRUE);
+
+ if (h == NULL
+ || (h->type != bfd_link_hash_defined
+ && h->type != bfd_link_hash_defweak))
+ * status = info->callbacks->undefined_symbol
+ (info, name, input_bfd, input_section, offset, TRUE);
+ else
+ value = (h->u.def.value
+ + h->u.def.section->output_section->vma
+ + h->u.def.section->output_offset);
+
+ return value;
+}
+
+static bfd_vma
+get_romstart (bfd_reloc_status_type * status,
+ struct bfd_link_info * info,
+ bfd * abfd,
+ asection * sec,
+ int offset)
+{
+ static bfd_boolean cached = FALSE;
+ static bfd_vma cached_value = 0;
+
+ if (!cached)
+ {
+ cached_value = get_symbol_value ("_start", status, info, abfd, sec, offset);
+ cached = TRUE;
+ }
+ return cached_value;
+}
+
+static bfd_vma
+get_ramstart (bfd_reloc_status_type * status,
+ struct bfd_link_info * info,
+ bfd * abfd,
+ asection * sec,
+ int offset)
+{
+ static bfd_boolean cached = FALSE;
+ static bfd_vma cached_value = 0;
+
+ if (!cached)
+ {
+ cached_value = get_symbol_value ("__datastart", status, info, abfd, sec, offset);
+ cached = TRUE;
+ }
+ return cached_value;
+}
+
+#define NUM_STACK_ENTRIES 16
+static int32_t rl78_stack [ NUM_STACK_ENTRIES ];
+static unsigned int rl78_stack_top;
+
+#define RL78_STACK_PUSH(val) \
+ do \
+ { \
+ if (rl78_stack_top < NUM_STACK_ENTRIES) \
+ rl78_stack [rl78_stack_top ++] = (val); \
+ else \
+ r = bfd_reloc_dangerous; \
+ } \
+ while (0)
+
+#define RL78_STACK_POP(dest) \
+ do \
+ { \
+ if (rl78_stack_top > 0) \
+ (dest) = rl78_stack [-- rl78_stack_top]; \
+ else \
+ (dest) = 0, r = bfd_reloc_dangerous; \
+ } \
+ while (0)
+
+/* Relocate an RL78 ELF section.
+ There is some attempt to make this function usable for many architectures,
+ both USE_REL and USE_RELA ['twould be nice if such a critter existed],
+ if only to serve as a learning tool.
+
+ The RELOCATE_SECTION function is called by the new ELF backend linker
+ to handle the relocations for a section.
+
+ The relocs are always passed as Rela structures; if the section
+ actually uses Rel structures, the r_addend field will always be
+ zero.
+
+ This function is responsible for adjusting the section contents as
+ necessary, and (if using Rela relocs and generating a relocatable
+ output file) adjusting the reloc addend as necessary.
+
+ This function does not have to worry about setting the reloc
+ address or the reloc symbol index.
+
+ LOCAL_SYMS is a pointer to the swapped in local symbols.
+
+ LOCAL_SECTIONS is an array giving the section in the input file
+ corresponding to the st_shndx field of each local symbol.
+
+ The global hash table entry for the global symbols can be found
+ via elf_sym_hashes (input_bfd).
+
+ When generating relocatable output, this function must handle
+ STB_LOCAL/STT_SECTION symbols specially. The output symbol is
+ going to be the section symbol corresponding to the output
+ section, which means that the addend must be adjusted
+ accordingly. */
+
+static bfd_boolean
+rl78_elf_relocate_section
+ (bfd * output_bfd,
+ struct bfd_link_info * info,
+ bfd * input_bfd,
+ asection * input_section,
+ bfd_byte * contents,
+ Elf_Internal_Rela * relocs,
+ Elf_Internal_Sym * local_syms,
+ asection ** local_sections)
+{
+ Elf_Internal_Shdr * symtab_hdr;
+ struct elf_link_hash_entry ** sym_hashes;
+ Elf_Internal_Rela * rel;
+ Elf_Internal_Rela * relend;
+ bfd *dynobj;
+ asection *splt;
+
+ symtab_hdr = & elf_tdata (input_bfd)->symtab_hdr;
+ sym_hashes = elf_sym_hashes (input_bfd);
+ relend = relocs + input_section->reloc_count;
+
+ dynobj = elf_hash_table (info)->dynobj;
+ splt = NULL;
+ if (dynobj != NULL)
+ splt = bfd_get_section_by_name (dynobj, ".plt");
+
+ for (rel = relocs; rel < relend; rel ++)
+ {
+ reloc_howto_type * howto;
+ unsigned long r_symndx;
+ Elf_Internal_Sym * sym;
+ asection * sec;
+ struct elf_link_hash_entry * h;
+ bfd_vma relocation;
+ bfd_reloc_status_type r;
+ const char * name = NULL;
+ bfd_boolean unresolved_reloc = TRUE;
+ int r_type;
+
+ r_type = ELF32_R_TYPE (rel->r_info);
+ r_symndx = ELF32_R_SYM (rel->r_info);
+
+ howto = rl78_elf_howto_table + ELF32_R_TYPE (rel->r_info);
+ h = NULL;
+ sym = NULL;
+ sec = NULL;
+ relocation = 0;
+
+ if (r_symndx < symtab_hdr->sh_info)
+ {
+ sym = local_syms + r_symndx;
+ sec = local_sections [r_symndx];
+ relocation = _bfd_elf_rela_local_sym (output_bfd, sym, & sec, rel);
+
+ name = bfd_elf_string_from_elf_section
+ (input_bfd, symtab_hdr->sh_link, sym->st_name);
+ name = (sym->st_name == 0) ? bfd_section_name (input_bfd, sec) : name;
+ }
+ else
+ {
+ bfd_boolean warned;
+
+ RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
+ r_symndx, symtab_hdr, sym_hashes, h,
+ sec, relocation, unresolved_reloc,
+ warned);
+
+ name = h->root.root.string;
+ }
+
+ if (sec != NULL && elf_discarded_section (sec))
+ RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
+ rel, relend, howto, contents);
+
+ if (info->relocatable)
+ {
+ /* This is a relocatable link. We don't have to change
+ anything, unless the reloc is against a section symbol,
+ in which case we have to adjust according to where the
+ section symbol winds up in the output section. */
+ if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
+ rel->r_addend += sec->output_offset;
+ continue;
+ }
+
+ switch (ELF32_R_TYPE (rel->r_info))
+ {
+ case R_RL78_DIR16S:
+ {
+ bfd_vma *plt_offset;
+
+ if (h != NULL)
+ plt_offset = &h->plt.offset;
+ else
+ plt_offset = elf_local_got_offsets (input_bfd) + r_symndx;
+
+ /* printf("%s: rel %x plt %d\n", h ? h->root.root.string : "(none)",
+ relocation, *plt_offset);*/
+ if (valid_16bit_address (relocation))
+ {
+ /* If the symbol is in range for a 16-bit address, we should
+ have deallocated the plt entry in relax_section. */
+ BFD_ASSERT (*plt_offset == (bfd_vma) -1);
+ }
+ else
+ {
+ /* If the symbol is out of range for a 16-bit address,
+ we must have allocated a plt entry. */
+ BFD_ASSERT (*plt_offset != (bfd_vma) -1);
+
+ /* If this is the first time we've processed this symbol,
+ fill in the plt entry with the correct symbol address. */
+ if ((*plt_offset & 1) == 0)
+ {
+ unsigned int x;
+
+ x = 0x000000ec; /* br !!abs24 */
+ x |= (relocation << 8) & 0xffffff00;
+ bfd_put_32 (input_bfd, x, splt->contents + *plt_offset);
+ *plt_offset |= 1;
+ }
+
+ relocation = (splt->output_section->vma
+ + splt->output_offset
+ + (*plt_offset & -2));
+ if (name)
+ {
+ char *newname = bfd_malloc (strlen(name)+5);
+ strcpy (newname, name);
+ strcat(newname, ".plt");
+ _bfd_generic_link_add_one_symbol (info,
+ input_bfd,
+ newname,
+ BSF_FUNCTION | BSF_WEAK,
+ splt,
+ (*plt_offset & -2),
+ 0,
+ 1,
+ 0,
+ 0);
+ }
+ }
+ }
+ break;
+ }
+
+ if (h != NULL && h->root.type == bfd_link_hash_undefweak)
+ /* If the symbol is undefined and weak
+ then the relocation resolves to zero. */
+ relocation = 0;
+ else
+ {
+ if (howto->pc_relative)
+ {
+ relocation -= (input_section->output_section->vma
+ + input_section->output_offset
+ + rel->r_offset);
+ relocation -= bfd_get_reloc_size (howto);
+ }
+
+ relocation += rel->r_addend;
+ }
+
+ r = bfd_reloc_ok;
+
+#define RANGE(a,b) if (a > (long) relocation || (long) relocation > b) r = bfd_reloc_overflow
+#define ALIGN(m) if (relocation & m) r = bfd_reloc_other;
+#define OP(i) (contents[rel->r_offset + (i)])
+
+ /* Opcode relocs are always big endian. Data relocs are bi-endian. */
+ switch (r_type)
+ {
+ case R_RL78_NONE:
+ break;
+
+ case R_RL78_DIR8S_PCREL:
+ RANGE (-128, 127);
+ OP (0) = relocation;
+ break;
+
+ case R_RL78_DIR8S:
+ RANGE (-128, 255);
+ OP (0) = relocation;
+ break;
+
+ case R_RL78_DIR8U:
+ RANGE (0, 255);
+ OP (0) = relocation;
+ break;
+
+ case R_RL78_DIR16S_PCREL:
+ RANGE (-32768, 32767);
+ OP (0) = relocation;
+ OP (1) = relocation >> 8;
+ break;
+
+ case R_RL78_DIR16S:
+ if ((relocation & 0xf0000) == 0xf0000)
+ relocation &= 0xffff;
+ RANGE (-32768, 65535);
+ OP (0) = relocation;
+ OP (1) = relocation >> 8;
+ break;
+
+ case R_RL78_DIR16U:
+ RANGE (0, 65536);
+ OP (0) = relocation;
+ OP (1) = relocation >> 8;
+ break;
+
+ case R_RL78_DIR16:
+ RANGE (-32768, 65536);
+ OP (0) = relocation;
+ OP (1) = relocation >> 8;
+ break;
+
+ case R_RL78_DIR16_REV:
+ RANGE (-32768, 65536);
+ OP (1) = relocation;
+ OP (0) = relocation >> 8;
+ break;
+
+ case R_RL78_DIR3U_PCREL:
+ RANGE (3, 10);
+ OP (0) &= 0xf8;
+ OP (0) |= relocation & 0x07;
+ break;
+
+ case R_RL78_DIR24S_PCREL:
+ RANGE (-0x800000, 0x7fffff);
+ OP (0) = relocation;
+ OP (1) = relocation >> 8;
+ OP (2) = relocation >> 16;
+ break;
+
+ case R_RL78_DIR24S:
+ RANGE (-0x800000, 0x7fffff);
+ OP (0) = relocation;
+ OP (1) = relocation >> 8;
+ OP (2) = relocation >> 16;
+ break;
+
+ case R_RL78_DIR32:
+ OP (0) = relocation;
+ OP (1) = relocation >> 8;
+ OP (2) = relocation >> 16;
+ OP (3) = relocation >> 24;
+ break;
+
+ case R_RL78_DIR32_REV:
+ OP (3) = relocation;
+ OP (2) = relocation >> 8;
+ OP (1) = relocation >> 16;
+ OP (0) = relocation >> 24;
+ break;
+
+ /* Complex reloc handling: */
+
+ case R_RL78_ABS32:
+ RL78_STACK_POP (relocation);
+ OP (0) = relocation;
+ OP (1) = relocation >> 8;
+ OP (2) = relocation >> 16;
+ OP (3) = relocation >> 24;
+ break;
+
+ case R_RL78_ABS32_REV:
+ RL78_STACK_POP (relocation);
+ OP (3) = relocation;
+ OP (2) = relocation >> 8;
+ OP (1) = relocation >> 16;
+ OP (0) = relocation >> 24;
+ break;
+
+ case R_RL78_ABS24S_PCREL:
+ case R_RL78_ABS24S:
+ RL78_STACK_POP (relocation);
+ RANGE (-0x800000, 0x7fffff);
+ OP (0) = relocation;
+ OP (1) = relocation >> 8;
+ OP (2) = relocation >> 16;
+ break;
+
+ case R_RL78_ABS16:
+ RL78_STACK_POP (relocation);
+ RANGE (-32768, 65535);
+ OP (0) = relocation;
+ OP (1) = relocation >> 8;
+ break;
+
+ case R_RL78_ABS16_REV:
+ RL78_STACK_POP (relocation);
+ RANGE (-32768, 65535);
+ OP (1) = relocation;
+ OP (0) = relocation >> 8;
+ break;
+
+ case R_RL78_ABS16S_PCREL:
+ case R_RL78_ABS16S:
+ RL78_STACK_POP (relocation);
+ RANGE (-32768, 32767);
+ OP (0) = relocation;
+ OP (1) = relocation >> 8;
+ break;
+
+ case R_RL78_ABS16U:
+ RL78_STACK_POP (relocation);
+ RANGE (0, 65536);
+ OP (0) = relocation;
+ OP (1) = relocation >> 8;
+ break;
+
+ case R_RL78_ABS16UL:
+ RL78_STACK_POP (relocation);
+ relocation >>= 2;
+ RANGE (0, 65536);
+ OP (0) = relocation;
+ OP (1) = relocation >> 8;
+ break;
+
+ case R_RL78_ABS16UW:
+ RL78_STACK_POP (relocation);
+ relocation >>= 1;
+ RANGE (0, 65536);
+ OP (0) = relocation;
+ OP (1) = relocation >> 8;
+ break;
+
+ case R_RL78_ABS8:
+ RL78_STACK_POP (relocation);
+ RANGE (-128, 255);
+ OP (0) = relocation;
+ break;
+
+ case R_RL78_ABS8U:
+ RL78_STACK_POP (relocation);
+ RANGE (0, 255);
+ OP (0) = relocation;
+ break;
+
+ case R_RL78_ABS8UL:
+ RL78_STACK_POP (relocation);
+ relocation >>= 2;
+ RANGE (0, 255);
+ OP (0) = relocation;
+ break;
+
+ case R_RL78_ABS8UW:
+ RL78_STACK_POP (relocation);
+ relocation >>= 1;
+ RANGE (0, 255);
+ OP (0) = relocation;
+ break;
+
+ case R_RL78_ABS8S_PCREL:
+ case R_RL78_ABS8S:
+ RL78_STACK_POP (relocation);
+ RANGE (-128, 127);
+ OP (0) = relocation;
+ break;
+
+ case R_RL78_SYM:
+ if (r_symndx < symtab_hdr->sh_info)
+ RL78_STACK_PUSH (sec->output_section->vma
+ + sec->output_offset
+ + sym->st_value
+ + rel->r_addend);
+ else
+ {
+ if (h != NULL
+ && (h->root.type == bfd_link_hash_defined
+ || h->root.type == bfd_link_hash_defweak))
+ RL78_STACK_PUSH (h->root.u.def.value
+ + sec->output_section->vma
+ + sec->output_offset
+ + rel->r_addend);
+ else
+ _bfd_error_handler (_("Warning: RL78_SYM reloc with an unknown symbol"));
+ }
+ break;
+
+ case R_RL78_OPneg:
+ {
+ int32_t tmp;
+
+ RL78_STACK_POP (tmp);
+ tmp = - tmp;
+ RL78_STACK_PUSH (tmp);
+ }
+ break;
+
+ case R_RL78_OPadd:
+ {
+ int32_t tmp1, tmp2;
+
+ RL78_STACK_POP (tmp2);
+ RL78_STACK_POP (tmp1);
+ tmp1 += tmp2;
+ RL78_STACK_PUSH (tmp1);
+ }
+ break;
+
+ case R_RL78_OPsub:
+ {
+ int32_t tmp1, tmp2;
+
+ RL78_STACK_POP (tmp2);
+ RL78_STACK_POP (tmp1);
+ tmp2 -= tmp1;
+ RL78_STACK_PUSH (tmp2);
+ }
+ break;
+
+ case R_RL78_OPmul:
+ {
+ int32_t tmp1, tmp2;
+
+ RL78_STACK_POP (tmp2);
+ RL78_STACK_POP (tmp1);
+ tmp1 *= tmp2;
+ RL78_STACK_PUSH (tmp1);
+ }
+ break;
+
+ case R_RL78_OPdiv:
+ {
+ int32_t tmp1, tmp2;
+
+ RL78_STACK_POP (tmp2);
+ RL78_STACK_POP (tmp1);
+ tmp1 /= tmp2;
+ RL78_STACK_PUSH (tmp1);
+ }
+ break;
+
+ case R_RL78_OPshla:
+ {
+ int32_t tmp1, tmp2;
+
+ RL78_STACK_POP (tmp2);
+ RL78_STACK_POP (tmp1);
+ tmp1 <<= tmp2;
+ RL78_STACK_PUSH (tmp1);
+ }
+ break;
+
+ case R_RL78_OPshra:
+ {
+ int32_t tmp1, tmp2;
+
+ RL78_STACK_POP (tmp2);
+ RL78_STACK_POP (tmp1);
+ tmp1 >>= tmp2;
+ RL78_STACK_PUSH (tmp1);
+ }
+ break;
+
+ case R_RL78_OPsctsize:
+ RL78_STACK_PUSH (input_section->size);
+ break;
+
+ case R_RL78_OPscttop:
+ RL78_STACK_PUSH (input_section->output_section->vma);
+ break;
+
+ case R_RL78_OPand:
+ {
+ int32_t tmp1, tmp2;
+
+ RL78_STACK_POP (tmp2);
+ RL78_STACK_POP (tmp1);
+ tmp1 &= tmp2;
+ RL78_STACK_PUSH (tmp1);
+ }
+ break;
+
+ case R_RL78_OPor:
+ {
+ int32_t tmp1, tmp2;
+
+ RL78_STACK_POP (tmp2);
+ RL78_STACK_POP (tmp1);
+ tmp1 |= tmp2;
+ RL78_STACK_PUSH (tmp1);
+ }
+ break;
+
+ case R_RL78_OPxor:
+ {
+ int32_t tmp1, tmp2;
+
+ RL78_STACK_POP (tmp2);
+ RL78_STACK_POP (tmp1);
+ tmp1 ^= tmp2;
+ RL78_STACK_PUSH (tmp1);
+ }
+ break;
+
+ case R_RL78_OPnot:
+ {
+ int32_t tmp;
+
+ RL78_STACK_POP (tmp);
+ tmp = ~ tmp;
+ RL78_STACK_PUSH (tmp);
+ }
+ break;
+
+ case R_RL78_OPmod:
+ {
+ int32_t tmp1, tmp2;
+
+ RL78_STACK_POP (tmp2);
+ RL78_STACK_POP (tmp1);
+ tmp1 %= tmp2;
+ RL78_STACK_PUSH (tmp1);
+ }
+ break;
+
+ case R_RL78_OPromtop:
+ RL78_STACK_PUSH (get_romstart (&r, info, input_bfd, input_section, rel->r_offset));
+ break;
+
+ case R_RL78_OPramtop:
+ RL78_STACK_PUSH (get_ramstart (&r, info, input_bfd, input_section, rel->r_offset));
+ break;
+
+ default:
+ r = bfd_reloc_notsupported;
+ break;
+ }
+
+ if (r != bfd_reloc_ok)
+ {
+ const char * msg = NULL;
+
+ switch (r)
+ {
+ case bfd_reloc_overflow:
+ /* Catch the case of a missing function declaration
+ and emit a more helpful error message. */
+ if (r_type == R_RL78_DIR24S_PCREL)
+ msg = _("%B(%A): error: call to undefined function '%s'");
+ else
+ r = info->callbacks->reloc_overflow
+ (info, (h ? &h->root : NULL), name, howto->name, (bfd_vma) 0,
+ input_bfd, input_section, rel->r_offset);
+ break;
+
+ case bfd_reloc_undefined:
+ r = info->callbacks->undefined_symbol
+ (info, name, input_bfd, input_section, rel->r_offset,
+ TRUE);
+ break;
+
+ case bfd_reloc_other:
+ msg = _("%B(%A): warning: unaligned access to symbol '%s' in the small data area");
+ break;
+
+ case bfd_reloc_outofrange:
+ msg = _("%B(%A): internal error: out of range error");
+ break;
+
+ case bfd_reloc_notsupported:
+ msg = _("%B(%A): internal error: unsupported relocation error");
+ break;
+
+ case bfd_reloc_dangerous:
+ msg = _("%B(%A): internal error: dangerous relocation");
+ break;
+
+ default:
+ msg = _("%B(%A): internal error: unknown error");
+ break;
+ }
+
+ if (msg)
+ _bfd_error_handler (msg, input_bfd, input_section, name);
+
+ if (! r)
+ return FALSE;
+ }
+ }
+
+ return TRUE;
+}
+
+/* Function to set the ELF flag bits. */
+
+static bfd_boolean
+rl78_elf_set_private_flags (bfd * abfd, flagword flags)
+{
+ elf_elfheader (abfd)->e_flags = flags;
+ elf_flags_init (abfd) = TRUE;
+ return TRUE;
+}
+
+static bfd_boolean no_warn_mismatch = FALSE;
+
+void bfd_elf32_rl78_set_target_flags (bfd_boolean);
+
+void
+bfd_elf32_rl78_set_target_flags (bfd_boolean user_no_warn_mismatch)
+{
+ no_warn_mismatch = user_no_warn_mismatch;
+}
+
+/* Merge backend specific data from an object file to the output
+ object file when linking. */
+
+static bfd_boolean
+rl78_elf_merge_private_bfd_data (bfd * ibfd, bfd * obfd)
+{
+ flagword old_flags;
+ flagword new_flags;
+ bfd_boolean error = FALSE;
+
+ new_flags = elf_elfheader (ibfd)->e_flags;
+ old_flags = elf_elfheader (obfd)->e_flags;
+
+ if (!elf_flags_init (obfd))
+ {
+ /* First call, no flags set. */
+ elf_flags_init (obfd) = TRUE;
+ elf_elfheader (obfd)->e_flags = new_flags;
+ }
+
+ return !error;
+}
+
+static bfd_boolean
+rl78_elf_print_private_bfd_data (bfd * abfd, void * ptr)
+{
+ FILE * file = (FILE *) ptr;
+ flagword flags;
+
+ BFD_ASSERT (abfd != NULL && ptr != NULL);
+
+ /* Print normal ELF private data. */
+ _bfd_elf_print_private_bfd_data (abfd, ptr);
+
+ flags = elf_elfheader (abfd)->e_flags;
+ fprintf (file, _("private flags = 0x%lx:"), (long) flags);
+
+ fputc ('\n', file);
+ return TRUE;
+}
+
+/* Return the MACH for an e_flags value. */
+
+static int
+elf32_rl78_machine (bfd * abfd)
+{
+ if ((elf_elfheader (abfd)->e_flags & EF_RL78_CPU_MASK) == EF_RL78_CPU_RL78)
+ return bfd_mach_rl78;
+
+ return 0;
+}
+
+static bfd_boolean
+rl78_elf_object_p (bfd * abfd)
+{
+ bfd_default_set_arch_mach (abfd, bfd_arch_rl78,
+ elf32_rl78_machine (abfd));
+ return TRUE;
+}
+
+#ifdef DEBUG
+void
+rl78_dump_symtab (bfd * abfd, void * internal_syms, void * external_syms)
+{
+ size_t locsymcount;
+ Elf_Internal_Sym * isymbuf;
+ Elf_Internal_Sym * isymend;
+ Elf_Internal_Sym * isym;
+ Elf_Internal_Shdr * symtab_hdr;
+ bfd_boolean free_internal = FALSE, free_external = FALSE;
+ char * st_info_str;
+ char * st_info_stb_str;
+ char * st_other_str;
+ char * st_shndx_str;
+
+ if (! internal_syms)
+ {
+ internal_syms = bfd_malloc (1000);
+ free_internal = 1;
+ }
+ if (! external_syms)
+ {
+ external_syms = bfd_malloc (1000);
+ free_external = 1;
+ }
+
+ symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
+ locsymcount = symtab_hdr->sh_size / get_elf_backend_data (abfd)->s->sizeof_sym;
+ if (free_internal)
+ isymbuf = bfd_elf_get_elf_syms (abfd, symtab_hdr,
+ symtab_hdr->sh_info, 0,
+ internal_syms, external_syms, NULL);
+ else
+ isymbuf = internal_syms;
+ isymend = isymbuf + locsymcount;
+
+ for (isym = isymbuf ; isym < isymend ; isym++)
+ {
+ switch (ELF_ST_TYPE (isym->st_info))
+ {
+ case STT_FUNC: st_info_str = "STT_FUNC";
+ case STT_SECTION: st_info_str = "STT_SECTION";
+ case STT_FILE: st_info_str = "STT_FILE";
+ case STT_OBJECT: st_info_str = "STT_OBJECT";
+ case STT_TLS: st_info_str = "STT_TLS";
+ default: st_info_str = "";
+ }
+ switch (ELF_ST_BIND (isym->st_info))
+ {
+ case STB_LOCAL: st_info_stb_str = "STB_LOCAL";
+ case STB_GLOBAL: st_info_stb_str = "STB_GLOBAL";
+ default: st_info_stb_str = "";
+ }
+ switch (ELF_ST_VISIBILITY (isym->st_other))
+ {
+ case STV_DEFAULT: st_other_str = "STV_DEFAULT";
+ case STV_INTERNAL: st_other_str = "STV_INTERNAL";
+ case STV_PROTECTED: st_other_str = "STV_PROTECTED";
+ default: st_other_str = "";
+ }
+ switch (isym->st_shndx)
+ {
+ case SHN_ABS: st_shndx_str = "SHN_ABS";
+ case SHN_COMMON: st_shndx_str = "SHN_COMMON";
+ case SHN_UNDEF: st_shndx_str = "SHN_UNDEF";
+ default: st_shndx_str = "";
+ }
+
+ printf ("isym = %p st_value = %lx st_size = %lx st_name = (%lu) %s "
+ "st_info = (%d) %s %s st_other = (%d) %s st_shndx = (%d) %s\n",
+ isym,
+ (unsigned long) isym->st_value,
+ (unsigned long) isym->st_size,
+ isym->st_name,
+ bfd_elf_string_from_elf_section (abfd, symtab_hdr->sh_link,
+ isym->st_name),
+ isym->st_info, st_info_str, st_info_stb_str,
+ isym->st_other, st_other_str,
+ isym->st_shndx, st_shndx_str);
+ }
+ if (free_internal)
+ free (internal_syms);
+ if (free_external)
+ free (external_syms);
+}
+
+char *
+rl78_get_reloc (long reloc)
+{
+ if (0 <= reloc && reloc < R_RL78_max)
+ return rl78_elf_howto_table[reloc].name;
+ return "";
+}
+#endif /* DEBUG */
+
+
+/* support PLT for 16-bit references to 24-bit functions. */
+
+/* We support 16-bit pointers to code above 64k by generating a thunk
+ below 64k containing a JMP instruction to the final address. */
+
+static bfd_boolean
+rl78_elf_check_relocs
+ (bfd * abfd,
+ struct bfd_link_info * info,
+ asection * sec,
+ const Elf_Internal_Rela * relocs)
+{
+ Elf_Internal_Shdr * symtab_hdr;
+ struct elf_link_hash_entry ** sym_hashes;
+ const Elf_Internal_Rela * rel;
+ const Elf_Internal_Rela * rel_end;
+ bfd_vma *local_plt_offsets;
+ asection *splt;
+ bfd *dynobj;
+
+ if (info->relocatable)
+ return TRUE;
+
+ symtab_hdr = &elf_tdata (abfd)->symtab_hdr;
+ sym_hashes = elf_sym_hashes (abfd);
+ local_plt_offsets = elf_local_got_offsets (abfd);
+ splt = NULL;
+ dynobj = elf_hash_table(info)->dynobj;
+
+ rel_end = relocs + sec->reloc_count;
+ for (rel = relocs; rel < rel_end; rel++)
+ {
+ struct elf_link_hash_entry *h;
+ unsigned long r_symndx;
+ bfd_vma *offset;
+
+ r_symndx = ELF32_R_SYM (rel->r_info);
+ if (r_symndx < symtab_hdr->sh_info)
+ h = NULL;
+ else
+ {
+ h = sym_hashes[r_symndx - symtab_hdr->sh_info];
+ while (h->root.type == bfd_link_hash_indirect
+ || h->root.type == bfd_link_hash_warning)
+ h = (struct elf_link_hash_entry *) h->root.u.i.link;
+ }
+
+ switch (ELF32_R_TYPE (rel->r_info))
+ {
+ /* This relocation describes a 16-bit pointer to a function.
+ We may need to allocate a thunk in low memory; reserve memory
+ for it now. */
+ case R_RL78_DIR16S:
+ if (dynobj == NULL)
+ elf_hash_table (info)->dynobj = dynobj = abfd;
+ if (splt == NULL)
+ {
+ splt = bfd_get_section_by_name (dynobj, ".plt");
+ if (splt == NULL)
+ {
+ flagword flags = (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS
+ | SEC_IN_MEMORY | SEC_LINKER_CREATED
+ | SEC_READONLY | SEC_CODE);
+ splt = bfd_make_section_with_flags (dynobj, ".plt", flags);
+ if (splt == NULL
+ || ! bfd_set_section_alignment (dynobj, splt, 1))
+ return FALSE;
+ }
+ }
+
+ if (h != NULL)
+ offset = &h->plt.offset;
+ else
+ {
+ if (local_plt_offsets == NULL)
+ {
+ size_t size;
+ unsigned int i;
+
+ size = symtab_hdr->sh_info * sizeof (bfd_vma);
+ local_plt_offsets = (bfd_vma *) bfd_alloc (abfd, size);
+ if (local_plt_offsets == NULL)
+ return FALSE;
+ elf_local_got_offsets (abfd) = local_plt_offsets;
+
+ for (i = 0; i < symtab_hdr->sh_info; i++)
+ local_plt_offsets[i] = (bfd_vma) -1;
+ }
+ offset = &local_plt_offsets[r_symndx];
+ }
+
+ if (*offset == (bfd_vma) -1)
+ {
+ *offset = splt->size;
+ splt->size += 4;
+ }
+ break;
+ }
+ }
+
+ return TRUE;
+}
+
+/* This must exist if dynobj is ever set. */
+
+static bfd_boolean
+rl78_elf_finish_dynamic_sections (bfd *abfd ATTRIBUTE_UNUSED,
+ struct bfd_link_info *info)
+{
+ bfd *dynobj;
+ asection *splt;
+
+ /* As an extra sanity check, verify that all plt entries have
+ been filled in. */
+
+ if ((dynobj = elf_hash_table (info)->dynobj) != NULL
+ && (splt = bfd_get_section_by_name (dynobj, ".plt")) != NULL)
+ {
+ bfd_byte *contents = splt->contents;
+ unsigned int i, size = splt->size;
+ for (i = 0; i < size; i += 4)
+ {
+ unsigned int x = bfd_get_32 (dynobj, contents + i);
+ BFD_ASSERT (x != 0);
+ }
+ }
+
+ return TRUE;
+}
+
+static bfd_boolean
+rl78_elf_always_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
+ struct bfd_link_info *info)
+{
+ bfd *dynobj;
+ asection *splt;
+
+ if (info->relocatable)
+ return TRUE;
+
+ dynobj = elf_hash_table (info)->dynobj;
+ if (dynobj == NULL)
+ return TRUE;
+
+ splt = bfd_get_section_by_name (dynobj, ".plt");
+ BFD_ASSERT (splt != NULL);
+
+ splt->contents = (bfd_byte *) bfd_zalloc (dynobj, splt->size);
+ if (splt->contents == NULL)
+ return FALSE;
+
+ return TRUE;
+}
+
+
+
+/* Handle relaxing. */
+
+/* A subroutine of rl78_elf_relax_section. If the global symbol H
+ is within the low 64k, remove any entry for it in the plt. */
+
+struct relax_plt_data
+{
+ asection *splt;
+ bfd_boolean *again;
+};
+
+static bfd_boolean
+rl78_relax_plt_check (struct elf_link_hash_entry *h,
+ PTR xdata)
+{
+ struct relax_plt_data *data = (struct relax_plt_data *) xdata;
+
+ if (h->plt.offset != (bfd_vma) -1)
+ {
+ bfd_vma address;
+
+ if (h->root.type == bfd_link_hash_undefined
+ || h->root.type == bfd_link_hash_undefweak)
+ address = 0;
+ else
+ address = (h->root.u.def.section->output_section->vma
+ + h->root.u.def.section->output_offset
+ + h->root.u.def.value);
+
+ if (valid_16bit_address (address))
+ {
+ h->plt.offset = -1;
+ data->splt->size -= 4;
+ *data->again = TRUE;
+ }
+ }
+
+ return TRUE;
+}
+
+/* A subroutine of rl78_elf_relax_section. If the global symbol H
+ previously had a plt entry, give it a new entry offset. */
+
+static bfd_boolean
+rl78_relax_plt_realloc (struct elf_link_hash_entry *h,
+ PTR xdata)
+{
+ bfd_vma *entry = (bfd_vma *) xdata;
+
+ if (h->plt.offset != (bfd_vma) -1)
+ {
+ h->plt.offset = *entry;
+ *entry += 4;
+ }
+
+ return TRUE;
+}
+
+static bfd_boolean
+rl78_elf_relax_plt_section (bfd *dynobj,
+ asection *splt,
+ struct bfd_link_info *info,
+ bfd_boolean *again)
+{
+ struct relax_plt_data relax_plt_data;
+ bfd *ibfd;
+
+ /* Assume nothing changes. */
+ *again = FALSE;
+
+ if (info->relocatable)
+ return TRUE;
+
+ /* We only relax the .plt section at the moment. */
+ if (dynobj != elf_hash_table (info)->dynobj
+ || strcmp (splt->name, ".plt") != 0)
+ return TRUE;
+
+ /* Quick check for an empty plt. */
+ if (splt->size == 0)
+ return TRUE;
+
+ /* Map across all global symbols; see which ones happen to
+ fall in the low 64k. */
+ relax_plt_data.splt = splt;
+ relax_plt_data.again = again;
+ elf_link_hash_traverse (elf_hash_table (info), rl78_relax_plt_check,
+ &relax_plt_data);
+
+ /* Likewise for local symbols, though that's somewhat less convenient
+ as we have to walk the list of input bfds and swap in symbol data. */
+ for (ibfd = info->input_bfds; ibfd ; ibfd = ibfd->link_next)
+ {
+ bfd_vma *local_plt_offsets = elf_local_got_offsets (ibfd);
+ Elf_Internal_Shdr *symtab_hdr;
+ Elf_Internal_Sym *isymbuf = NULL;
+ unsigned int idx;
+
+ if (! local_plt_offsets)
+ continue;
+
+ symtab_hdr = &elf_tdata (ibfd)->symtab_hdr;
+ if (symtab_hdr->sh_info != 0)
+ {
+ isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
+ if (isymbuf == NULL)
+ isymbuf = bfd_elf_get_elf_syms (ibfd, symtab_hdr,
+ symtab_hdr->sh_info, 0,
+ NULL, NULL, NULL);
+ if (isymbuf == NULL)
+ return FALSE;
+ }
+
+ for (idx = 0; idx < symtab_hdr->sh_info; ++idx)
+ {
+ Elf_Internal_Sym *isym;
+ asection *tsec;
+ bfd_vma address;
+
+ if (local_plt_offsets[idx] == (bfd_vma) -1)
+ continue;
+
+ isym = &isymbuf[idx];
+ if (isym->st_shndx == SHN_UNDEF)
+ continue;
+ else if (isym->st_shndx == SHN_ABS)
+ tsec = bfd_abs_section_ptr;
+ else if (isym->st_shndx == SHN_COMMON)
+ tsec = bfd_com_section_ptr;
+ else
+ tsec = bfd_section_from_elf_index (ibfd, isym->st_shndx);
+
+ address = (tsec->output_section->vma
+ + tsec->output_offset
+ + isym->st_value);
+ if (valid_16bit_address (address))
+ {
+ local_plt_offsets[idx] = -1;
+ splt->size -= 4;
+ *again = TRUE;
+ }
+ }
+
+ if (isymbuf != NULL
+ && symtab_hdr->contents != (unsigned char *) isymbuf)
+ {
+ if (! info->keep_memory)
+ free (isymbuf);
+ else
+ {
+ /* Cache the symbols for elf_link_input_bfd. */
+ symtab_hdr->contents = (unsigned char *) isymbuf;
+ }
+ }
+ }
+
+ /* If we changed anything, walk the symbols again to reallocate
+ .plt entry addresses. */
+ if (*again && splt->size > 0)
+ {
+ bfd_vma entry = 0;
+
+ elf_link_hash_traverse (elf_hash_table (info),
+ rl78_relax_plt_realloc, &entry);
+
+ for (ibfd = info->input_bfds; ibfd ; ibfd = ibfd->link_next)
+ {
+ bfd_vma *local_plt_offsets = elf_local_got_offsets (ibfd);
+ unsigned int nlocals = elf_tdata (ibfd)->symtab_hdr.sh_info;
+ unsigned int idx;
+
+ if (! local_plt_offsets)
+ continue;
+
+ for (idx = 0; idx < nlocals; ++idx)
+ if (local_plt_offsets[idx] != (bfd_vma) -1)
+ {
+ local_plt_offsets[idx] = entry;
+ entry += 4;
+ }
+ }
+ }
+
+ return TRUE;
+}
+
+static bfd_boolean
+rl78_elf_relax_section
+ (bfd * abfd,
+ asection * sec,
+ struct bfd_link_info * link_info,
+ bfd_boolean * again)
+{
+ if (abfd == elf_hash_table (link_info)->dynobj
+ && strcmp (sec->name, ".plt") == 0)
+ return rl78_elf_relax_plt_section (abfd, sec, link_info, again);
+
+ /* Assume nothing changes. */
+ *again = FALSE;
+ return TRUE;
+}
+
+
+
+#define ELF_ARCH bfd_arch_rl78
+#define ELF_MACHINE_CODE EM_RL78
+#define ELF_MAXPAGESIZE 0x1000
+
+#define TARGET_LITTLE_SYM bfd_elf32_rl78_vec
+#define TARGET_LITTLE_NAME "elf32-rl78"
+
+#define elf_info_to_howto_rel NULL
+#define elf_info_to_howto rl78_info_to_howto_rela
+#define elf_backend_object_p rl78_elf_object_p
+#define elf_backend_relocate_section rl78_elf_relocate_section
+#define elf_symbol_leading_char ('_')
+#define elf_backend_can_gc_sections 1
+
+#define bfd_elf32_bfd_reloc_type_lookup rl78_reloc_type_lookup
+#define bfd_elf32_bfd_reloc_name_lookup rl78_reloc_name_lookup
+#define bfd_elf32_bfd_set_private_flags rl78_elf_set_private_flags
+#define bfd_elf32_bfd_merge_private_bfd_data rl78_elf_merge_private_bfd_data
+#define bfd_elf32_bfd_print_private_bfd_data rl78_elf_print_private_bfd_data
+
+#define bfd_elf32_bfd_relax_section rl78_elf_relax_section
+#define elf_backend_check_relocs rl78_elf_check_relocs
+#define elf_backend_always_size_sections \
+ rl78_elf_always_size_sections
+#define elf_backend_finish_dynamic_sections \
+ rl78_elf_finish_dynamic_sections
+
+#include "elf32-target.h"
Index: bfd/reloc.c
===================================================================
RCS file: /cvs/src/src/bfd/reloc.c,v
retrieving revision 1.216
diff -p -U5 -r1.216 reloc.c
--- bfd/reloc.c 24 Jul 2011 14:20:06 -0000 1.216
+++ bfd/reloc.c 24 Oct 2011 22:25:17 -0000
@@ -4314,10 +4314,77 @@ ENUM
ENUMDOC
This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
instructions
ENUM
+ BFD_RELOC_RL78_NEG8
+ENUMX
+ BFD_RELOC_RL78_NEG16
+ENUMX
+ BFD_RELOC_RL78_NEG24
+ENUMX
+ BFD_RELOC_RL78_NEG32
+ENUMX
+ BFD_RELOC_RL78_16_OP
+ENUMX
+ BFD_RELOC_RL78_24_OP
+ENUMX
+ BFD_RELOC_RL78_32_OP
+ENUMX
+ BFD_RELOC_RL78_8U
+ENUMX
+ BFD_RELOC_RL78_16U
+ENUMX
+ BFD_RELOC_RL78_24U
+ENUMX
+ BFD_RELOC_RL78_DIR3U_PCREL
+ENUMX
+ BFD_RELOC_RL78_DIFF
+ENUMX
+ BFD_RELOC_RL78_GPRELB
+ENUMX
+ BFD_RELOC_RL78_GPRELW
+ENUMX
+ BFD_RELOC_RL78_GPRELL
+ENUMX
+ BFD_RELOC_RL78_SYM
+ENUMX
+ BFD_RELOC_RL78_OP_SUBTRACT
+ENUMX
+ BFD_RELOC_RL78_OP_NEG
+ENUMX
+ BFD_RELOC_RL78_OP_AND
+ENUMX
+ BFD_RELOC_RL78_OP_SHRA
+ENUMX
+ BFD_RELOC_RL78_ABS8
+ENUMX
+ BFD_RELOC_RL78_ABS16
+ENUMX
+ BFD_RELOC_RL78_ABS16_REV
+ENUMX
+ BFD_RELOC_RL78_ABS32
+ENUMX
+ BFD_RELOC_RL78_ABS32_REV
+ENUMX
+ BFD_RELOC_RL78_ABS16U
+ENUMX
+ BFD_RELOC_RL78_ABS16UW
+ENUMX
+ BFD_RELOC_RL78_ABS16UL
+ENUMX
+ BFD_RELOC_RL78_RELAX
+ENUMX
+ BFD_RELOC_RL78_HI16
+ENUMX
+ BFD_RELOC_RL78_HI8
+ENUMX
+ BFD_RELOC_RL78_LO16
+ENUMDOC
+ Renesas RL78 Relocations.
+
+ENUM
BFD_RELOC_RX_NEG8
ENUMX
BFD_RELOC_RX_NEG16
ENUMX
BFD_RELOC_RX_NEG24
Index: bfd/targets.c
===================================================================
RCS file: /cvs/src/src/bfd/targets.c,v
retrieving revision 1.208
diff -p -U5 -r1.208 targets.c
--- bfd/targets.c 17 Aug 2011 00:39:38 -0000 1.208
+++ bfd/targets.c 24 Oct 2011 22:25:17 -0000
@@ -666,10 +666,11 @@ extern const bfd_target bfd_elf32_or32_b
extern const bfd_target bfd_elf32_pj_vec;
extern const bfd_target bfd_elf32_pjl_vec;
extern const bfd_target bfd_elf32_powerpc_vec;
extern const bfd_target bfd_elf32_powerpcle_vec;
extern const bfd_target bfd_elf32_powerpc_vxworks_vec;
+extern const bfd_target bfd_elf32_rl78_vec;
extern const bfd_target bfd_elf32_rx_le_vec;
extern const bfd_target bfd_elf32_rx_be_vec;
extern const bfd_target bfd_elf32_rx_be_ns_vec;
extern const bfd_target bfd_elf32_s390_vec;
extern const bfd_target bfd_elf32_bigscore_vec;
@@ -1031,10 +1032,11 @@ static const bfd_target * const _bfd_tar
&bfd_elf32_pj_vec,
&bfd_elf32_pjl_vec,
&bfd_elf32_powerpc_vec,
&bfd_elf32_powerpc_vxworks_vec,
&bfd_elf32_powerpcle_vec,
+ &bfd_elf32_rl78_vec,
&bfd_elf32_rx_be_vec,
&bfd_elf32_rx_be_ns_vec,
&bfd_elf32_rx_le_vec,
&bfd_elf32_s390_vec,
#ifdef BFD64
Index: binutils/readelf.c
===================================================================
RCS file: /cvs/src/src/binutils/readelf.c,v
retrieving revision 1.558
diff -p -U5 -r1.558 readelf.c
--- binutils/readelf.c 13 Oct 2011 15:33:32 -0000 1.558
+++ binutils/readelf.c 24 Oct 2011 22:25:18 -0000
@@ -131,10 +131,11 @@
#include "elf/msp430.h"
#include "elf/or32.h"
#include "elf/pj.h"
#include "elf/ppc.h"
#include "elf/ppc64.h"
+#include "elf/rl78.h"
#include "elf/rx.h"
#include "elf/s390.h"
#include "elf/score.h"
#include "elf/sh.h"
#include "elf/sparc.h"
@@ -589,10 +590,11 @@ guess_is_rela (unsigned int e_machine)
case EM_MSP430_OLD:
case EM_MT:
case EM_NIOS32:
case EM_PPC64:
case EM_PPC:
+ case EM_RL78:
case EM_RX:
case EM_S390:
case EM_S390_OLD:
case EM_SH:
case EM_SPARC:
@@ -1211,10 +1213,14 @@ dump_relocations (FILE * file,
case EM_MICROBLAZE:
case EM_MICROBLAZE_OLD:
rtype = elf_microblaze_reloc_type (type);
break;
+ case EM_RL78:
+ rtype = elf_rl78_reloc_type (type);
+ break;
+
case EM_RX:
rtype = elf_rx_reloc_type (type);
break;
case EM_XC16X:
@@ -1969,10 +1975,11 @@ get_machine_name (unsigned e_machine)
case EM_CYGNUS_MEP: return "Toshiba MeP Media Engine";
case EM_CR16:
case EM_CR16_OLD: return "National Semiconductor's CR16";
case EM_MICROBLAZE: return "Xilinx MicroBlaze";
case EM_MICROBLAZE_OLD: return "Xilinx MicroBlaze";
+ case EM_RL78: return "Renesas RL78";
case EM_RX: return "Renesas RX";
case EM_METAG: return "Imagination Technologies META processor architecture";
case EM_MCST_ELBRUS: return "MCST Elbrus general purpose hardware architecture";
case EM_ECOG16: return "Cyan Technology eCOG16 family";
case EM_ETPU: return "Freescale Extended Time Processing Unit";
@@ -9757,10 +9764,12 @@ is_32bit_abs_reloc (unsigned int reloc_t
return reloc_type == 1; /* R_PJ_DATA_DIR32. */
case EM_PPC64:
return reloc_type == 1; /* R_PPC64_ADDR32. */
case EM_PPC:
return reloc_type == 1; /* R_PPC_ADDR32. */
+ case EM_RL78:
+ return reloc_type == 1; /* R_RL78_DIR32. */
case EM_RX:
return reloc_type == 1; /* R_RX_DIR32. */
case EM_S370:
return reloc_type == 1; /* R_I370_ADDR31. */
case EM_S390_OLD:
Index: gas/Makefile.am
===================================================================
RCS file: /cvs/src/src/gas/Makefile.am,v
retrieving revision 1.194
diff -p -U5 -r1.194 Makefile.am
--- gas/Makefile.am 13 Jun 2011 15:18:47 -0000 1.194
+++ gas/Makefile.am 24 Oct 2011 22:25:18 -0000
@@ -148,10 +148,11 @@ TARGET_CPU_CFILES = \
config/tc-openrisc.c \
config/tc-or32.c \
config/tc-pdp11.c \
config/tc-pj.c \
config/tc-ppc.c \
+ config/tc-rl78.c \
config/tc-rx.c \
config/tc-s390.c \
config/tc-score.c \
config/tc-sh.c \
config/tc-sh64.c \
@@ -213,10 +214,11 @@ TARGET_CPU_HFILES = \
config/tc-openrisc.h \
config/tc-or32.h \
config/tc-pdp11.h \
config/tc-pj.h \
config/tc-ppc.h \
+ config/tc-rl78.h \
config/tc-rx.h \
config/tc-s390.h \
config/tc-score.h \
config/tc-sh.h \
config/tc-sh64.h \
@@ -332,10 +334,11 @@ noinst_PROGRAMS = as-new
noinst_SCRIPTS = $(GDBINIT)
EXTRA_SCRIPTS = .gdbinit
EXTRA_DIST = m68k-parse.c itbl-parse.c itbl-parse.h itbl-lex.c \
bfin-parse.c bfin-parse.h bfin-lex.c \
+ rl78-parse.c rl78-parse.h \
rx-parse.c rx-parse.h
diststuff: $(EXTRA_DIST) info
DISTCLEANFILES = targ-cpu.h obj-format.h targ-env.h itbl-cpu.h cgen-desc.h
@@ -461,10 +464,18 @@ if AMDEP
DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
endif
$(COMPILE) -c `test -f bfin-lex.c || echo $(srcdir)/`bfin-lex.c $(NO_WERROR)
endif
+rl78-parse.c: $(srcdir)/config/rl78-parse.y
+ $(SHELL) $(YLWRAP) $(srcdir)/config/rl78-parse.y y.tab.c rl78-parse.c y.tab.h rl78-parse.h -- $(YACCCOMPILE) -d ;
+rl78-parse.h: rl78-parse.c
+rl78-parse.@OBJEXT@: rl78-parse.c rl78-parse.h $(srcdir)/config/rl78-defs.h \
+ $(INCDIR)/elf/common.h $(INCDIR)/elf/rl78.h $(BFDDIR)/libbfd.h
+
+rl78-defs.h: ; @true
+
rx-parse.c: $(srcdir)/config/rx-parse.y
$(SHELL) $(YLWRAP) $(srcdir)/config/rx-parse.y y.tab.c rx-parse.c y.tab.h rx-parse.h -- $(YACCCOMPILE) -d ;
rx-parse.h: rx-parse.c
rx-parse.@OBJEXT@: rx-parse.c rx-parse.h $(srcdir)/config/rx-defs.h \
$(INCDIR)/elf/common.h $(INCDIR)/elf/rx.h $(BFDDIR)/libbfd.h
Index: gas/configure.in
===================================================================
RCS file: /cvs/src/src/gas/configure.in,v
retrieving revision 1.223
diff -p -U5 -r1.223 configure.in
--- gas/configure.in 18 May 2011 09:41:14 -0000 1.223
+++ gas/configure.in 24 Oct 2011 22:25:21 -0000
@@ -351,10 +351,17 @@ changequote([,])dnl
if test $this_target = $target ; then
AC_DEFINE_UNQUOTED(DEFAULT_ARCH, "${arch}", [Default architecture.])
fi
;;
+ rl78)
+ echo ${extra_objects} | grep -s "rl78-parse.o"
+ if test $? -ne 0 ; then
+ extra_objects="$extra_objects rl78-parse.o"
+ fi
+ ;;
+
rx)
echo ${extra_objects} | grep -s "rx-parse.o"
if test $? -ne 0 ; then
extra_objects="$extra_objects rx-parse.o"
fi
Index: gas/configure.tgt
===================================================================
RCS file: /cvs/src/src/gas/configure.tgt,v
retrieving revision 1.70
diff -p -U5 -r1.70 configure.tgt
--- gas/configure.tgt 20 Jun 2011 13:23:21 -0000 1.70
+++ gas/configure.tgt 24 Oct 2011 22:25:21 -0000
@@ -62,10 +62,11 @@ case ${cpu} in
pjl*) cpu_type=pj endian=little ;;
pj*) cpu_type=pj endian=big ;;
powerpc*le*) cpu_type=ppc endian=little ;;
powerpc*) cpu_type=ppc endian=big ;;
rs6000*) cpu_type=ppc ;;
+ rl78*) cpu_type=rl78 ;;
rx) cpu_type=rx ;;
s390x*) cpu_type=s390 arch=s390x ;;
s390*) cpu_type=s390 arch=s390 ;;
score*l) cpu_type=score endian=little ;;
score*) cpu_type=score endian=big ;;
Index: gas/config/rl78-defs.h
===================================================================
RCS file: gas/config/rl78-defs.h
diff -N gas/config/rl78-defs.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/config/rl78-defs.h 24 Oct 2011 22:25:21 -0000
@@ -0,0 +1,51 @@
+/* rl78-defs.h Renesas RL78 internal definitions
+ Copyright 2008, 2009
+ Free Software Foundation, Inc.
+
+ This file is part of GAS, the GNU Assembler.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GAS; see the file COPYING. If not, write to the Free
+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+ 02110-1301, USA. */
+
+#ifndef RL78_DEFS_H
+#define RL78_DEFS_H
+
+/* Third operand to rl78_op. */
+#define RL78REL_DATA 0
+#define RL78REL_PCREL 1
+
+extern int rl78_error (char *);
+extern void rl78_lex_init (char *, char *);
+extern void rl78_prefix (int);
+extern int rl78_has_prefix (void);
+extern void rl78_base1 (int);
+extern void rl78_base2 (int, int);
+extern void rl78_base3 (int, int, int);
+extern void rl78_base4 (int, int, int, int);
+extern void rl78_field (int, int, int);
+extern void rl78_op (expressionS, int, int);
+extern void rl78_disp3 (expressionS, int);
+extern void rl78_field5s (expressionS);
+extern void rl78_field5s2 (expressionS);
+extern void rl78_relax (int, int);
+extern void rl78_linkrelax_dsp (int);
+extern void rl78_linkrelax_imm (int);
+extern void rl78_linkrelax_branch (void);
+extern int rl78_parse (void);
+extern int rl78_wrap (void);
+
+extern char * rl78_lex_start;
+extern char * rl78_lex_end;
+#endif
Index: gas/config/rl78-parse.y
===================================================================
RCS file: gas/config/rl78-parse.y
diff -N gas/config/rl78-parse.y
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/config/rl78-parse.y 24 Oct 2011 22:25:21 -0000
@@ -0,0 +1,1532 @@
+/* rl78-parse.y Renesas RL78 parser
+ Copyright 2011
+ Free Software Foundation, Inc.
+
+ This file is part of GAS, the GNU Assembler.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GAS; see the file COPYING. If not, write to the Free
+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+ 02110-1301, USA. */
+%{
+
+#include "as.h"
+#include "safe-ctype.h"
+#include "rl78-defs.h"
+
+static int rl78_lex (void);
+
+/* Ok, here are the rules for using these macros...
+
+ B*() is used to specify the base opcode bytes. Fields to be filled
+ in later, leave zero. Call this first.
+
+ F() and FE() are used to fill in fields within the base opcode bytes. You MUST
+ call B*() before any F() or FE().
+
+ [UN]*O*(), PC*() appends operands to the end of the opcode. You
+ must call P() and B*() before any of these, so that the fixups
+ have the right byte location.
+ O = signed, UO = unsigned, NO = negated, PC = pcrel
+
+ IMM() adds an immediate and fills in the field for it.
+ NIMM() same, but negates the immediate.
+ NBIMM() same, but negates the immediate, for sbb.
+ DSP() adds a displacement, and fills in the field for it.
+
+ Note that order is significant for the O, IMM, and DSP macros, as
+ they append their data to the operand buffer in the order that you
+ call them.
+
+ Use "disp" for displacements whenever possible; this handles the
+ "0" case properly. */
+
+#define B1(b1) rl78_base1 (b1)
+#define B2(b1, b2) rl78_base2 (b1, b2)
+#define B3(b1, b2, b3) rl78_base3 (b1, b2, b3)
+#define B4(b1, b2, b3, b4) rl78_base4 (b1, b2, b3, b4)
+
+/* POS is bits from the MSB of the first byte to the LSB of the last byte. */
+#define F(val,pos,sz) rl78_field (val, pos, sz)
+#define FE(exp,pos,sz) rl78_field (exp_val (exp), pos, sz);
+
+#define O1(v) rl78_op (v, 1, RL78REL_DATA)
+#define O2(v) rl78_op (v, 2, RL78REL_DATA)
+#define O3(v) rl78_op (v, 3, RL78REL_DATA)
+#define O4(v) rl78_op (v, 4, RL78REL_DATA)
+
+#define PC1(v) rl78_op (v, 1, RL78REL_PCREL)
+#define PC2(v) rl78_op (v, 2, RL78REL_PCREL)
+#define PC3(v) rl78_op (v, 3, RL78REL_PCREL)
+
+#define IMM(v,pos) F (immediate (v, RL78REL_SIGNED, pos), pos, 2); \
+ if (v.X_op != O_constant && v.X_op != O_big) rl78_linkrelax_imm (pos)
+#define NIMM(v,pos) F (immediate (v, RL78REL_NEGATIVE, pos), pos, 2)
+#define NBIMM(v,pos) F (immediate (v, RL78REL_NEGATIVE_BORROW, pos), pos, 2)
+#define DSP(v,pos,msz) if (!v.X_md) rl78_relax (RL78_RELAX_DISP, pos); \
+ else rl78_linkrelax_dsp (pos); \
+ F (displacement (v, msz), pos, 2)
+
+#define id24(a,b2,b3) B3 (0xfb+a, b2, b3)
+
+static int expr_is_sfr (expressionS);
+static int expr_is_saddr (expressionS);
+static int expr_is_word_aligned (expressionS);
+static int exp_val (expressionS exp);
+
+static int need_flag = 0;
+static int rl78_in_brackets = 0;
+static int rl78_last_token = 0;
+static char * rl78_init_start;
+static char * rl78_last_exp_start = 0;
+
+#define YYDEBUG 1
+#define YYERROR_VERBOSE 1
+
+#define NOT_SADDR rl78_error ("Expression not 0xFFE20 to 0xFFF1F")
+#define SA(e) if (!expr_is_saddr (e)) NOT_SADDR;
+
+#define NOT_SFR rl78_error ("Expression not 0xFFF00 to 0xFFFFF")
+#define SFR(e) if (!expr_is_sfr (e)) NOT_SFR;
+
+#define NOT_SFR_OR_SADDR rl78_error ("Expression not 0xFFE20 to 0xFFFFF")
+
+#define NOT_ES if (rl78_has_prefix()) rl78_error ("ES: prefix not allowed here");
+
+#define WA(x) if (!expr_is_word_aligned (x)) rl78_error ("Expression not word-aligned");
+
+static void check_expr_is_bit_index (expressionS);
+#define Bit(e) check_expr_is_bit_index (e);
+
+/* Returns TRUE (non-zero) if the expression is a constant in the
+ given range. */
+static int check_expr_is_const (expressionS, int vmin, int vmax);
+
+/* Convert a "regb" value to a "reg_xbc" value. Error if other
+ registers are passed. Needed to avoid reduce-reduce conflicts. */
+static int
+reg_xbc (int reg)
+{
+ switch (reg)
+ {
+ case 0: /* X */
+ return 0x10;
+ case 3: /* B */
+ return 0x20;
+ case 2: /* C */
+ return 0x30;
+ default:
+ rl78_error ("Only X, B, or C allowed here");
+ return 0;
+ }
+}
+
+%}
+
+%name-prefix="rl78_"
+
+%union {
+ int regno;
+ expressionS exp;
+}
+
+%type <regno> regb regb_na regw regw_na FLAG sfr
+%type <regno> A X B C D E H L AX BC DE HL
+%type <exp> EXPR
+
+%type <regno> addsub addsubw andor1 bt_bf setclr1 oneclrb oneclrw
+%type <regno> incdec incdecw
+
+%token A X B C D E H L AX BC DE HL
+%token SPL SPH PSW CS ES PMC MEM
+%token FLAG SP CY
+%token RB0 RB1 RB2 RB3
+
+%token EXPR UNKNOWN_OPCODE IS_OPCODE
+
+%token DOT_S DOT_B DOT_W DOT_L DOT_A DOT_UB DOT_UW
+
+%token ADD ADDC ADDW AND_ AND1
+/* BC is also a register pair */
+%token BF BH BNC BNH BNZ BR BRK BRK1 BT BTCLR BZ
+%token CALL CALLT CLR1 CLRB CLRW CMP CMP0 CMPS CMPW
+%token DEC DECW DI DIVHU DIVWU
+%token EI
+%token HALT
+%token INC INCW
+%token MACH MACHU MOV MOV1 MOVS MOVW MULH MULHU MULU
+%token NOP
+%token ONEB ONEW OR OR1
+%token POP PUSH
+%token RET RETI RETB ROL ROLC ROLWC ROR RORC
+%token SAR SARW SEL SET1 SHL SHLW SHR SHRW
+%token SKC SKH SKNC SKNH SKNZ SKZ STOP SUB SUBC SUBW
+%token XCH XCHW XOR XOR1
+
+%%
+/* ====================================================================== */
+
+statement :
+
+ UNKNOWN_OPCODE
+ { as_bad (_("Unknown opcode: %s"), rl78_init_start); }
+
+/* The opcodes are listed in approximately alphabetical order. */
+
+/* For reference:
+
+ sfr = special function register - symbol, 0xFFF00 to 0xFFFFF
+ sfrp = special function register - symbol, 0xFFF00 to 0xFFFFE, even only
+ saddr = 0xFFE20 to 0xFFF1F
+ saddrp = 0xFFE20 to 0xFFF1E, even only
+
+ addr20 = 0x00000 to 0xFFFFF
+ addr16 = 0x00000 to 0x0FFFF, even only for 16-bit ops
+ addr5 = 0x00000 to 0x000BE, even only
+*/
+
+/* ---------------------------------------------------------------------- */
+
+/* addsub is ADD, ADDC, SUB, SUBC, AND, OR, XOR, and parts of CMP. */
+
+ | addsub A ',' '#' EXPR
+ { B1 (0x0c|$1); O1 ($5); }
+
+ | addsub EXPR {SA($2)} ',' '#' EXPR
+ { B1 (0x0a|$1); O1 ($2); O1 ($6); }
+
+ | addsub A ',' A
+ { B2 (0x61, 0x01|$1); }
+
+ | addsub A ',' regb_na
+ { B2 (0x61, 0x08|$1); F ($4, 13, 3); }
+
+ | addsub regb_na ',' A
+ { B2 (0x61, 0x00|$1); F ($2, 13, 3); }
+
+ | addsub A ',' EXPR {SA($4)}
+ { B1 (0x0b|$1); O1 ($4); }
+
+ | addsub A ',' opt_es '!' EXPR
+ { B1 (0x0f|$1); O2 ($6); }
+
+ | addsub A ',' opt_es '[' HL ']'
+ { B1 (0x0d|$1); }
+
+ | addsub A ',' opt_es '[' HL '+' EXPR ']'
+ { B1 (0x0e|$1); O1 ($8); }
+
+ | addsub A ',' opt_es '[' HL '+' B ']'
+ { B2 (0x61, 0x80|$1); }
+
+ | addsub A ',' opt_es '[' HL '+' C ']'
+ { B2 (0x61, 0x82|$1); }
+
+
+
+ | addsub opt_es '!' EXPR ',' '#' EXPR
+ { if ($1 != 0x40)
+ { rl78_error ("Only CMP takes these operands"); }
+ else
+ { B1 (0x00|$1); O2 ($4); O1 ($7); }
+ }
+
+/* ---------------------------------------------------------------------- */
+
+ | addsubw AX ',' '#' EXPR
+ { B1 (0x04|$1); O2 ($5); }
+
+ | addsubw AX ',' regw
+ { B1 (0x01|$1); F ($4, 5, 2); }
+
+ | addsubw AX ',' EXPR {SA($4)}
+ { B1 (0x06|$1); O1 ($4); }
+
+ | addsubw AX ',' opt_es '!' EXPR
+ { B1 (0x02|$1); O2 ($6); }
+
+ | addsubw AX ',' opt_es '[' HL '+' EXPR ']'
+ { B2 (0x61, 0x09|$1); O1 ($8); }
+
+ | addsubw AX ',' opt_es '[' HL ']'
+ { B4 (0x61, 0x09|$1, 0, 0); }
+
+ | addsubw SP ',' '#' EXPR
+ { B1 ($1 ? 0x20 : 0x10); O1 ($5);
+ if ($1 == 0x40)
+ rl78_error ("CMPW SP,#imm not allowed");
+ }
+
+/* ---------------------------------------------------------------------- */
+
+ | andor1 CY ',' sfr '.' EXPR {Bit($6)}
+ { B3 (0x71, 0x08|$1, $4); FE ($6, 9, 3); }
+
+ | andor1 CY ',' EXPR '.' EXPR {Bit($6)}
+ { if (expr_is_sfr ($4))
+ { B2 (0x71, 0x08|$1); FE ($6, 9, 3); O1 ($4); }
+ else if (expr_is_saddr ($4))
+ { B2 (0x71, 0x00|$1); FE ($6, 9, 3); O1 ($4); }
+ else
+ NOT_SFR_OR_SADDR;
+ }
+
+ | andor1 CY ',' A '.' EXPR {Bit($6)}
+ { B2 (0x71, 0x88|$1); FE ($6, 9, 3); }
+
+ | andor1 CY ',' opt_es '[' HL ']' '.' EXPR {Bit($9)}
+ { B2 (0x71, 0x80|$1); FE ($9, 9, 3); }
+
+/* ---------------------------------------------------------------------- */
+
+ | BC '$' EXPR
+ { B1 (0xdc); PC1 ($3); }
+
+ | BNC '$' EXPR
+ { B1 (0xde); PC1 ($3); }
+
+ | BZ '$' EXPR
+ { B1 (0xdd); PC1 ($3); }
+
+ | BNZ '$' EXPR
+ { B1 (0xdf); PC1 ($3); }
+
+ | BH '$' EXPR
+ { B2 (0x61, 0xc3); PC1 ($3); }
+
+ | BNH '$' EXPR
+ { B2 (0x61, 0xd3); PC1 ($3); }
+
+/* ---------------------------------------------------------------------- */
+
+ | bt_bf sfr '.' EXPR ',' '$' EXPR
+ { B3 (0x31, 0x80|$1, $2); FE ($4, 9, 3); PC1 ($7); }
+
+ | bt_bf EXPR '.' EXPR ',' '$' EXPR
+ { if (expr_is_sfr ($2))
+ { B2 (0x31, 0x80|$1); FE ($4, 9, 3); O1 ($2); PC1 ($7); }
+ else if (expr_is_saddr ($2))
+ { B2 (0x31, 0x00|$1); FE ($4, 9, 3); O1 ($2); PC1 ($7); }
+ else
+ NOT_SFR_OR_SADDR;
+ }
+
+ | bt_bf A '.' EXPR ',' '$' EXPR
+ { B2 (0x31, 0x01|$1); FE ($4, 9, 3); PC1 ($7); }
+
+ | bt_bf opt_es '[' HL ']' '.' EXPR ',' '$' EXPR
+ { B2 (0x31, 0x81|$1); FE ($7, 9, 3); PC1 ($10); }
+
+/* ---------------------------------------------------------------------- */
+
+ | BR AX
+ { B2 (0x61, 0xcb); }
+
+ | BR '$' EXPR
+ { B1 (0xef); PC1 ($3); }
+
+ | BR '$' '!' EXPR
+ { B1 (0xee); PC2 ($4); }
+
+ | BR '!' EXPR
+ { B1 (0xed); O2 ($3); }
+
+ | BR '!' '!' EXPR
+ { B1 (0xec); O3 ($4); }
+
+/* ---------------------------------------------------------------------- */
+
+ | BRK
+ { B2 (0x61, 0xcc); }
+
+ | BRK1
+ { B1 (0xff); }
+
+/* ---------------------------------------------------------------------- */
+
+ | CALL regw
+ { B2 (0x61, 0xca); F ($2, 10, 2); }
+
+ | CALL '$' '!' EXPR
+ { B1 (0xfe); PC2 ($4); }
+
+ | CALL '!' EXPR
+ { B1 (0xfd); O2 ($3); }
+
+ | CALL '!' '!' EXPR
+ { B1 (0xfc); O3 ($4); }
+
+ | CALLT '[' EXPR ']'
+ { if ($3.X_op != O_constant)
+ rl78_error ("CALLT requires a numeric address");
+ else
+ {
+ int i = $3.X_add_number;
+ if (i < 0x80 || i > 0xbe)
+ rl78_error ("CALLT address not 0x80..0xbe");
+ else if (i & 1)
+ rl78_error ("CALLT address not even");
+ else
+ {
+ B2 (0x61, 0x84);
+ F ((i >> 1) & 7, 9, 3);
+ F ((i >> 4) & 7, 14, 2);
+ }
+ }
+ }
+
+/* ---------------------------------------------------------------------- */
+
+ | setclr1 CY
+ { B2 (0x71, $1 ? 0x88 : 0x80); }
+
+ | setclr1 sfr '.' EXPR
+ { B3 (0x71, 0x0a|$1, $2); FE ($4, 9, 3); }
+
+ | setclr1 EXPR '.' EXPR
+ { if (expr_is_sfr ($2))
+ { B2 (0x71, 0x0a|$1); FE ($4, 9, 3); O1 ($2); }
+ else if (expr_is_saddr ($2))
+ { B2 (0x71, 0x02|$1); FE ($4, 9, 3); O1 ($2); }
+ else
+ NOT_SFR_OR_SADDR;
+ }
+
+ | setclr1 A '.' EXPR
+ { B2 (0x71, 0x8a|$1); FE ($4, 9, 3); }
+
+ | setclr1 opt_es '!' EXPR '.' EXPR
+ { B2 (0x71, 0x00+$1*0x08); FE ($6, 9, 3); O2 ($4); }
+
+ | setclr1 opt_es '[' HL ']' '.' EXPR
+ { B2 (0x71, 0x82|$1); FE ($7, 9, 3); }
+
+/* ---------------------------------------------------------------------- */
+
+ | oneclrb A
+ { B1 (0xe1|$1); }
+ | oneclrb X
+ { B1 (0xe0|$1); }
+ | oneclrb B
+ { B1 (0xe3|$1); }
+ | oneclrb C
+ { B1 (0xe2|$1); }
+
+ | oneclrb EXPR {SA($2)}
+ { B1 (0xe4|$1); O1 ($2); }
+
+ | oneclrb opt_es '!' EXPR
+ { B1 (0xe5|$1); O2 ($4); }
+
+/* ---------------------------------------------------------------------- */
+
+ | oneclrw AX
+ { B1 (0xe6|$1); }
+ | oneclrw BC
+ { B1 (0xe7|$1); }
+
+/* ---------------------------------------------------------------------- */
+
+ | CMP0 A
+ { B1 (0xd1); }
+
+ | CMP0 X
+ { B1 (0xd0); }
+
+ | CMP0 B
+ { B1 (0xd3); }
+
+ | CMP0 C
+ { B1 (0xd2); }
+
+ | CMP0 EXPR {SA($2)}
+ { B1 (0xd4); O1 ($2); }
+
+ | CMP0 opt_es '!' EXPR
+ { B1 (0xd5); O2 ($4); }
+
+/* ---------------------------------------------------------------------- */
+
+ | CMPS X ',' opt_es '[' HL '+' EXPR ']'
+ { B2 (0x61, 0xde); O1 ($8); }
+
+/* ---------------------------------------------------------------------- */
+
+ | incdec regb
+ { B1 (0x80|$1); F ($2, 5, 3); }
+
+ | incdec EXPR {SA($2)}
+ { B1 (0xa4|$1); O1 ($2); }
+ | incdec '!' EXPR
+ { B1 (0xa0|$1); O2 ($3); }
+ | incdec ES ':' '!' EXPR
+ { B2 (0x11, 0xa0|$1); O2 ($5); }
+ | incdec '[' HL '+' EXPR ']'
+ { B2 (0x61, 0x59+$1); O1 ($5); }
+ | incdec ES ':' '[' HL '+' EXPR ']'
+ { B3 (0x11, 0x61, 0x59+$1); O1 ($7); }
+
+/* ---------------------------------------------------------------------- */
+
+ | incdecw regw
+ { B1 (0xa1|$1); F ($2, 5, 2); }
+
+ | incdecw EXPR {SA($2)}
+ { B1 (0xa6|$1); O1 ($2); }
+
+ | incdecw opt_es '!' EXPR
+ { B1 (0xa2|$1); O2 ($4); }
+
+ | incdecw opt_es '[' HL '+' EXPR ']'
+ { B2 (0x61, 0x79+$1); O1 ($6); }
+
+/* ---------------------------------------------------------------------- */
+
+ | DI
+ { B3 (0x71, 0x7b, 0xfa); }
+
+ | EI
+ { B3 (0x71, 0x7a, 0xfa); }
+
+/* ---------------------------------------------------------------------- */
+
+ | MULHU
+ { B3 (0xce, 0xfb, 0x01); }
+
+ | MULH
+ { B3 (0xce, 0xfb, 0x02); }
+
+ | MULU X
+ { B1 (0xd6); }
+
+ | DIVHU
+ { B3 (0xce, 0xfb, 0x03); }
+
+ | DIVWU
+ { B3 (0xce, 0xfb, 0x04); }
+
+ | MACHU
+ { B3 (0xce, 0xfb, 0x05); }
+
+ | MACH
+ { B3 (0xce, 0xfb, 0x06); }
+
+/* ---------------------------------------------------------------------- */
+
+ | HALT
+ { B2 (0x61, 0xed); }
+
+/* ---------------------------------------------------------------------- */
+/* Note that opt_es is included even when it's not an option, to avoid
+ shift/reduce conflicts. The NOT_ES macro produces an error if ES:
+ is given by the user. */
+
+ | MOV A ',' '#' EXPR
+ { B1 (0x51); O1 ($5); }
+ | MOV regb_na ',' '#' EXPR
+ { B1 (0x50); F($2, 5, 3); O1 ($5); }
+
+ | MOV sfr ',' '#' EXPR
+ { if ($2 != 0xfd)
+ { B2 (0xce, $2); O1 ($5); }
+ else
+ { B1 (0x41); O1 ($5); }
+ }
+
+ | MOV opt_es EXPR ',' '#' EXPR {NOT_ES}
+ { if (expr_is_sfr ($3))
+ { B1 (0xce); O1 ($3); O1 ($6); }
+ else if (expr_is_saddr ($3))
+ { B1 (0xcd); O1 ($3); O1 ($6); }
+ else
+ NOT_SFR_OR_SADDR;
+ }
+
+ | MOV '!' EXPR ',' '#' EXPR
+ { B1 (0xcf); O2 ($3); O1 ($6); }
+
+ | MOV ES ':' '!' EXPR ',' '#' EXPR
+ { B2 (0x11, 0xcf); O2 ($5); O1 ($8); }
+
+ | MOV regb_na ',' A
+ { B1 (0x70); F ($2, 5, 3); }
+
+ | MOV A ',' regb_na
+ { B1 (0x60); F ($4, 5, 3); }
+
+ | MOV opt_es EXPR ',' A {NOT_ES}
+ { if (expr_is_sfr ($3))
+ { B1 (0x9e); O1 ($3); }
+ else if (expr_is_saddr ($3))
+ { B1 (0x9d); O1 ($3); }
+ else
+ NOT_SFR_OR_SADDR;
+ }
+
+ | MOV A ',' opt_es '!' EXPR
+ { B1 (0x8f); O2 ($6); }
+
+ | MOV '!' EXPR ',' A
+ { B1 (0x9f); O2 ($3); }
+
+ | MOV ES ':' '!' EXPR ',' A
+ { B2 (0x11, 0x9f); O2 ($5); }
+
+ | MOV regb_na ',' opt_es '!' EXPR
+ { B1 (0xc9|reg_xbc($2)); O2 ($6); }
+
+ | MOV A ',' opt_es EXPR {NOT_ES}
+ { if (expr_is_saddr ($5))
+ { B1 (0x8d); O1 ($5); }
+ else if (expr_is_sfr ($5))
+ { B1 (0x8e); O1 ($5); }
+ else
+ NOT_SFR_OR_SADDR;
+ }
+
+ | MOV regb_na ',' opt_es EXPR {SA($5)} {NOT_ES}
+ { B1 (0xc8|reg_xbc($2)); O1 ($5); }
+
+ | MOV A ',' sfr
+ { B2 (0x8e, $4); }
+
+ | MOV sfr ',' regb
+ { if ($4 != 1)
+ rl78_error ("Only A allowed here");
+ else
+ { B2 (0x9e, $2); }
+ }
+
+ | MOV sfr ',' opt_es EXPR {SA($5)} {NOT_ES}
+ { if ($2 != 0xfd)
+ rl78_error ("Only ES allowed here");
+ else
+ { B2 (0x61, 0xb8); O1 ($5); }
+ }
+
+ | MOV A ',' opt_es '[' DE ']'
+ { B1 (0x89); }
+
+ | MOV opt_es '[' DE ']' ',' A
+ { B1 (0x99); }
+
+ | MOV opt_es '[' DE '+' EXPR ']' ',' '#' EXPR
+ { B1 (0xca); O1 ($6); O1 ($10); }
+
+ | MOV A ',' opt_es '[' DE '+' EXPR ']'
+ { B1 (0x8a); O1 ($8); }
+
+ | MOV opt_es '[' DE '+' EXPR ']' ',' A
+ { B1 (0x9a); O1 ($6); }
+
+ | MOV A ',' opt_es '[' HL ']'
+ { B1 (0x8b); }
+
+ | MOV opt_es '[' HL ']' ',' A
+ { B1 (0x9b); }
+
+ | MOV opt_es '[' HL '+' EXPR ']' ',' '#' EXPR
+ { B1 (0xcc); O1 ($6); O1 ($10); }
+
+ | MOV A ',' opt_es '[' HL '+' EXPR ']'
+ { B1 (0x8c); O1 ($8); }
+
+ | MOV opt_es '[' HL '+' EXPR ']' ',' A
+ { B1 (0x9c); O1 ($6); }
+
+ | MOV A ',' opt_es '[' HL '+' B ']'
+ { B2 (0x61, 0xc9); }
+
+ | MOV opt_es '[' HL '+' B ']' ',' A
+ { B2 (0x61, 0xd9); }
+
+ | MOV A ',' opt_es '[' HL '+' C ']'
+ { B2 (0x61, 0xe9); }
+
+ | MOV opt_es '[' HL '+' C ']' ',' A
+ { B2 (0x61, 0xf9); }
+
+ | MOV opt_es EXPR '[' B ']' ',' '#' EXPR
+ { B1 (0x19); O2 ($3); O1 ($9); }
+
+ | MOV A ',' opt_es EXPR '[' B ']'
+ { B1 (0x09); O2 ($5); }
+
+ | MOV opt_es EXPR '[' B ']' ',' A
+ { B1 (0x18); O2 ($3); }
+
+ | MOV opt_es EXPR '[' C ']' ',' '#' EXPR
+ { B1 (0x38); O2 ($3); O1 ($9); }
+
+ | MOV A ',' opt_es EXPR '[' C ']'
+ { B1 (0x29); O2 ($5); }
+
+ | MOV opt_es EXPR '[' C ']' ',' A
+ { B1 (0x28); O2 ($3); }
+
+ | MOV opt_es EXPR '[' BC ']' ',' '#' EXPR
+ { B1 (0x39); O2 ($3); O1 ($9); }
+
+ | MOV opt_es '[' BC ']' ',' '#' EXPR
+ { B3 (0x39, 0, 0); O1 ($8); }
+
+ | MOV A ',' opt_es EXPR '[' BC ']'
+ { B1 (0x49); O2 ($5); }
+
+ | MOV A ',' opt_es '[' BC ']'
+ { B3 (0x49, 0, 0); }
+
+ | MOV opt_es EXPR '[' BC ']' ',' A
+ { B1 (0x48); O2 ($3); }
+
+ | MOV opt_es '[' BC ']' ',' A
+ { B3 (0x48, 0, 0); }
+
+ | MOV opt_es '[' SP '+' EXPR ']' ',' '#' EXPR {NOT_ES}
+ { B1 (0xc8); O1 ($6); O1 ($10); }
+
+ | MOV opt_es '[' SP ']' ',' '#' EXPR {NOT_ES}
+ { B2 (0xc8, 0); O1 ($8); }
+
+ | MOV A ',' opt_es '[' SP '+' EXPR ']' {NOT_ES}
+ { B1 (0x88); O1 ($8); }
+
+ | MOV A ',' opt_es '[' SP ']' {NOT_ES}
+ { B2 (0x88, 0); }
+
+ | MOV opt_es '[' SP '+' EXPR ']' ',' A {NOT_ES}
+ { B1 (0x98); O1 ($6); }
+
+ | MOV opt_es '[' SP ']' ',' A {NOT_ES}
+ { B2 (0x98, 0); }
+
+/* ---------------------------------------------------------------------- */
+
+ | MOV1 CY ',' EXPR '.' EXPR
+ { if (expr_is_saddr ($4))
+ { B2 (0x71, 0x04); FE ($6, 9, 3); O1 ($4); }
+ else if (expr_is_sfr ($4))
+ { B2 (0x71, 0x0c); FE ($6, 9, 3); O1 ($4); }
+ else
+ NOT_SFR_OR_SADDR;
+ }
+
+ | MOV1 CY ',' A '.' EXPR
+ { B2 (0x71, 0x8c); FE ($6, 9, 3); }
+
+ | MOV1 CY ',' sfr '.' EXPR
+ { B3 (0x71, 0x0c, $4); FE ($6, 9, 3); }
+
+ | MOV1 CY ',' opt_es '[' HL ']' '.' EXPR
+ { B2 (0x71, 0x84); FE ($9, 9, 3); }
+
+ | MOV1 EXPR '.' EXPR ',' CY
+ { if (expr_is_saddr ($2))
+ { B2 (0x71, 0x01); FE ($4, 9, 3); O1 ($2); }
+ else if (expr_is_sfr ($2))
+ { B2 (0x71, 0x09); FE ($4, 9, 3); O1 ($2); }
+ else
+ NOT_SFR_OR_SADDR;
+ }
+
+ | MOV1 A '.' EXPR ',' CY
+ { B2 (0x71, 0x89); FE ($4, 9, 3); }
+
+ | MOV1 sfr '.' EXPR ',' CY
+ { B3 (0x71, 0x09, $2); FE ($4, 9, 3); }
+
+ | MOV1 opt_es '[' HL ']' '.' EXPR ',' CY
+ { B2 (0x71, 0x81); FE ($7, 9, 3); }
+
+/* ---------------------------------------------------------------------- */
+
+ | MOVS opt_es '[' HL '+' EXPR ']' ',' X
+ { B2 (0x61, 0xce); O1 ($6); }
+
+/* ---------------------------------------------------------------------- */
+
+ | MOVW AX ',' '#' EXPR
+ { B1 (0x30); O2 ($5); }
+
+ | MOVW regw_na ',' '#' EXPR
+ { B1 (0x30); F ($2, 5, 2); O2 ($5); }
+
+ | MOVW opt_es EXPR ',' '#' EXPR {NOT_ES}
+ { if (expr_is_saddr ($3))
+ { B1 (0xc9); O1 ($3); O2 ($6); }
+ else if (expr_is_sfr ($3))
+ { B1 (0xcb); O1 ($3); O2 ($6); }
+ else
+ NOT_SFR_OR_SADDR;
+ }
+
+ | MOVW AX ',' opt_es EXPR {NOT_ES}
+ { if (expr_is_saddr ($5))
+ { B1 (0xad); O1 ($5); WA($5); }
+ else if (expr_is_sfr ($5))
+ { B1 (0xae); O1 ($5); WA($5); }
+ else
+ NOT_SFR_OR_SADDR;
+ }
+
+ | MOVW opt_es EXPR ',' AX {NOT_ES}
+ { if (expr_is_saddr ($3))
+ { B1 (0xbd); O1 ($3); WA($3); }
+ else if (expr_is_sfr ($3))
+ { B1 (0xbe); O1 ($3); WA($3); }
+ else
+ NOT_SFR_OR_SADDR;
+ }
+
+ | MOVW AX ',' regw_na
+ { B1 (0x11); F ($4, 5, 2); }
+
+ | MOVW regw_na ',' AX
+ { B1 (0x10); F ($2, 5, 2); }
+
+ | MOVW AX ',' opt_es '!' EXPR
+ { B1 (0xaf); O2 ($6); WA($6); }
+
+ | MOVW opt_es '!' EXPR ',' AX
+ { B1 (0xbf); O2 ($4); WA($4); }
+
+ | MOVW AX ',' opt_es '[' DE ']'
+ { B1 (0xa9); }
+
+ | MOVW opt_es '[' DE ']' ',' AX
+ { B1 (0xb9); }
+
+ | MOVW AX ',' opt_es '[' DE '+' EXPR ']'
+ { B1 (0xaa); O1 ($8); }
+
+ | MOVW opt_es '[' DE '+' EXPR ']' ',' AX
+ { B1 (0xba); O1 ($6); }
+
+ | MOVW AX ',' opt_es '[' HL ']'
+ { B1 (0xab); }
+
+ | MOVW opt_es '[' HL ']' ',' AX
+ { B1 (0xbb); }
+
+ | MOVW AX ',' opt_es '[' HL '+' EXPR ']'
+ { B1 (0xac); O1 ($8); }
+
+ | MOVW opt_es '[' HL '+' EXPR ']' ',' AX
+ { B1 (0xbc); O1 ($6); }
+
+ | MOVW AX ',' opt_es EXPR '[' B ']'
+ { B1 (0x59); O2 ($5); }
+
+ | MOVW opt_es EXPR '[' B ']' ',' AX
+ { B1 (0x58); O2 ($3); }
+
+ | MOVW AX ',' opt_es EXPR '[' C ']'
+ { B1 (0x69); O2 ($5); }
+
+ | MOVW opt_es EXPR '[' C ']' ',' AX
+ { B1 (0x68); O2 ($3); }
+
+ | MOVW AX ',' opt_es EXPR '[' BC ']'
+ { B1 (0x79); O2 ($5); }
+
+ | MOVW AX ',' opt_es '[' BC ']'
+ { B3 (0x79, 0, 0); }
+
+ | MOVW opt_es EXPR '[' BC ']' ',' AX
+ { B1 (0x78); O2 ($3); }
+
+ | MOVW opt_es '[' BC ']' ',' AX
+ { B3 (0x78, 0, 0); }
+
+ | MOVW AX ',' opt_es '[' SP '+' EXPR ']' {NOT_ES}
+ { B1 (0xa8); O1 ($8); WA($8);}
+
+ | MOVW AX ',' opt_es '[' SP ']' {NOT_ES}
+ { B2 (0xa8, 0); }
+
+ | MOVW opt_es '[' SP '+' EXPR ']' ',' AX {NOT_ES}
+ { B1 (0xb8); O1 ($6); WA($6); }
+
+ | MOVW opt_es '[' SP ']' ',' AX {NOT_ES}
+ { B2 (0xb8, 0); }
+
+ | MOVW regw_na ',' EXPR {SA($4)}
+ { B1 (0xca); F ($2, 2, 2); O1 ($4); WA($4); }
+
+ | MOVW regw_na ',' opt_es '!' EXPR
+ { B1 (0xcb); F ($2, 2, 2); O2 ($6); WA($6); }
+
+ | MOVW SP ',' '#' EXPR
+ { B2 (0xcb, 0xf8); O2 ($5); }
+
+ | MOVW SP ',' AX
+ { B2 (0xbe, 0xf8); }
+
+ | MOVW AX ',' SP
+ { B2 (0xae, 0xf8); }
+
+ | MOVW regw_na ',' SP
+ { B3 (0xcb, 0xf8, 0xff); F ($2, 2, 2); }
+
+/* ---------------------------------------------------------------------- */
+
+ | NOP
+ { B1 (0x00); }
+
+/* ---------------------------------------------------------------------- */
+
+ | POP regw
+ { B1 (0xc0); F ($2, 5, 2); }
+
+ | POP PSW
+ { B2 (0x61, 0xcd); };
+
+ | PUSH regw
+ { B1 (0xc1); F ($2, 5, 2); }
+
+ | PUSH PSW
+ { B2 (0x61, 0xdd); };
+
+/* ---------------------------------------------------------------------- */
+
+ | RET
+ { B1 (0xd7); }
+
+ | RETI
+ { B2 (0x61, 0xfc); }
+
+ | RETB
+ { B2 (0x61, 0xec); }
+
+/* ---------------------------------------------------------------------- */
+
+ | ROL A ',' EXPR
+ { if (check_expr_is_const ($4, 1, 1))
+ { B2 (0x61, 0xeb); }
+ }
+
+ | ROLC A ',' EXPR
+ { if (check_expr_is_const ($4, 1, 1))
+ { B2 (0x61, 0xdc); }
+ }
+
+ | ROLWC AX ',' EXPR
+ { if (check_expr_is_const ($4, 1, 1))
+ { B2 (0x61, 0xee); }
+ }
+
+ | ROLWC BC ',' EXPR
+ { if (check_expr_is_const ($4, 1, 1))
+ { B2 (0x61, 0xfe); }
+ }
+
+ | ROR A ',' EXPR
+ { if (check_expr_is_const ($4, 1, 1))
+ { B2 (0x61, 0xdb); }
+ }
+
+ | RORC A ',' EXPR
+ { if (check_expr_is_const ($4, 1, 1))
+ { B2 (0x61, 0xfb);}
+ }
+
+/* ---------------------------------------------------------------------- */
+
+ | SAR A ',' EXPR
+ { if (check_expr_is_const ($4, 1, 7))
+ { B2 (0x31, 0x0b); FE ($4, 9, 3); }
+ }
+
+ | SARW AX ',' EXPR
+ { if (check_expr_is_const ($4, 1, 15))
+ { B2 (0x31, 0x0f); FE ($4, 8, 4); }
+ }
+
+/* ---------------------------------------------------------------------- */
+
+ | SEL RB0
+ { B2 (0x61, 0xcf); }
+
+ | SEL RB1
+ { B2 (0x61, 0xdf); }
+
+ | SEL RB2
+ { B2 (0x61, 0xef); }
+
+ | SEL RB3
+ { B2 (0x61, 0xff); }
+
+/* ---------------------------------------------------------------------- */
+
+ | SHL A ',' EXPR
+ { if (check_expr_is_const ($4, 1, 7))
+ { B2 (0x31, 0x09); FE ($4, 9, 3); }
+ }
+
+ | SHL B ',' EXPR
+ { if (check_expr_is_const ($4, 1, 7))
+ { B2 (0x31, 0x08); FE ($4, 9, 3); }
+ }
+
+ | SHL C ',' EXPR
+ { if (check_expr_is_const ($4, 1, 7))
+ { B2 (0x31, 0x07); FE ($4, 9, 3); }
+ }
+
+ | SHLW AX ',' EXPR
+ { if (check_expr_is_const ($4, 1, 15))
+ { B2 (0x31, 0x0d); FE ($4, 8, 4); }
+ }
+
+ | SHLW BC ',' EXPR
+ { if (check_expr_is_const ($4, 1, 15))
+ { B2 (0x31, 0x0c); FE ($4, 8, 4); }
+ }
+
+/* ---------------------------------------------------------------------- */
+
+ | SHR A ',' EXPR
+ { if (check_expr_is_const ($4, 1, 7))
+ { B2 (0x31, 0x0a); FE ($4, 9, 3); }
+ }
+
+ | SHRW AX ',' EXPR
+ { if (check_expr_is_const ($4, 1, 15))
+ { B2 (0x31, 0x0e); FE ($4, 8, 4); }
+ }
+
+/* ---------------------------------------------------------------------- */
+
+ | SKC
+ { B2 (0x61, 0xc8); }
+
+ | SKH
+ { B2 (0x61, 0xe3); }
+
+ | SKNC
+ { B2 (0x61, 0xd8); }
+
+ | SKNH
+ { B2 (0x61, 0xf3); }
+
+ | SKNZ
+ { B2 (0x61, 0xf8); }
+
+ | SKZ
+ { B2 (0x61, 0xe8); }
+
+/* ---------------------------------------------------------------------- */
+
+ | STOP
+ { B2 (0x61, 0xfd); }
+
+/* ---------------------------------------------------------------------- */
+
+ | XCH A ',' regb_na
+ { if ($4 == 0) /* X */
+ { B1 (0x08); }
+ else
+ { B2 (0x61, 0x88); F ($4, 13, 3); }
+ }
+
+ | XCH A ',' opt_es '!' EXPR
+ { B2 (0x61, 0xaa); O2 ($6); }
+
+ | XCH A ',' opt_es '[' DE ']'
+ { B2 (0x61, 0xae); }
+
+ | XCH A ',' opt_es '[' DE '+' EXPR ']'
+ { B2 (0x61, 0xaf); O1 ($8); }
+
+ | XCH A ',' opt_es '[' HL ']'
+ { B2 (0x61, 0xac); }
+
+ | XCH A ',' opt_es '[' HL '+' EXPR ']'
+ { B2 (0x61, 0xad); O1 ($8); }
+
+ | XCH A ',' opt_es '[' HL '+' B ']'
+ { B2 (0x61, 0xb9); }
+
+ | XCH A ',' opt_es '[' HL '+' C ']'
+ { B2 (0x61, 0xa9); }
+
+ | XCH A ',' EXPR
+ { if (expr_is_sfr ($4))
+ { B2 (0x61, 0xab); O1 ($4); }
+ else if (expr_is_saddr ($4))
+ { B2 (0x61, 0xa8); O1 ($4); }
+ else
+ NOT_SFR_OR_SADDR;
+ }
+
+/* ---------------------------------------------------------------------- */
+
+ | XCHW AX ',' regw_na
+ { B1 (0x31); F ($4, 5, 2); }
+
+/* ---------------------------------------------------------------------- */
+
+ ; /* end of statement */
+
+/* ---------------------------------------------------------------------- */
+
+opt_es : /* nothing */
+ | ES ':'
+ { rl78_prefix (0x11); }
+ ;
+
+regb : X { $$ = 0; }
+ | A { $$ = 1; }
+ | C { $$ = 2; }
+ | B { $$ = 3; }
+ | E { $$ = 4; }
+ | D { $$ = 5; }
+ | L { $$ = 6; }
+ | H { $$ = 7; }
+ ;
+
+regb_na : X { $$ = 0; }
+ | C { $$ = 2; }
+ | B { $$ = 3; }
+ | E { $$ = 4; }
+ | D { $$ = 5; }
+ | L { $$ = 6; }
+ | H { $$ = 7; }
+ ;
+
+regw : AX { $$ = 0; }
+ | BC { $$ = 1; }
+ | DE { $$ = 2; }
+ | HL { $$ = 3; }
+ ;
+
+regw_na : BC { $$ = 1; }
+ | DE { $$ = 2; }
+ | HL { $$ = 3; }
+ ;
+
+sfr : SPL { $$ = 0xf8; }
+ | SPH { $$ = 0xf9; }
+ | PSW { $$ = 0xfa; }
+ | CS { $$ = 0xfc; }
+ | ES { $$ = 0xfd; }
+ | PMC { $$ = 0xfe; }
+ | MEM { $$ = 0xff; }
+ ;
+
+/* ---------------------------------------------------------------------- */
+/* Shortcuts for groups of opcodes with common encodings. */
+
+addsub : ADD { $$ = 0x00; }
+ | ADDC { $$ = 0x10; }
+ | SUB { $$ = 0x20; }
+ | SUBC { $$ = 0x30; }
+ | CMP { $$ = 0x40; }
+ | AND_ { $$ = 0x50; }
+ | OR { $$ = 0x60; }
+ | XOR { $$ = 0x70; }
+ ;
+
+addsubw : ADDW { $$ = 0x00; }
+ | SUBW { $$ = 0x20; }
+ | CMPW { $$ = 0x40; }
+ ;
+
+andor1 : AND1 { $$ = 0x05; }
+ | OR1 { $$ = 0x06; }
+ | XOR1 { $$ = 0x07; }
+ ;
+
+bt_bf : BT { $$ = 0x02; }
+ | BF { $$ = 0x04; }
+ | BTCLR { $$ = 0x00; }
+ ;
+
+setclr1 : SET1 { $$ = 0; }
+ | CLR1 { $$ = 1; }
+ ;
+
+oneclrb : ONEB { $$ = 0x00; }
+ | CLRB { $$ = 0x10; }
+ ;
+
+oneclrw : ONEW { $$ = 0x00; }
+ | CLRW { $$ = 0x10; }
+ ;
+
+incdec : INC { $$ = 0x00; }
+ | DEC { $$ = 0x10; }
+ ;
+
+incdecw : INCW { $$ = 0x00; }
+ | DECW { $$ = 0x10; }
+ ;
+
+%%
+/* ====================================================================== */
+
+static struct
+{
+ const char * string;
+ int token;
+ int val;
+}
+token_table[] =
+{
+ { "r0", X, 0 },
+ { "r1", A, 1 },
+ { "r2", C, 2 },
+ { "r3", B, 3 },
+ { "r4", E, 4 },
+ { "r5", D, 5 },
+ { "r6", L, 6 },
+ { "r7", H, 7 },
+ { "x", X, 0 },
+ { "a", A, 1 },
+ { "c", C, 2 },
+ { "b", B, 3 },
+ { "e", E, 4 },
+ { "d", D, 5 },
+ { "l", L, 6 },
+ { "h", H, 7 },
+
+ { "rp0", AX, 0 },
+ { "rp1", BC, 1 },
+ { "rp2", DE, 2 },
+ { "rp3", HL, 3 },
+ { "ax", AX, 0 },
+ { "bc", BC, 1 },
+ { "de", DE, 2 },
+ { "hl", HL, 3 },
+
+ { "RB0", RB0, 0 },
+ { "RB1", RB1, 1 },
+ { "RB2", RB2, 2 },
+ { "RB3", RB3, 3 },
+
+ { "sp", SP, 0 },
+ { "cy", CY, 0 },
+
+ { "spl", SPL, 0xf8 },
+ { "sph", SPH, 0xf9 },
+ { "psw", PSW, 0xfa },
+ { "cs", CS, 0xfc },
+ { "es", ES, 0xfd },
+ { "pmc", PMC, 0xfe },
+ { "mem", MEM, 0xff },
+
+ { ".s", DOT_S, 0 },
+ { ".b", DOT_B, 0 },
+ { ".w", DOT_W, 0 },
+ { ".l", DOT_L, 0 },
+ { ".a", DOT_A , 0},
+ { ".ub", DOT_UB, 0 },
+ { ".uw", DOT_UW , 0},
+
+ { "c", FLAG, 0 },
+ { "z", FLAG, 1 },
+ { "s", FLAG, 2 },
+ { "o", FLAG, 3 },
+ { "i", FLAG, 8 },
+ { "u", FLAG, 9 },
+
+#define OPC(x) { #x, x, IS_OPCODE }
+
+ OPC(ADD),
+ OPC(ADDC),
+ OPC(ADDW),
+ { "and", AND_, IS_OPCODE },
+ OPC(AND1),
+ OPC(BC),
+ OPC(BF),
+ OPC(BH),
+ OPC(BNC),
+ OPC(BNH),
+ OPC(BNZ),
+ OPC(BR),
+ OPC(BRK),
+ OPC(BRK1),
+ OPC(BT),
+ OPC(BTCLR),
+ OPC(BZ),
+ OPC(CALL),
+ OPC(CALLT),
+ OPC(CLR1),
+ OPC(CLRB),
+ OPC(CLRW),
+ OPC(CMP),
+ OPC(CMP0),
+ OPC(CMPS),
+ OPC(CMPW),
+ OPC(DEC),
+ OPC(DECW),
+ OPC(DI),
+ OPC(DIVHU),
+ OPC(DIVWU),
+ OPC(EI),
+ OPC(HALT),
+ OPC(INC),
+ OPC(INCW),
+ OPC(MACH),
+ OPC(MACHU),
+ OPC(MOV),
+ OPC(MOV1),
+ OPC(MOVS),
+ OPC(MOVW),
+ OPC(MULH),
+ OPC(MULHU),
+ OPC(MULU),
+ OPC(NOP),
+ OPC(ONEB),
+ OPC(ONEW),
+ OPC(OR),
+ OPC(OR1),
+ OPC(POP),
+ OPC(PUSH),
+ OPC(RET),
+ OPC(RETI),
+ OPC(RETB),
+ OPC(ROL),
+ OPC(ROLC),
+ OPC(ROLWC),
+ OPC(ROR),
+ OPC(RORC),
+ OPC(SAR),
+ OPC(SARW),
+ OPC(SEL),
+ OPC(SET1),
+ OPC(SHL),
+ OPC(SHLW),
+ OPC(SHR),
+ OPC(SHRW),
+ OPC(SKC),
+ OPC(SKH),
+ OPC(SKNC),
+ OPC(SKNH),
+ OPC(SKNZ),
+ OPC(SKZ),
+ OPC(STOP),
+ OPC(SUB),
+ OPC(SUBC),
+ OPC(SUBW),
+ OPC(XCH),
+ OPC(XCHW),
+ OPC(XOR),
+ OPC(XOR1),
+};
+
+#define NUM_TOKENS (sizeof (token_table) / sizeof (token_table[0]))
+
+void
+rl78_lex_init (char * beginning, char * ending)
+{
+ rl78_init_start = beginning;
+ rl78_lex_start = beginning;
+ rl78_lex_end = ending;
+ rl78_in_brackets = 0;
+ rl78_last_token = 0;
+
+ setbuf (stdout, 0);
+}
+
+static int
+rl78_lex (void)
+{
+ /*unsigned int ci;*/
+ char * save_input_pointer;
+
+ while (ISSPACE (*rl78_lex_start)
+ && rl78_lex_start != rl78_lex_end)
+ rl78_lex_start ++;
+
+ rl78_last_exp_start = rl78_lex_start;
+
+ if (rl78_lex_start == rl78_lex_end)
+ return 0;
+
+ if (ISALPHA (*rl78_lex_start)
+ || (*rl78_lex_start == '.' && ISALPHA (rl78_lex_start[1])))
+ {
+ unsigned int i;
+ char * e;
+ char save;
+
+ for (e = rl78_lex_start + 1;
+ e < rl78_lex_end && ISALNUM (*e);
+ e ++)
+ ;
+ save = *e;
+ *e = 0;
+
+ for (i = 0; i < NUM_TOKENS; i++)
+ if (strcasecmp (rl78_lex_start, token_table[i].string) == 0
+ && !(token_table[i].val == IS_OPCODE && rl78_last_token != 0)
+ && !(token_table[i].token == FLAG && !need_flag))
+ {
+ rl78_lval.regno = token_table[i].val;
+ *e = save;
+ rl78_lex_start = e;
+ rl78_last_token = token_table[i].token;
+ return token_table[i].token;
+ }
+ *e = save;
+ }
+
+ if (rl78_last_token == 0)
+ {
+ rl78_last_token = UNKNOWN_OPCODE;
+ return UNKNOWN_OPCODE;
+ }
+
+ if (rl78_last_token == UNKNOWN_OPCODE)
+ return 0;
+
+ if (*rl78_lex_start == '[')
+ rl78_in_brackets = 1;
+ if (*rl78_lex_start == ']')
+ rl78_in_brackets = 0;
+
+ /* '.' is funny - the syntax includes it for bitfields, but only for
+ bitfields. We check for it specially so we can allow labels
+ with '.' in them. */
+
+ if (*rl78_lex_start == '.'
+ && ISDIGIT (rl78_lex_start[1])
+ && (rl78_last_token == ']'
+ || rl78_last_token == A
+ || rl78_last_token == PSW
+ || rl78_last_token == EXPR))
+ {
+ rl78_last_token = *rl78_lex_start;
+ return *rl78_lex_start ++;
+ }
+
+ if ((rl78_in_brackets && *rl78_lex_start == '+')
+ || strchr ("[],#!$:", *rl78_lex_start))
+ {
+ rl78_last_token = *rl78_lex_start;
+ return *rl78_lex_start ++;
+ }
+
+ save_input_pointer = input_line_pointer;
+ input_line_pointer = rl78_lex_start;
+ rl78_lval.exp.X_md = 0;
+ expression (&rl78_lval.exp);
+
+ rl78_lex_start = input_line_pointer;
+ input_line_pointer = save_input_pointer;
+ rl78_last_token = EXPR;
+ return EXPR;
+}
+
+int
+rl78_error (char * str)
+{
+ int len;
+
+ len = rl78_last_exp_start - rl78_init_start;
+
+ as_bad ("%s", rl78_init_start);
+ as_bad ("%*s^ %s", len, "", str);
+ return 0;
+}
+
+static int
+expr_is_sfr (expressionS exp)
+{
+ unsigned long v;
+
+ if (exp.X_op != O_constant)
+ return 0;
+
+ v = exp.X_add_number;
+ if (0xFFF00 <= v && v <= 0xFFFFF)
+ return 1;
+ return 0;
+}
+
+static int
+expr_is_saddr (expressionS exp)
+{
+ unsigned long v;
+
+ if (exp.X_op != O_constant)
+ return 0;
+
+ v = exp.X_add_number;
+ if (0xFFE20 <= v && v <= 0xFFF1F)
+ return 1;
+ return 0;
+}
+
+static int
+expr_is_word_aligned (expressionS exp)
+{
+ unsigned long v;
+
+ if (exp.X_op != O_constant)
+ return 1;
+
+ v = exp.X_add_number;
+ if (v & 1)
+ return 0;
+ return 1;
+
+}
+
+static void
+check_expr_is_bit_index (expressionS exp)
+{
+ int val;
+
+ if (exp.X_op != O_constant)
+ {
+ rl78_error (_("bit index must be a constant"));
+ return;
+ }
+ val = exp.X_add_number;
+
+ if (val < 0 || val > 7)
+ rl78_error (_("rtsd size must be 0..7"));
+}
+
+static int
+exp_val (expressionS exp)
+{
+ if (exp.X_op != O_constant)
+ {
+ rl78_error (_("constant expected"));
+ return 0;
+ }
+ return exp.X_add_number;
+}
+
+static int
+check_expr_is_const (expressionS e, int vmin, int vmax)
+{
+ static char buf[100];
+ if (e.X_op != O_constant
+ || e.X_add_number < vmin
+ || e.X_add_number > vmax)
+ {
+ if (vmin == vmax)
+ sprintf (buf, "%d expected here", vmin);
+ else
+ sprintf (buf, "%d..%d expected here", vmin, vmax);
+ rl78_error(buf);
+ return 0;
+ }
+ return 1;
+}
+
+
Index: gas/config/tc-rl78.c
===================================================================
RCS file: gas/config/tc-rl78.c
diff -N gas/config/tc-rl78.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/config/tc-rl78.c 24 Oct 2011 22:25:21 -0000
@@ -0,0 +1,701 @@
+/* tc-rl78.c -- Assembler for the Renesas RL78
+ Copyright 2011
+ Free Software Foundation, Inc.
+
+ This file is part of GAS, the GNU Assembler.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GAS; see the file COPYING. If not, write to the Free
+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+ 02110-1301, USA. */
+
+#include "as.h"
+#include "struc-symbol.h"
+#include "obstack.h"
+#include "safe-ctype.h"
+#include "dwarf2dbg.h"
+#include "libbfd.h"
+#include "elf/common.h"
+#include "elf/rl78.h"
+#include "rl78-defs.h"
+#include "filenames.h"
+#include "listing.h"
+#include "sb.h"
+#include "macro.h"
+
+const char comment_chars[] = ";";
+/* Note that input_file.c hand checks for '#' at the beginning of the
+ first line of the input file. This is because the compiler outputs
+ #NO_APP at the beginning of its output. */
+const char line_comment_chars[] = "#";
+const char line_separator_chars[] = "|";
+
+const char EXP_CHARS[] = "eE";
+const char FLT_CHARS[] = "dD";
+
+/*------------------------------------------------------------------*/
+
+char * rl78_lex_start;
+char * rl78_lex_end;
+
+typedef struct rl78_bytesT
+{
+ char prefix[1];
+ int n_prefix;
+ char base[4];
+ int n_base;
+ char ops[8];
+ int n_ops;
+ struct
+ {
+ expressionS exp;
+ char offset;
+ char nbits;
+ char type; /* RL78REL_*. */
+ int reloc;
+ fixS * fixP;
+ } fixups[2];
+ int n_fixups;
+ struct
+ {
+ char type;
+ char field_pos;
+ char val_ofs;
+ } relax[2];
+ int n_relax;
+ int link_relax;
+ fixS *link_relax_fixP;
+ char times_grown;
+ char times_shrank;
+} rl78_bytesT;
+
+static rl78_bytesT rl78_bytes;
+
+static void
+rl78_fixup (expressionS exp, int offsetbits, int nbits, int type)
+{
+ rl78_bytes.fixups[rl78_bytes.n_fixups].exp = exp;
+ rl78_bytes.fixups[rl78_bytes.n_fixups].offset = offsetbits;
+ rl78_bytes.fixups[rl78_bytes.n_fixups].nbits = nbits;
+ rl78_bytes.fixups[rl78_bytes.n_fixups].type = type;
+ rl78_bytes.fixups[rl78_bytes.n_fixups].reloc = exp.X_md;
+ rl78_bytes.n_fixups ++;
+}
+
+#define rl78_field_fixup(exp, offset, nbits, type) \
+ rl78_fixup (exp, offset + 8 * rl78_bytes.n_prefix), nbits, type)
+
+#define rl78_op_fixup(exp, offset, nbits, type) \
+ rl78_fixup (exp, offset + 8 * (rl78_bytes.n_prefix + rl78_bytes.n_base), nbits, type)
+
+void
+rl78_prefix (int p)
+{
+ rl78_bytes.prefix[0] = p;
+ rl78_bytes.n_prefix = 1;
+}
+
+int
+rl78_has_prefix ()
+{
+ return rl78_bytes.n_prefix;
+}
+
+void
+rl78_base1 (int b1)
+{
+ rl78_bytes.base[0] = b1;
+ rl78_bytes.n_base = 1;
+}
+
+void
+rl78_base2 (int b1, int b2)
+{
+ rl78_bytes.base[0] = b1;
+ rl78_bytes.base[1] = b2;
+ rl78_bytes.n_base = 2;
+}
+
+void
+rl78_base3 (int b1, int b2, int b3)
+{
+ rl78_bytes.base[0] = b1;
+ rl78_bytes.base[1] = b2;
+ rl78_bytes.base[2] = b3;
+ rl78_bytes.n_base = 3;
+}
+
+void
+rl78_base4 (int b1, int b2, int b3, int b4)
+{
+ rl78_bytes.base[0] = b1;
+ rl78_bytes.base[1] = b2;
+ rl78_bytes.base[2] = b3;
+ rl78_bytes.base[3] = b4;
+ rl78_bytes.n_base = 4;
+}
+
+#define F_PRECISION 2
+
+void
+rl78_op (expressionS exp, int nbytes, int type)
+{
+ int v = 0;
+
+ if ((exp.X_op == O_constant || exp.X_op == O_big)
+ && type != RL78REL_PCREL)
+ {
+ if (exp.X_op == O_big && exp.X_add_number <= 0)
+ {
+ LITTLENUM_TYPE w[2];
+ char * ip = rl78_bytes.ops + rl78_bytes.n_ops;
+
+ gen_to_words (w, F_PRECISION, 8);
+ ip[3] = w[0] >> 8;
+ ip[2] = w[0];
+ ip[1] = w[1] >> 8;
+ ip[0] = w[1];
+ rl78_bytes.n_ops += 4;
+ }
+ else
+ {
+ v = exp.X_add_number;
+ while (nbytes)
+ {
+ rl78_bytes.ops[rl78_bytes.n_ops++] =v & 0xff;
+ v >>= 8;
+ nbytes --;
+ }
+ }
+ }
+ else
+ {
+ rl78_op_fixup (exp, rl78_bytes.n_ops * 8, nbytes * 8, type);
+ memset (rl78_bytes.ops + rl78_bytes.n_ops, 0, nbytes);
+ rl78_bytes.n_ops += nbytes;
+ }
+}
+
+/* This gets complicated when the field spans bytes, because fields
+ are numbered from the MSB of the first byte as zero, and bits are
+ stored LSB towards the LSB of the byte. Thus, a simple four-bit
+ insertion of 12 at position 4 of 0x00 yields: 0x0b. A three-bit
+ insertion of b'MXL at position 7 is like this:
+
+ - - - - - - - - - - - - - - - -
+ M X L */
+
+void
+rl78_field (int val, int pos, int sz)
+{
+ int valm;
+ int bytep, bitp;
+
+ if (sz > 0)
+ {
+ if (val < 0 || val >= (1 << sz))
+ as_bad (_("Value %d doesn't fit in unsigned %d-bit field"), val, sz);
+ }
+ else
+ {
+ sz = - sz;
+ if (val < -(1 << (sz - 1)) || val >= (1 << (sz - 1)))
+ as_bad (_("Value %d doesn't fit in signed %d-bit field"), val, sz);
+ }
+
+ /* This code points at 'M' in the above example. */
+ bytep = pos / 8;
+ bitp = pos % 8;
+
+ while (bitp + sz > 8)
+ {
+ int ssz = 8 - bitp;
+ int svalm;
+
+ svalm = val >> (sz - ssz);
+ svalm = svalm & ((1 << ssz) - 1);
+ svalm = svalm << (8 - bitp - ssz);
+ gas_assert (bytep < rl78_bytes.n_base);
+ rl78_bytes.base[bytep] |= svalm;
+
+ bitp = 0;
+ sz -= ssz;
+ bytep ++;
+ }
+ valm = val & ((1 << sz) - 1);
+ valm = valm << (8 - bitp - sz);
+ gas_assert (bytep < rl78_bytes.n_base);
+ rl78_bytes.base[bytep] |= valm;
+}
+
+/*------------------------------------------------------------------*/
+
+#define RL78_SHORTOPTS ""
+const char * md_shortopts = RL78_SHORTOPTS;
+
+/* Assembler options. */
+struct option md_longopts[] =
+{
+ {NULL, no_argument, NULL, 0}
+};
+size_t md_longopts_size = sizeof (md_longopts);
+
+int
+md_parse_option (int c ATTRIBUTE_UNUSED, char * arg ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+
+void
+md_show_usage (FILE * stream ATTRIBUTE_UNUSED)
+{
+}
+
+
+static void
+s_bss (int ignore ATTRIBUTE_UNUSED)
+{
+ int temp;
+
+ temp = get_absolute_expression ();
+ subseg_set (bss_section, (subsegT) temp);
+ demand_empty_rest_of_line ();
+}
+
+/* The target specific pseudo-ops which we support. */
+const pseudo_typeS md_pseudo_table[] =
+{
+ /* Our "standard" pseudos. */
+ { "double", float_cons, 'd' },
+ { "bss", s_bss, 0 },
+ { "3byte", cons, 3 },
+ { "int", cons, 4 },
+ { "word", cons, 4 },
+
+ /* End of list marker. */
+ { NULL, NULL, 0 }
+};
+
+void
+md_begin (void)
+{
+}
+
+void
+rl78_md_end (void)
+{
+}
+
+/* Write a value out to the object file, using the appropriate endianness. */
+void
+md_number_to_chars (char * buf, valueT val, int n)
+{
+ number_to_chars_littleendian (buf, val, n);
+}
+
+static struct
+{
+ char * fname;
+ int reloc;
+}
+reloc_functions[] =
+{
+ { "lo16", BFD_RELOC_RL78_LO16 },
+ { "hi16", BFD_RELOC_RL78_HI16 },
+ { "hi8", BFD_RELOC_RL78_HI8 },
+ { 0, 0 }
+};
+
+void
+md_operand (expressionS * exp ATTRIBUTE_UNUSED)
+{
+ int reloc = 0;
+ int i;
+
+ for (i = 0; reloc_functions[i].fname; i++)
+ {
+ int flen = strlen (reloc_functions[i].fname);
+
+ if (input_line_pointer[0] == '%'
+ && strncasecmp (input_line_pointer + 1, reloc_functions[i].fname, flen) == 0
+ && input_line_pointer[flen + 1] == '(')
+ {
+ reloc = reloc_functions[i].reloc;
+ input_line_pointer += flen + 2;
+ break;
+ }
+ }
+ if (reloc == 0)
+ return;
+
+ expression (exp);
+ if (* input_line_pointer == ')')
+ input_line_pointer ++;
+
+ exp->X_md = reloc;
+}
+
+void
+rl78_frag_init (fragS * fragP)
+{
+ fragP->tc_frag_data = 0;
+}
+
+char *
+md_atof (int type, char * litP, int * sizeP)
+{
+ return ieee_md_atof (type, litP, sizeP, target_big_endian);
+}
+
+symbolS *
+md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
+{
+ return NULL;
+}
+
+#define APPEND(B, N_B) \
+ if (rl78_bytes.N_B) \
+ { \
+ memcpy (bytes + idx, rl78_bytes.B, rl78_bytes.N_B); \
+ idx += rl78_bytes.N_B; \
+ }
+
+
+void
+md_assemble (char * str)
+{
+ char * bytes;
+ fragS * frag_then = frag_now;
+ int idx = 0;
+ int i;
+ int rel;
+ expressionS *exp;
+
+ /*printf("\033[32mASM: %s\033[0m\n", str);*/
+
+ dwarf2_emit_insn (0);
+
+ memset (& rl78_bytes, 0, sizeof (rl78_bytes));
+
+ rl78_lex_init (str, str + strlen (str));
+
+ rl78_parse ();
+
+ bytes = frag_more (rl78_bytes.n_prefix + rl78_bytes.n_base + rl78_bytes.n_ops);
+ frag_then = frag_now;
+
+ APPEND (prefix, n_prefix);
+ APPEND (base, n_base);
+ APPEND (ops, n_ops);
+
+ for (i = 0; i < rl78_bytes.n_fixups; i ++)
+ {
+ /* index: [nbytes][type] */
+ static int reloc_map[5][4] =
+ {
+ { 0, 0 },
+ { BFD_RELOC_8, BFD_RELOC_8_PCREL },
+ { BFD_RELOC_16, BFD_RELOC_16_PCREL },
+ { BFD_RELOC_24, BFD_RELOC_24_PCREL },
+ { BFD_RELOC_32, BFD_RELOC_32_PCREL },
+ };
+ fixS * f;
+
+ idx = rl78_bytes.fixups[i].offset / 8;
+ rel = reloc_map [rl78_bytes.fixups[i].nbits / 8][(int) rl78_bytes.fixups[i].type];
+
+ if (rl78_bytes.fixups[i].reloc)
+ rel = rl78_bytes.fixups[i].reloc;
+
+ if (frag_then->tc_frag_data)
+ exp = & frag_then->tc_frag_data->fixups[i].exp;
+ else
+ exp = & rl78_bytes.fixups[i].exp;
+
+ f = fix_new_exp (frag_then,
+ (char *) bytes + idx - frag_then->fr_literal,
+ rl78_bytes.fixups[i].nbits / 8,
+ exp,
+ rl78_bytes.fixups[i].type == RL78REL_PCREL ? 1 : 0,
+ rel);
+ if (frag_then->tc_frag_data)
+ frag_then->tc_frag_data->fixups[i].fixP = f;
+ }
+}
+
+void
+rl78_cons_fix_new (fragS * frag,
+ int where,
+ int size,
+ expressionS * exp)
+{
+ bfd_reloc_code_real_type type;
+
+ switch (size)
+ {
+ case 1:
+ type = BFD_RELOC_8;
+ break;
+ case 2:
+ type = BFD_RELOC_16;
+ break;
+ case 3:
+ type = BFD_RELOC_24;
+ break;
+ case 4:
+ type = BFD_RELOC_32;
+ break;
+ default:
+ as_bad (_("unsupported constant size %d\n"), size);
+ return;
+ }
+
+ if (exp->X_op == O_subtract && exp->X_op_symbol)
+ {
+ if (size != 4 && size != 2 && size != 1)
+ as_bad (_("difference of two symbols only supported with .long, .short, or .byte"));
+ else
+ type = BFD_RELOC_RL78_DIFF;
+ }
+
+ fix_new_exp (frag, where, (int) size, exp, 0, type);
+}
+
+/* No relaxation just yet */
+int
+md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED, segT segment ATTRIBUTE_UNUSED)
+{
+ return 0;
+}
+arelent **
+tc_gen_reloc (asection * seg ATTRIBUTE_UNUSED, fixS * fixp)
+{
+ static arelent * reloc[8];
+ int rp;
+ int is_opcode = 0;
+
+ if (fixp->fx_r_type == BFD_RELOC_NONE)
+ {
+ reloc[0] = NULL;
+ return reloc;
+ }
+
+ if (fixp->fx_subsy
+ && S_GET_SEGMENT (fixp->fx_subsy) == absolute_section)
+ {
+ fixp->fx_offset -= S_GET_VALUE (fixp->fx_subsy);
+ fixp->fx_subsy = NULL;
+ }
+
+ reloc[0] = (arelent *) xmalloc (sizeof (arelent));
+ reloc[0]->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
+ * reloc[0]->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
+ reloc[0]->address = fixp->fx_frag->fr_address + fixp->fx_where;
+ reloc[0]->addend = fixp->fx_offset;
+
+ if (fixp->fx_r_type == BFD_RELOC_RL78_32_OP
+ && fixp->fx_subsy)
+ {
+ fixp->fx_r_type = BFD_RELOC_RL78_DIFF;
+ is_opcode = 1;
+ }
+
+#define OPX(REL,SYM,ADD) \
+ reloc[rp] = (arelent *) xmalloc (sizeof (arelent)); \
+ reloc[rp]->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); \
+ reloc[rp]->howto = bfd_reloc_type_lookup (stdoutput, REL); \
+ reloc[rp]->addend = ADD; \
+ * reloc[rp]->sym_ptr_ptr = SYM; \
+ reloc[rp]->address = fixp->fx_frag->fr_address + fixp->fx_where; \
+ reloc[++rp] = NULL
+#define OPSYM(SYM) OPX(BFD_RELOC_RL78_SYM, SYM, 0)
+#define OPIMM(IMM) OPX(BFD_RELOC_RL78_SYM, abs_symbol.bsym, IMM)
+#define OP(OP) OPX(BFD_RELOC_RL78_##OP, *reloc[0]->sym_ptr_ptr, 0)
+#define SYM0() reloc[0]->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_RL78_SYM)
+
+ rp = 1;
+
+ /* Certain BFD relocations cannot be translated directly into
+ a single (non-Red Hat) RL78 relocation, but instead need
+ multiple RL78 relocations - handle them here. */
+ switch (fixp->fx_r_type)
+ {
+ case BFD_RELOC_RL78_DIFF:
+ SYM0 ();
+ OPSYM (symbol_get_bfdsym (fixp->fx_subsy));
+ OP(OP_SUBTRACT);
+
+ switch (fixp->fx_size)
+ {
+ case 1:
+ OP(ABS8);
+ break;
+ case 2:
+ OP (ABS16);
+ break;
+ case 4:
+ OP (ABS32);
+ break;
+ }
+ break;
+
+ case BFD_RELOC_RL78_NEG32:
+ SYM0 ();
+ OP (OP_NEG);
+ OP (ABS32);
+ break;
+
+ case BFD_RELOC_RL78_LO16:
+ SYM0 ();
+ OPIMM (0xffff);
+ OP (OP_AND);
+ OP (ABS16);
+ break;
+
+ case BFD_RELOC_RL78_HI16:
+ SYM0 ();
+ OPIMM (16);
+ OP (OP_SHRA);
+ OP (ABS16);
+ break;
+
+ case BFD_RELOC_RL78_HI8:
+ SYM0 ();
+ OPIMM (16);
+ OP (OP_SHRA);
+ OPIMM (0xff);
+ OP (OP_AND);
+ OP (ABS8);
+ break;
+
+ default:
+ reloc[0]->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
+ reloc[1] = NULL;
+ break;
+ }
+
+ return reloc;
+}
+
+int
+rl78_validate_fix_sub (struct fix * f)
+{
+ /* We permit the subtraction of two symbols in a few cases. */
+ /* mov #sym1-sym2, R3 */
+ if (f->fx_r_type == BFD_RELOC_RL78_32_OP)
+ return 1;
+ /* .long sym1-sym2 */
+ if (f->fx_r_type == BFD_RELOC_RL78_DIFF
+ && ! f->fx_pcrel
+ && (f->fx_size == 4 || f->fx_size == 2 || f->fx_size == 1))
+ return 1;
+ return 0;
+}
+
+long
+md_pcrel_from_section (fixS * fixP, segT sec)
+{
+ long rv;
+
+ if (fixP->fx_addsy != NULL
+ && (! S_IS_DEFINED (fixP->fx_addsy)
+ || S_GET_SEGMENT (fixP->fx_addsy) != sec))
+ /* The symbol is undefined (or is defined but not in this section).
+ Let the linker figure it out. */
+ return 0;
+
+ rv = fixP->fx_frag->fr_address + fixP->fx_where;
+ switch (fixP->fx_r_type)
+ {
+ case BFD_RELOC_8_PCREL:
+ rv += 1;
+ break;
+ case BFD_RELOC_16_PCREL:
+ rv += 2;
+ break;
+ default:
+ break;
+ }
+ return rv;
+}
+
+void
+md_apply_fix (struct fix * f ATTRIBUTE_UNUSED,
+ valueT * t ATTRIBUTE_UNUSED,
+ segT s ATTRIBUTE_UNUSED)
+{
+ char * op;
+ unsigned long val;
+
+ if (f->fx_addsy && S_FORCE_RELOC (f->fx_addsy, 1))
+ return;
+ if (f->fx_subsy && S_FORCE_RELOC (f->fx_subsy, 1))
+ return;
+
+ op = f->fx_frag->fr_literal + f->fx_where;
+ val = (unsigned long) * t;
+
+ switch (f->fx_r_type)
+ {
+ case BFD_RELOC_NONE:
+ break;
+
+ case BFD_RELOC_8:
+ case BFD_RELOC_8_PCREL:
+ op[0] = val;
+ break;
+
+ case BFD_RELOC_16:
+ case BFD_RELOC_16_PCREL:
+ op[0] = val;
+ op[1] = val >> 8;
+ break;
+
+ case BFD_RELOC_24:
+ op[0] = val;
+ op[1] = val >> 8;
+ op[2] = val >> 16;
+ break;
+
+ case BFD_RELOC_32:
+ case BFD_RELOC_RL78_DIFF:
+ op[0] = val;
+ op[1] = val >> 8;
+ op[2] = val >> 16;
+ op[3] = val >> 24;
+ break;
+
+ default:
+ as_bad (_("Unknown reloc in md_apply_fix: %s"),
+ bfd_get_reloc_code_name (f->fx_r_type));
+ break;
+ }
+
+ if (f->fx_addsy == NULL)
+ f->fx_done = 1;
+}
+
+valueT
+md_section_align (segT segment, valueT size)
+{
+ int align = bfd_get_section_alignment (stdoutput, segment);
+ return ((size + (1 << align) - 1) & (-1 << align));
+}
+
+void
+md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED,
+ segT segment ATTRIBUTE_UNUSED,
+ fragS * fragP ATTRIBUTE_UNUSED)
+{
+ /* No relaxation yet */
+}
Index: gas/config/tc-rl78.h
===================================================================
RCS file: gas/config/tc-rl78.h
diff -N gas/config/tc-rl78.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/config/tc-rl78.h 24 Oct 2011 22:25:21 -0000
@@ -0,0 +1,75 @@
+/* tc-rl78.h - header file for Renesas RL78
+ Copyright 2011
+ Free Software Foundation, Inc.
+
+ This file is part of GAS, the GNU Assembler.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GAS; see the file COPYING. If not, write to the Free
+ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+ 02110-1301, USA. */
+
+#define TC_RL78
+
+extern int target_little_endian;
+
+#define LISTING_HEADER "RL78 GAS LE"
+#define LISTING_LHS_WIDTH 8
+#define LISTING_WORD_SIZE 1
+
+#define TARGET_ARCH bfd_arch_rl78
+
+#define TARGET_BYTES_BIG_ENDIAN 0
+
+#define TARGET_FORMAT "elf32-rl78"
+
+/* We don't need to handle .word strangely. */
+#define WORKING_DOT_WORD
+
+/* Permit temporary numeric labels. */
+#define LOCAL_LABELS_FB 1
+/* But make sure that the binutils treat them as locals. */
+#define LOCAL_LABEL_PREFIX '.'
+
+/* Allow classic-style constants. */
+#define NUMBERS_WITH_SUFFIX 1
+
+/* .-foo gets turned into PC relative relocs. */
+#define DIFF_EXPR_OK
+
+#define md_end rl78_md_end
+extern void rl78_md_end (void);
+
+#define TC_FRAG_TYPE struct rl78_bytesT *
+#define TC_FRAG_INIT rl78_frag_init
+extern void rl78_frag_init (fragS *);
+
+/* Call md_pcrel_from_section(), not md_pcrel_from(). */
+#define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP, SEC)
+extern long md_pcrel_from_section (struct fix *, segT);
+
+/* RL78 doesn't have a 32 bit PCREL relocations. */
+#define TC_FORCE_RELOCATION_SUB_LOCAL(FIX, SEG) 1
+
+#define TC_VALIDATE_FIX_SUB(FIX, SEG) \
+ rl78_validate_fix_sub (FIX)
+extern int rl78_validate_fix_sub (struct fix *);
+
+#define TC_CONS_FIX_NEW(FRAG, WHERE, NBYTES, EXP) \
+ rl78_cons_fix_new (FRAG, WHERE, NBYTES, EXP)
+extern void rl78_cons_fix_new (fragS *, int, int, expressionS *);
+
+#define tc_fix_adjustable(x) 0
+
+#define RELOC_EXPANSION_POSSIBLE 1
+#define MAX_RELOC_EXPANSION 8
Index: include/dis-asm.h
===================================================================
RCS file: /cvs/src/src/include/dis-asm.h,v
retrieving revision 1.81
diff -p -U5 -r1.81 dis-asm.h
--- include/dis-asm.h 13 Jun 2011 15:18:53 -0000 1.81
+++ include/dis-asm.h 24 Oct 2011 22:25:22 -0000
@@ -296,10 +296,11 @@ extern int print_insn_xstormy16 (bfd_vm
extern int print_insn_xtensa (bfd_vma, disassemble_info *);
extern int print_insn_z80 (bfd_vma, disassemble_info *);
extern int print_insn_z8001 (bfd_vma, disassemble_info *);
extern int print_insn_z8002 (bfd_vma, disassemble_info *);
extern int print_insn_rx (bfd_vma, disassemble_info *);
+extern int print_insn_rl78 (bfd_vma, disassemble_info *);
extern disassembler_ftype arc_get_disassembler (void *);
extern disassembler_ftype cris_get_disassembler (bfd *);
extern void print_i386_disassembler_options (FILE *);
Index: include/elf/common.h
===================================================================
RCS file: /cvs/src/src/include/elf/common.h,v
retrieving revision 1.132
diff -p -U5 -r1.132 common.h
--- include/elf/common.h 22 Jul 2011 20:22:36 -0000 1.132
+++ include/elf/common.h 24 Oct 2011 22:25:23 -0000
@@ -294,10 +294,12 @@
#define EM_TILE64 187 /* Tilera TILE64 multicore architecture family */
#define EM_TILEPRO 188 /* Tilera TILEPro multicore architecture family */
#define EM_MICROBLAZE 189 /* Xilinx MicroBlaze 32-bit RISC soft processor core */
#define EM_CUDA 190 /* NVIDIA CUDA architecture */
#define EM_TILEGX 191 /* Tilera TILE-Gx multicore architecture family */
+#define EM_RL78 197 /* Renesas RL78 family. */
+#define EM_78K0R 199 /* Renesas 78K0R. */
/* If it is necessary to assign new unofficial EM_* values, please pick large
random numbers (0x8523, 0xa7f2, etc.) to minimize the chances of collision
with official or non-GNU unofficial values.
Index: include/elf/rl78.h
===================================================================
RCS file: include/elf/rl78.h
diff -N include/elf/rl78.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ include/elf/rl78.h 24 Oct 2011 22:25:23 -0000
@@ -0,0 +1,118 @@
+/* RL78 ELF support for BFD.
+ Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc.
+
+ This file is part of BFD, the Binary File Descriptor library.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation,
+ Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+
+#ifndef _ELF_RL78_H
+#define _ELF_RL78_H
+
+#include "elf/reloc-macros.h"
+
+/* Note that there are a few internal relocation types used by the
+ linker to do link-time relaxation. If you update this file, please
+ check elf32-rl78.c to see if any of the internal relocations need to
+ be, er, relocated. */
+
+/* Preliminary relocations. */
+START_RELOC_NUMBERS (elf_rl78_reloc_type)
+
+ RELOC_NUMBER (R_RL78_NONE, 0x00)
+ /* These are for data, and are bi-endian. */
+ RELOC_NUMBER (R_RL78_DIR32, 0x01) /* Was: R_RL78_32. */
+ RELOC_NUMBER (R_RL78_DIR24S, 0x02) /* Was: R_RL78_24. */
+ RELOC_NUMBER (R_RL78_DIR16, 0x03)
+ RELOC_NUMBER (R_RL78_DIR16U, 0x04) /* Was: R_RL78_16_UNS. */
+ RELOC_NUMBER (R_RL78_DIR16S, 0x05) /* Was: R_RL78_16. */
+ RELOC_NUMBER (R_RL78_DIR8, 0x06)
+ RELOC_NUMBER (R_RL78_DIR8U, 0x07) /* Was: R_RL78_8_UNS. */
+ RELOC_NUMBER (R_RL78_DIR8S, 0x08) /* Was: R_RL78_8. */
+
+ /* Signed pc-relative values. */
+ RELOC_NUMBER (R_RL78_DIR24S_PCREL, 0x09) /* Was: R_RL78_24_PCREL. */
+ RELOC_NUMBER (R_RL78_DIR16S_PCREL, 0x0a) /* Was: R_RL78_16_PCREL. */
+ RELOC_NUMBER (R_RL78_DIR8S_PCREL, 0x0b) /* Was: R_RL78_8_PCREL. */
+
+ /* These are for fields in the instructions. */
+ RELOC_NUMBER (R_RL78_DIR16UL, 0x0c)
+ RELOC_NUMBER (R_RL78_DIR16UW, 0x0d)
+ RELOC_NUMBER (R_RL78_DIR8UL, 0x0e)
+ RELOC_NUMBER (R_RL78_DIR8UW, 0x0f)
+ RELOC_NUMBER (R_RL78_DIR32_REV, 0x10)
+ RELOC_NUMBER (R_RL78_DIR16_REV, 0x11)
+ RELOC_NUMBER (R_RL78_DIR3U_PCREL, 0x12)
+
+ /* These are for complex relocs. */
+ RELOC_NUMBER (R_RL78_ABS32, 0x41)
+ RELOC_NUMBER (R_RL78_ABS24S, 0x42)
+ RELOC_NUMBER (R_RL78_ABS16, 0x43)
+ RELOC_NUMBER (R_RL78_ABS16U, 0x44)
+ RELOC_NUMBER (R_RL78_ABS16S, 0x45)
+ RELOC_NUMBER (R_RL78_ABS8, 0x46)
+ RELOC_NUMBER (R_RL78_ABS8U, 0x47)
+ RELOC_NUMBER (R_RL78_ABS8S, 0x48)
+ RELOC_NUMBER (R_RL78_ABS24S_PCREL, 0x49)
+ RELOC_NUMBER (R_RL78_ABS16S_PCREL, 0x4a)
+ RELOC_NUMBER (R_RL78_ABS8S_PCREL, 0x4b)
+ RELOC_NUMBER (R_RL78_ABS16UL, 0x4c)
+ RELOC_NUMBER (R_RL78_ABS16UW, 0x4d)
+ RELOC_NUMBER (R_RL78_ABS8UL, 0x4e)
+ RELOC_NUMBER (R_RL78_ABS8UW, 0x4f)
+ RELOC_NUMBER (R_RL78_ABS32_REV, 0x50)
+ RELOC_NUMBER (R_RL78_ABS16_REV, 0x51)
+
+ RELOC_NUMBER (R_RL78_SYM, 0x80)
+ RELOC_NUMBER (R_RL78_OPneg, 0x81)
+ RELOC_NUMBER (R_RL78_OPadd, 0x82)
+ RELOC_NUMBER (R_RL78_OPsub, 0x83)
+ RELOC_NUMBER (R_RL78_OPmul, 0x84)
+ RELOC_NUMBER (R_RL78_OPdiv, 0x85)
+ RELOC_NUMBER (R_RL78_OPshla, 0x86)
+ RELOC_NUMBER (R_RL78_OPshra, 0x87)
+ RELOC_NUMBER (R_RL78_OPsctsize, 0x88)
+ RELOC_NUMBER (R_RL78_OPscttop, 0x8d)
+ RELOC_NUMBER (R_RL78_OPand, 0x90)
+ RELOC_NUMBER (R_RL78_OPor, 0x91)
+ RELOC_NUMBER (R_RL78_OPxor, 0x92)
+ RELOC_NUMBER (R_RL78_OPnot, 0x93)
+ RELOC_NUMBER (R_RL78_OPmod, 0x94)
+ RELOC_NUMBER (R_RL78_OPromtop, 0x95)
+ RELOC_NUMBER (R_RL78_OPramtop, 0x96)
+
+END_RELOC_NUMBERS (R_RL78_max)
+
+#define EF_RL78_CPU_RL78 0x00000079 /* FIXME: correct value? */
+#define EF_RL78_CPU_MASK 0x0000007F /* specific cpu bits. */
+#define EF_RL78_ALL_FLAGS (EF_RL78_CPU_MASK)
+
+/* Values for the e_flags field in the ELF header. */
+#define E_FLAG_RL78_64BIT_DOUBLES (1 << 0)
+#define E_FLAG_RL78_DSP (1 << 1) /* Defined in the RL78 CPU Object file specification, but not explained. */
+
+/* These define the addend field of R_RL78_RH_RELAX relocations. */
+#define RL78_RELAXA_IMM6 0x00000010 /* Imm8/16/24/32 at bit offset 6. */
+#define RL78_RELAXA_IMM12 0x00000020 /* Imm8/16/24/32 at bit offset 12. */
+#define RL78_RELAXA_DSP4 0x00000040 /* Dsp0/8/16 at bit offset 4. */
+#define RL78_RELAXA_DSP6 0x00000080 /* Dsp0/8/16 at bit offset 6. */
+#define RL78_RELAXA_DSP14 0x00000100 /* Dsp0/8/16 at bit offset 14. */
+#define RL78_RELAXA_BRA 0x00000200 /* Any type of branch (must be decoded). */
+#define RL78_RELAXA_RNUM 0x0000000f /* Number of associated relocations. */
+/* These mark the place where alignment is requested, and the place where the filler bytes end. */
+#define RL78_RELAXA_ALIGN 0x10000000 /* Start alignment; the remaining bits are the alignment value. */
+#define RL78_RELAXA_ELIGN 0x20000000 /* End alignment; the remaining bits are the alignment value. */
+#define RL78_RELAXA_ANUM 0x00ffffff /* Alignment amount, in bytes (i.e. .balign). */
+
+#endif /* _ELF_RL78_H */
Index: include/opcode/rl78.h
===================================================================
RCS file: include/opcode/rl78.h
diff -N include/opcode/rl78.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ include/opcode/rl78.h 24 Oct 2011 22:25:23 -0000
@@ -0,0 +1,168 @@
+/* Opcode decoder for the Renesas RL78
+ Copyright 2011
+ Free Software Foundation, Inc.
+ Written by DJ Delorie <dj@redhat.com>
+
+ This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
+ 02110-1301, USA. */
+
+/* The RL78 decoder in libopcodes is used by the simulator, gdb's
+ analyzer, and the disassembler. Given an opcode data source, it
+ decodes the next opcode into the following structures. */
+
+#ifndef RL78_OPCODES_H_INCLUDED
+#define RL78_OPCODES_H_INCLUDED
+
+/* For the purposes of these structures, the RL78 registers are as
+ follows, despite most of these being memory-mapped and
+ bank-switched: */
+typedef enum {
+ RL78_Reg_None,
+ /* The order of these matches the encodings. */
+ RL78_Reg_X,
+ RL78_Reg_A,
+ RL78_Reg_C,
+ RL78_Reg_B,
+ RL78_Reg_E,
+ RL78_Reg_D,
+ RL78_Reg_L,
+ RL78_Reg_H,
+ /* The order of these matches the encodings. */
+ RL78_Reg_AX,
+ RL78_Reg_BC,
+ RL78_Reg_DE,
+ RL78_Reg_HL,
+ /* Unordered. */
+ RL78_Reg_SP,
+ RL78_Reg_PSW,
+ RL78_Reg_CS,
+ RL78_Reg_ES,
+ RL78_Reg_PMC,
+ RL78_Reg_MEM
+} RL78_Register;
+
+typedef enum
+{
+ RL78_Byte = 0,
+ RL78_Word
+} RL78_Size;
+
+typedef enum {
+ RL78_Condition_T,
+ RL78_Condition_F,
+ RL78_Condition_C,
+ RL78_Condition_NC,
+ RL78_Condition_H,
+ RL78_Condition_NH,
+ RL78_Condition_Z,
+ RL78_Condition_NZ
+} RL78_Condition;
+
+typedef enum {
+ RL78_Operand_None = 0,
+ RL78_Operand_Immediate, /* #addend */
+ RL78_Operand_Register, /* reg */
+ RL78_Operand_Indirect, /* [reg + reg2 + addend] */
+ RL78_Operand_Bit, /* reg.bit */
+ RL78_Operand_BitIndirect, /* [reg+reg2+addend].bit */
+ RL78_Operand_PreDec, /* [--reg] = push */
+ RL78_Operand_PostInc /* [reg++] = pop */
+} RL78_Operand_Type;
+
+typedef enum
+{
+ RLO_unknown,
+ RLO_add, /* d += s */
+ RLO_addc, /* d += s + CY */
+ RLO_and, /* d &= s (byte, word, bit) */
+ RLO_branch, /* pc = d */
+ RLO_branch_cond, /* pc = d if cond(src) */
+ RLO_branch_cond_clear, /* pc = d if cond(src), and clear(src) */
+ RLO_break, /* BRK */
+ RLO_call, /* call */
+ RLO_cmp, /* cmp d, s */
+ RLO_divhu, /* DIVHU */
+ RLO_divwu, /* DIVWU */
+ RLO_halt, /* HALT */
+ RLO_mov, /* d = s */
+ RLO_mach, /* MACH */
+ RLO_machu, /* MACHU */
+ RLO_mulu, /* MULU */
+ RLO_mulh, /* MULH */
+ RLO_mulhu, /* MULHU */
+ RLO_nop, /* NOP */
+ RLO_or, /* d |= s */
+ RLO_ret, /* RET */
+ RLO_reti, /* RETI */
+ RLO_rol, /* d <<= s, MSB to LSB and CY */
+ RLO_rolc, /* d <<= s, MSB to CY, CY, to LSB */
+ RLO_ror, /* d >>= s, LSB to MSB and CY */
+ RLO_rorc, /* d >>= s, LSB to CY, CY, to MSB */
+ RLO_sar, /* d >>= s, signed */
+ RLO_sel, /* rb = s */
+ RLO_shr, /* d >>= s, unsigned */
+ RLO_shl, /* d <<= s */
+ RLO_skip, /* skip next insn is cond(s) */
+ RLO_stop, /* STOP */
+ RLO_sub, /* d -= s */
+ RLO_subc, /* d -= s - CY */
+ RLO_xch, /* swap d, s */
+ RLO_xor, /* d ^= s */
+} RL78_Opcode_ID;
+
+typedef struct {
+ RL78_Operand_Type type;
+ int addend;
+ RL78_Register reg : 8;
+ RL78_Register reg2 : 8;
+ unsigned char bit_number : 4;
+ unsigned char condition : 3;
+ unsigned char use_es : 1;
+} RL78_Opcode_Operand;
+
+/* PSW flag bits */
+#define RL78_PSW_IE 0x80
+#define RL78_PSW_Z 0x40
+#define RL78_PSW_RBS1 0x20
+#define RL78_PSW_AC 0x10
+#define RL78_PSW_RBS0 0x08
+#define RL78_PSW_ISP1 0x04
+#define RL78_PSW_ISP0 0x02
+#define RL78_PSW_CY 0x01
+
+#define RL78_SFR_SP 0xffff8
+#define RL78_SFR_PSW 0xffffa
+#define RL78_SFR_CS 0xffffc
+#define RL78_SFR_ES 0xffffd
+#define RL78_SFR_PMC 0xffffe
+#define RL78_SFR_MEM 0xfffff
+
+typedef struct
+{
+ int lineno;
+ RL78_Opcode_ID id:24;
+ unsigned flags:8; /* PSW mask, for side effects only */
+ int n_bytes;
+ char * syntax;
+ RL78_Size size;
+ /* By convention, these are destination, source. */
+ RL78_Opcode_Operand op[2];
+} RL78_Opcode_Decoded;
+
+int rl78_decode_opcode (unsigned long, RL78_Opcode_Decoded *, int (*)(void *), void *);
+
+#endif
Index: ld/Makefile.am
===================================================================
RCS file: /cvs/src/src/ld/Makefile.am,v
retrieving revision 1.305
diff -p -U5 -r1.305 Makefile.am
--- ld/Makefile.am 22 Jul 2011 20:22:37 -0000 1.305
+++ ld/Makefile.am 24 Oct 2011 22:25:23 -0000
@@ -244,10 +244,11 @@ ALL_EMULATION_SOURCES = \
eelf32ppclinux.c \
eelf32ppcnto.c \
eelf32ppcsim.c \
eelf32ppcvxworks.c \
eelf32ppcwindiss.c \
+ eelf32rl78.c \
eelf32rx.c \
eelf32tilegx.c \
eelf32tilepro.c \
eelf32vax.c \
eelf32xc16x.c \
@@ -1134,10 +1135,13 @@ eelf32ppcvxworks.c: $(srcdir)/emulparams
$(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf32ppcvxworks "$(tdir_elf32ppcvxworks)"
eelf32ppcwindiss.c: $(srcdir)/emulparams/elf32ppcwindiss.sh \
$(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf32ppcwindiss "$(tdir_elf32ppcwindiss)"
+eelf32rl78.c: $(srcdir)/emulparams/elf32rl78.sh \
+ $(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+ ${GENSCRIPTS} elf32rl78 "$(tdir_elf32rl78)"
eelf32rx.c: $(srcdir)/emulparams/elf32rx.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
${GENSCRIPTS} elf32rx "$(tdir_elf32rx)"
eelf32tilegx.c: $(srcdir)/emulparams/elf32tilegx.sh \
$(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/needrelax.em \
Index: ld/configure.tgt
===================================================================
RCS file: /cvs/src/src/ld/configure.tgt,v
retrieving revision 1.252
diff -p -U5 -r1.252 configure.tgt
--- ld/configure.tgt 22 Jul 2011 20:22:37 -0000 1.252
+++ ld/configure.tgt 24 Oct 2011 22:25:23 -0000
@@ -512,10 +512,11 @@ powerpc-*-beos*) targ_emul=aixppc ;;
powerpc-*-windiss*) targ_emul=elf32ppcwindiss ;;
powerpc-*-lynxos*) targ_emul=ppclynx ;;
rs6000-*-aix[5-9]*) targ_emul=aix5rs6 ;;
rs6000-*-aix*) targ_emul=aixrs6
;;
+rl78-*-*) targ_emul=elf32rl78 ;;
rx-*-*) targ_emul=elf32rx ;;
s390x-*-linux*) targ_emul=elf64_s390
targ_extra_emuls=elf_s390
targ_extra_libpath=$targ_extra_emuls
tdir_elf_s390=`echo ${targ_alias} | sed -e 's/s390x/s390/'` ;;
Index: ld/emulparams/elf32rl78.sh
===================================================================
RCS file: ld/emulparams/elf32rl78.sh
diff -N ld/emulparams/elf32rl78.sh
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ ld/emulparams/elf32rl78.sh 24 Oct 2011 22:25:23 -0000
@@ -0,0 +1,26 @@
+MACHINE=
+SCRIPT_NAME=elf
+OUTPUT_FORMAT="elf32-rl78"
+# See also `include/elf/rl78.h'
+TEXT_START_ADDR=0x00000
+ARCH=rl78
+ENTRY=_start
+EMBEDDED=yes
+TEMPLATE_NAME=elf32
+ELFSIZE=32
+EXTRA_EM_FILE=needrelax
+MAXPAGESIZE=256
+# This is like setting STACK_ADDR to 0xffedc, except that the setting can
+# be overridden, e.g. --defsym _stack=0x0f00, and that we put an extra
+# sentinal value at the bottom.
+# N.B. We can't use PROVIDE to set the default value in a symbol because
+# the address is needed to place the .stack section, which in turn is needed
+# to hold the sentinel value(s).
+test -z "$CREATE_SHLIB" && OTHER_SECTIONS=" .stack ${RELOCATING-0}${RELOCATING+(DEFINED(__stack) ? __stack : 0xffedc)} :
+ {
+ ${RELOCATING+__stack = .;}
+ *(.stack)
+ LONG(0xdead)
+ }"
+# We do not need .stack for shared library.
+test -n "$CREATE_SHLIB" && OTHER_SECTIONS=""
Index: opcodes/Makefile.am
===================================================================
RCS file: /cvs/src/src/opcodes/Makefile.am,v
retrieving revision 1.164
diff -p -U5 -r1.164 Makefile.am
--- opcodes/Makefile.am 22 Aug 2011 15:25:06 -0000 1.164
+++ opcodes/Makefile.am 24 Oct 2011 22:25:24 -0000
@@ -185,10 +185,12 @@ TARGET_LIBOPCODES_CFILES = \
pdp11-opc.c \
pj-dis.c \
pj-opc.c \
ppc-dis.c \
ppc-opc.c \
+ rl78-decode.c \
+ rl78-dis.c \
rx-decode.c \
rx-dis.c \
s390-dis.c \
s390-opc.c \
score-dis.c \
@@ -462,10 +464,11 @@ MOSTLYCLEANFILES = i386-gen$(EXEEXT_FOR_
s390-mkopc$(EXEEXT_FOR_BUILD) s390-opc.tab z8kgen$(EXEEXT_FOR_BUILD) \
opc2c$(EXEEXT_FOR_BUILD)
MAINTAINERCLEANFILES = $(srcdir)/i386-tbl.h $(srcdir)/i386-init.h \
$(srcdir)/ia64-asmtab.c $(srcdir)/z8k-opc.h \
+ $(srcdir)/rl78-decode.c \
$(srcdir)/rx-decode.c
i386-gen$(EXEEXT_FOR_BUILD): i386-gen.o $(BUILD_LIB_DEPS)
$(LINK_FOR_BUILD) i386-gen.o $(BUILD_LIBS)
@@ -500,10 +503,13 @@ ia64_asmtab_deps = ia64-gen$(EXEEXT_FOR_
$(srcdir)/ia64-asmtab.c: @MAINT@ $(ia64_asmtab_deps)
./ia64-gen$(EXEEXT_FOR_BUILD) --srcdir $(srcdir) > $@
ia64-opc.lo: $(srcdir)/ia64-asmtab.c
+$(srcdir)/rl78-decode.c: @MAINT@ $(srcdir)/rl78-decode.opc opc2c$(EXEEXT_FOR_BUILD)
+ ./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/rl78-decode.opc > $(srcdir)/rl78-decode.c
+
$(srcdir)/rx-decode.c: @MAINT@ $(srcdir)/rx-decode.opc opc2c$(EXEEXT_FOR_BUILD)
./opc2c$(EXEEXT_FOR_BUILD) $(srcdir)/rx-decode.opc > $(srcdir)/rx-decode.c
opc2c$(EXEEXT_FOR_BUILD): opc2c.o $(BUILD_LIBS_DEPS)
$(LINK_FOR_BUILD) opc2c.o $(BUILD_LIBS)
Index: opcodes/configure.in
===================================================================
RCS file: /cvs/src/src/opcodes/configure.in,v
retrieving revision 1.99
diff -p -U5 -r1.99 configure.in
--- opcodes/configure.in 24 Jul 2011 14:20:13 -0000 1.99
+++ opcodes/configure.in 24 Oct 2011 22:25:26 -0000
@@ -268,10 +268,11 @@ if test x${all_targets} = xfalse ; then
bfd_powerpc_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;;
bfd_powerpc_64_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;;
bfd_pyramid_arch) ;;
bfd_romp_arch) ;;
bfd_rs6000_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;;
+ bfd_rl78_arch) ta="$ta rl78-dis.lo rl78-decode.lo";;
bfd_rx_arch) ta="$ta rx-dis.lo rx-decode.lo";;
bfd_s390_arch) ta="$ta s390-dis.lo s390-opc.lo" ;;
bfd_score_arch) ta="$ta score-dis.lo score7-dis.lo" ;;
bfd_sh_arch)
# We can't decide what we want just from the CPU family.
Index: opcodes/disassemble.c
===================================================================
RCS file: /cvs/src/src/opcodes/disassemble.c,v
retrieving revision 1.80
diff -p -U5 -r1.80 disassemble.c
--- opcodes/disassemble.c 22 Jul 2011 20:22:38 -0000 1.80
+++ opcodes/disassemble.c 24 Oct 2011 22:25:26 -0000
@@ -68,10 +68,11 @@
#define ARCH_or32
#define ARCH_pdp11
#define ARCH_pj
#define ARCH_powerpc
#define ARCH_rs6000
+#define ARCH_rl78
#define ARCH_rx
#define ARCH_s390
#define ARCH_score
#define ARCH_sh
#define ARCH_sparc
@@ -347,10 +348,15 @@ disassembler (abfd)
disassemble = print_insn_big_powerpc;
else
disassemble = print_insn_rs6000;
break;
#endif
+#ifdef ARCH_rl78
+ case bfd_arch_rl78:
+ disassemble = print_insn_rl78;
+ break;
+#endif
#ifdef ARCH_rx
case bfd_arch_rx:
disassemble = print_insn_rx;
break;
#endif
Index: opcodes/rl78-decode.opc
===================================================================
RCS file: opcodes/rl78-decode.opc
diff -N opcodes/rl78-decode.opc
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ opcodes/rl78-decode.opc 24 Oct 2011 22:25:26 -0000
@@ -0,0 +1,1263 @@
+/* -*- c -*- */
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "config.h"
+#include "ansidecl.h"
+#include "opcode/rl78.h"
+
+static int trace = 0;
+
+typedef struct
+{
+ RL78_Opcode_Decoded * rl78;
+ int (* getbyte)(void *);
+ void * ptr;
+ unsigned char * op;
+} LocalData;
+
+#define ID(x) rl78->id = RLO_##x, rl78->lineno = __LINE__
+#define OP(n,t,r,a) (rl78->op[n].type = t, \
+ rl78->op[n].reg = r, \
+ rl78->op[n].addend = a )
+#define OPX(n,t,r1,r2,a) \
+ (rl78->op[n].type = t, \
+ rl78->op[n].reg = r1, \
+ rl78->op[n].reg2 = r2, \
+ rl78->op[n].addend = a )
+
+#define W() rl78->size = RL78_Word
+
+#define AU ATTRIBUTE_UNUSED
+#define GETBYTE() (ld->op [ld->rl78->n_bytes++] = ld->getbyte (ld->ptr))
+#define B ((unsigned long) GETBYTE())
+
+#define SYNTAX(x) rl78->syntax = x
+
+#define UNSUPPORTED() \
+ rl78->syntax = "*unknown*"
+
+#define RB(x) ((x)+RL78_Reg_X)
+#define RW(x) ((x)+RL78_Reg_AX)
+
+#define Fz rl78->flags = RL78_PSW_Z
+#define Fza rl78->flags = RL78_PSW_Z | RL78_PSW_AC
+#define Fzc rl78->flags = RL78_PSW_Z | RL78_PSW_CY
+#define Fzac rl78->flags = RL78_PSW_Z | RL78_PSW_AC | RL78_PSW_CY
+#define Fa rl78->flags = RL78_PSW_AC
+#define Fc rl78->flags = RL78_PSW_CY
+#define Fac rl78->flags = RL78_PSW_AC | RL78_PSW_CY
+
+#define IMMU(bytes) immediate (bytes, 0, ld)
+#define IMMS(bytes) immediate (bytes, 1, ld)
+
+static int
+immediate (int bytes, int sign_extend, LocalData * ld)
+{
+ unsigned long i = 0;
+
+ switch (bytes)
+ {
+ case 1:
+ i |= B;
+ if (sign_extend && (i & 0x80))
+ i -= 0x100;
+ break;
+ case 2:
+ i |= B;
+ i |= B << 8;
+ if (sign_extend && (i & 0x8000))
+ i -= 0x10000;
+ break;
+ case 3:
+ i |= B;
+ i |= B << 8;
+ i |= B << 16;
+ if (sign_extend && (i & 0x800000))
+ i -= 0x1000000;
+ break;
+ default:
+ fprintf (stderr, "Programmer error: immediate() called with invalid byte count %d\n", bytes);
+ abort();
+ }
+ return i;
+}
+
+#define DC(c) OP (0, RL78_Operand_Immediate, 0, c)
+#define DR(r) OP (0, RL78_Operand_Register, RL78_Reg_##r, 0)
+#define DRB(r) OP (0, RL78_Operand_Register, RB(r), 0)
+#define DRW(r) OP (0, RL78_Operand_Register, RW(r), 0)
+#define DM(r,a) OP (0, RL78_Operand_Indirect, RL78_Reg_##r, a)
+#define DM2(r1,r2,a) OPX (0, RL78_Operand_Indirect, RL78_Reg_##r1, RL78_Reg_##r2, a)
+#define DE() rl78->op[0].use_es = 1
+#define DB(b) set_bit (rl78->op, b)
+#define DCY() DR(PSW); DB(0)
+#define DPUSH() OP (0, RL78_Operand_PreDec, RL78_Reg_SP, 0);
+
+#define SC(c) OP (1, RL78_Operand_Immediate, 0, c)
+#define SR(r) OP (1, RL78_Operand_Register, RL78_Reg_##r, 0)
+#define SRB(r) OP (1, RL78_Operand_Register, RB(r), 0)
+#define SRW(r) OP (1, RL78_Operand_Register, RW(r), 0)
+#define SM(r,a) OP (1, RL78_Operand_Indirect, RL78_Reg_##r, a)
+#define SM2(r1,r2,a) OPX (1, RL78_Operand_Indirect, RL78_Reg_##r1, RL78_Reg_##r2, a)
+#define SE() rl78->op[1].use_es = 1
+#define SB(b) set_bit (rl78->op+1, b)
+#define SCY() SR(PSW); SB(0)
+#define COND(c) rl78->op[1].condition = RL78_Condition_##c
+#define SPOP() OP (1, RL78_Operand_PostInc, RL78_Reg_SP, 0);
+
+static void
+set_bit (RL78_Opcode_Operand *op, int bit)
+{
+ op->bit_number = bit;
+ switch (op->type) {
+ case RL78_Operand_Register:
+ op->type = RL78_Operand_Bit;
+ break;
+ case RL78_Operand_Indirect:
+ op->type = RL78_Operand_BitIndirect;
+ break;
+ default:
+ break;
+ }
+}
+
+static int
+saddr (int x)
+{
+ if (x < 0x20)
+ return 0xfff00 + x;
+ return 0xffe00 + x;
+}
+
+static int
+sfr (int x)
+{
+ return 0xfff00 + x;
+}
+
+#define SADDR saddr (IMMU (1))
+#define SFR sfr (IMMU (1))
+
+int
+rl78_decode_opcode (unsigned long pc AU,
+ RL78_Opcode_Decoded * rl78,
+ int (* getbyte)(void *),
+ void * ptr)
+{
+ LocalData lds, * ld = &lds;
+ unsigned char op_buf[20] = {0};
+ unsigned char *op = op_buf;
+ int op0, op1;
+
+ lds.rl78 = rl78;
+ lds.getbyte = getbyte;
+ lds.ptr = ptr;
+ lds.op = op;
+
+ memset (rl78, 0, sizeof (*rl78));
+
+ start_again:
+
+/* Byte registers, not including A. */
+/** VARY rba 000 010 011 100 101 110 111 */
+/* Word registers, not including AX. */
+/** VARY ra 01 10 11 */
+
+/*----------------------------------------------------------------------*/
+/* ES: prefix */
+
+/** 0001 0001 es: */
+ DE(); SE();
+ op ++;
+ pc ++;
+ goto start_again;
+
+/*----------------------------------------------------------------------*/
+
+/** 0000 1111 add %0, %e1%!1 */
+ ID(add); DR(A); SM(None, IMMU(2)); Fzac;
+
+/** 0000 1101 add %0, %e1%1 */
+ ID(add); DR(A); SM(HL, 0); Fzac;
+
+/** 0110 0001 1000 000 add %0, %e1%1 */
+ ID(add); DR(A); SM2(HL, B, 0); Fzac;
+
+/** 0000 1110 add %0, %e1%1 */
+ ID(add); DR(A); SM(HL, IMMU(1)); Fzac;
+
+/** 0110 0001 1000 0010 add %0, %e1%1 */
+ ID(add); DR(A); SM2(HL, C, 0); Fzac;
+
+/** 0000 1100 add %0, #%1 */
+ ID(add); DR(A); SC(IMMU(1)); Fzac;
+
+/** 0110 0001 0000 1rba add %0, %1 */
+ ID(add); DR(A); SRB(rba); Fzac;
+
+/** 0000 1011 add %0, %1 */
+ ID(add); DR(A); SM(None, SADDR); Fzac;
+
+/** 0110 0001 0000 0reg add %0, %1 */
+ ID(add); DRB(reg); SR(A); Fzac;
+
+/** 0000 1010 add %0, #%1 */
+ ID(add); DM(None, SADDR); SC(IMMU(1)); Fzac;
+
+/*----------------------------------------------------------------------*/
+
+/** 0001 1111 addc %0, %e1%!1 */
+ ID(addc); DR(A); SM(None, IMMU(2)); Fzac;
+
+/** 0001 1101 addc %0, %e1%1 */
+ ID(addc); DR(A); SM(HL, 0); Fzac;
+
+/** 0110 0001 1001 0000 addc %0, %e1%1 */
+ ID(addc); DR(A); SM2(HL, B, 0); Fzac;
+
+/** 0110 0001 1001 0010 addc %0, %e1%1 */
+ ID(addc); DR(A); SM2(HL, C, 0); Fzac;
+
+/** 0001 1110 addc %0, %e1%1 */
+ ID(addc); DR(A); SM(HL, IMMU(1)); Fzac;
+
+/** 0001 1100 addc %0, #%1 */
+ ID(addc); DR(A); SC(IMMU(1)); Fzac;
+
+/** 0110 0001 0001 1rba addc %0, %1 */
+ ID(addc); DR(A); SRB(rba); Fzac;
+
+/** 0110 0001 0001 0reg addc %0, %1 */
+ ID(addc); DRB(reg); SR(A); Fzac;
+
+/** 0001 1011 addc %0, %1 */
+ ID(addc); DR(A); SM(None, SADDR); Fzac;
+
+/** 0001 1010 addc %0, #%1 */
+ ID(addc); DM(None, SADDR); SC(IMMU(1)); Fzac;
+
+/*----------------------------------------------------------------------*/
+
+/** 0000 0010 addw %0, %e1%!1 */
+ ID(add); W(); DR(AX); SM(None, IMMU(2)); Fzac;
+
+/** 0110 0001 0000 1001 addw %0, %e1%1 */
+ ID(add); W(); DR(AX); SM(HL, IMMU(1)); Fzac;
+
+/** 0000 0100 addw %0, #%1 */
+ ID(add); W(); DR(AX); SC(IMMU(2)); Fzac;
+
+/** 0000 0rw1 addw %0, %1 */
+ ID(add); W(); DR(AX); SRW(rw); Fzac;
+
+/** 0000 0110 addw %0, %1 */
+ ID(add); W(); DR(AX); SM(None, SADDR); Fzac;
+
+/** 0001 0000 addw %0, #%1 */
+ ID(add); W(); DR(SP); SC(IMMU(1)); Fzac;
+
+/*----------------------------------------------------------------------*/
+
+/** 0101 1111 and %0, %e1%!1 */
+ ID(and); DR(A); SM(None, IMMU(2)); Fz;
+
+/** 0101 1101 and %0, %e1%1 */
+ ID(and); DR(A); SM(HL, 0); Fz;
+
+/** 0110 0001 1101 0000 and %0, %e1%1 */
+ ID(and); DR(A); SM2(HL, B, 0); Fz;
+
+/** 0101 1110 and %0, %e1%1 */
+ ID(and); DR(A); SM(HL, IMMU(1)); Fz;
+
+/** 0110 0001 1101 0010 and %0, %e1%1 */
+ ID(and); DR(A); SM2(HL, C, 0); Fz;
+
+/** 0101 1100 and %0, #%1 */
+ ID(and); DR(A); SC(IMMU(1)); Fz;
+
+/** 0110 0001 0101 1rba and %0, %1 */
+ ID(and); DR(A); SRB(rba); Fz;
+
+/** 0110 0001 0101 0reg and %0, %1 */
+ ID(and); DRB(reg); SR(A); Fz;
+
+/** 0101 1011 and %0, %1 */
+ ID(and); DR(A); SM(None, SADDR); Fz;
+
+/** 0101 1010 and %0, #%1 */
+ ID(and); DM(None, SADDR); SC(IMMU(1)); Fz;
+
+/*----------------------------------------------------------------------*/
+
+/** 0111 0001 1bit 0101 and1 cy, %e1%1 */
+ ID(and); DCY(); SM(HL, 0); SB(bit);
+
+/** 0111 0001 1bit 1101 and1 cy, %1 */
+ ID(and); DCY(); SR(A); SB(bit);
+
+/** 0111 0001 0bit 1101 and1 cy, %s1 */
+ ID(and); DCY(); SM(None, SFR); SB(bit);
+
+/** 0111 0001 0bit 0101 and1 cy, %s1 */
+ ID(and); DCY(); SM(None, SADDR); SB(bit);
+
+/*----------------------------------------------------------------------*/
+
+/* Note that the branch insns need to be listed before the shift
+ ones, as "shift count of zero" means "branch insn" */
+
+/** 1101 1100 bc $%a0 */
+ ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(C);
+
+/** 1101 1110 bnc $%a0 */
+ ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(NC);
+
+/** 0110 0001 1100 0011 bh $%a0 */
+ ID(branch_cond); DC(pc+IMMS(1)+3); SR(None); COND(H);
+
+/** 0110 0001 1101 0011 bnh $%a0 */
+ ID(branch_cond); DC(pc+IMMS(1)+3); SR(None); COND(NH);
+
+/** 1101 1101 bz $%a0 */
+ ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(Z);
+
+/** 1101 1111 bnz $%a0 */
+ ID(branch_cond); DC(pc+IMMS(1)+2); SR(None); COND(NZ);
+
+/*----------------------------------------------------------------------*/
+
+/** 0011 0001 1bit 0101 bf %e1%1, $%a0 */
+ ID(branch_cond); DC(pc+IMMS(1)+3); SM(HL,0); SB(bit); COND(F);
+
+/** 0011 0001 0bit 0101 bf %1, $%a0 */
+ ID(branch_cond); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(F);
+
+/** 0011 0001 1bit 0100 bf %s1, $%a0 */
+ ID(branch_cond); SM(None, SFR); SB(bit); DC(pc+IMMS(1)+4); COND(F);
+
+/** 0011 0001 0bit 0100 bf %s1, $%a0 */
+ ID(branch_cond); SM(None, SADDR); SB(bit); DC(pc+IMMS(1)+4); COND(F);
+
+/*----------------------------------------------------------------------*/
+
+/** 1110 1100 br !%!a0 */
+ ID(branch); DC(IMMU(3));
+
+/** 1110 1101 br %!a0 */
+ ID(branch); DC(IMMU(2));
+
+/** 1110 1110 br $%!a0 */
+ ID(branch); DC(pc+IMMS(2)+3);
+
+/** 1110 1111 br $%a0 */
+ ID(branch); DC(pc+IMMS(1)+2);
+
+/** 0110 0001 1100 1011 br ax */
+ ID(branch); DR(AX);
+
+/*----------------------------------------------------------------------*/
+
+/** 1111 1111 brk1 */
+ ID(break);
+
+/** 0110 0001 1100 1100 brk */
+ ID(break);
+
+/*----------------------------------------------------------------------*/
+
+/** 0011 0001 1bit 0011 bt %e1%1, $%a0 */
+ ID(branch_cond); DC(pc+IMMS(1)+3); SM(HL,0); SB(bit); COND(T);
+
+/** 0011 0001 0bit 0011 bt %1, $%a0 */
+ ID(branch_cond); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(T);
+
+/** 0011 0001 1bit 0010 bt %s1, $%a0 */
+ ID(branch_cond); SM(None, SFR); SB(bit); DC(pc+IMMS(1)+4); COND(T);
+
+/** 0011 0001 0bit 0010 bt %s1, $%a0 */
+ ID(branch_cond); SM(None, SADDR); SB(bit); DC(pc+IMMS(1)+4); COND(T);
+
+/*----------------------------------------------------------------------*/
+
+/** 0011 0001 1bit 0001 btclr %e1%1, $%a0 */
+ ID(branch_cond_clear); DC(pc+IMMS(1)+3); SM(HL,0); SB(bit); COND(T);
+
+/** 0011 0001 0bit 0001 btclr %1, $%a0 */
+ ID(branch_cond_clear); DC(pc+IMMS(1)+3); SR(A); SB(bit); COND(T);
+
+/** 0011 0001 1bit 0000 btclr %s1, $%a0 */
+ ID(branch_cond_clear); SM(None, SFR); SB(bit); DC(pc+IMMS(1)+4); COND(T);
+
+/** 0011 0001 0bit 0000 btclr %s1, $%a0 */
+ ID(branch_cond_clear); SM(None, SADDR); SB(bit); DC(pc+IMMS(1)+4); COND(T);
+
+/*----------------------------------------------------------------------*/
+
+/** 1111 1100 call !%!a0 */
+ ID(call); DC(IMMU(3));
+
+/** 1111 1101 call %!a0 */
+ ID(call); DC(IMMU(2));
+
+/** 1111 1110 call $%!a0 */
+ ID(call); DC(pc+IMMS(2)+3);
+
+/** 0110 0001 11rg 1010 call %0 */
+ ID(call); DRW(rg);
+
+/** 0110 0001 1nnn 01mm callt [%x0] */
+ ID(call); DM(None, 0x80 + mm*16 + nnn*2);
+
+/*----------------------------------------------------------------------*/
+
+/** 0111 0001 0bit 1000 clr1 %e0%!0 */
+ ID(mov); DM(None, IMMU(2)); DB(bit); SC(0);
+
+/** 0111 0001 1bit 0011 clr1 %e0%0 */
+ ID(mov); DM(HL, 0); DB(bit); SC(0);
+
+/** 0111 0001 1bit 1011 clr1 %0 */
+ ID(mov); DR(A); DB(bit); SC(0);
+
+/** 0111 0001 1000 1000 clr1 cy */
+ ID(mov); DCY(); SC(0);
+
+/** 0111 0001 0bit 1011 clr1 %s0 */
+ op0 = SFR;
+ ID(mov); DM(None, op0); DB(bit); SC(0);
+ if (op0 == RL78_SFR_PSW && bit == 7)
+ rl78->syntax = "di";
+
+/** 0111 0001 0bit 0011 clr1 %0 */
+ ID(mov); DM(None, SADDR); DB(bit); SC(0);
+
+/*----------------------------------------------------------------------*/
+
+/** 1111 0101 clrb %e0%!0 */
+ ID(mov); DM(None, IMMU(2)); SC(0);
+
+/** 1111 00rg clrb %0 */
+ ID(mov); DRB(rg); SC(0);
+
+/** 1111 0100 clrb %0 */
+ ID(mov); DM(None, SADDR); SC(0);
+
+/*----------------------------------------------------------------------*/
+
+/** 1111 0110 clrw %0 */
+ ID(mov); DR(AX); SC(0);
+
+/** 1111 0111 clrw %0 */
+ ID(mov); DR(BC); SC(0);
+
+/*----------------------------------------------------------------------*/
+
+/** 0100 0000 cmp %e0%!0, #%1 */
+ ID(cmp); DM(None, IMMU(2)); SC(IMMU(1)); Fzac;
+
+/** 0100 1010 cmp %0, #%1 */
+ ID(cmp); DM(None, SADDR); SC(IMMU(1)); Fzac;
+
+/** 0100 1111 cmp %0, %e1%!1 */
+ ID(cmp); DR(A); SM(None, IMMU(2)); Fzac;
+
+/** 0100 1101 cmp %0, %e1%1 */
+ ID(cmp); DR(A); SM(HL, 0); Fzac;
+
+/** 0110 0001 1100 0000 cmp %0, %e1%1 */
+ ID(cmp); DR(A); SM2(HL, B, 0); Fzac;
+
+/** 0110 0001 1100 0010 cmp %0, %e1%1 */
+ ID(cmp); DR(A); SM2(HL, C, 0); Fzac;
+
+/** 0100 1110 cmp %0, %e1%1 */
+ ID(cmp); DR(A); SM(HL, IMMU(1)); Fzac;
+
+/** 0100 1100 cmp %0, #%1 */
+ ID(cmp); DR(A); SC(IMMU(1)); Fzac;
+
+/** 0110 0001 0100 1rba cmp %0, %1 */
+ ID(cmp); DR(A); SRB(rba); Fzac;
+
+/** 0110 0001 0100 0reg cmp %0, %1 */
+ ID(cmp); DRB(reg); SR(A); Fzac;
+
+/** 0100 1011 cmp %0, %1 */
+ ID(cmp); DR(A); SM(None, SADDR); Fzac;
+
+/*----------------------------------------------------------------------*/
+
+/** 1101 0101 cmp0 %e0%!0 */
+ ID(cmp); DM(None, IMMU(2)); SC(0); Fzac;
+
+/** 1101 00rg cmp0 %0 */
+ ID(cmp); DRB(rg); SC(0); Fzac;
+
+/** 1101 0100 cmp0 %0 */
+ ID(cmp); DM(None, SADDR); SC(0); Fzac;
+
+/*----------------------------------------------------------------------*/
+
+/** 0110 0001 1101 1110 cmps %0, %e1%1 */
+ ID(cmp); DR(X); SM(HL, IMMU(1)); Fzac;
+
+/*----------------------------------------------------------------------*/
+
+/** 0100 0010 cmpw %0, %e1%!1 */
+ ID(cmp); W(); DR(AX); SM(None, IMMU(2)); Fzac;
+
+/** 0110 0001 0100 1001 cmpw %0, %e1%1 */
+ ID(cmp); W(); DR(AX); SM(HL, IMMU(1)); Fzac;
+
+/** 0100 0100 cmpw %0, #%1 */
+ ID(cmp); W(); DR(AX); SC(IMMU(2)); Fzac;
+
+/** 0100 0ra1 cmpw %0, %1 */
+ ID(cmp); W(); DR(AX); SRW(ra); Fzac;
+
+/** 0100 0110 cmpw %0, %1 */
+ ID(cmp); W(); DR(AX); SM(None, SADDR); Fzac;
+
+/*----------------------------------------------------------------------*/
+
+/** 1011 0000 dec %e0%!0 */
+ ID(sub); DM(None, IMMU(2)); SC(1); Fza;
+
+/** 0110 0001 0110 1001 dec %e0%0 */
+ ID(sub); DM(HL, IMMU(1)); SC(1); Fza;
+
+/** 1001 0reg dec %0 */
+ ID(sub); DRB(reg); SC(1); Fza;
+
+/** 1011 0100 dec %0 */
+ ID(sub); DM(None, SADDR); SC(1); Fza;
+
+/*----------------------------------------------------------------------*/
+
+/** 1011 0010 decw %e0%!0 */
+ ID(sub); W(); DM(None, IMMU(2)); SC(1);
+
+/** 0110 0001 1000 1001 decw %e0%0 */
+ ID(sub); W(); DM(HL, IMMU(1)); SC(1);
+
+/** 1011 0rg1 decw %0 */
+ ID(sub); W(); DRW(rg); SC(1);
+
+/** 1011 0110 decw %0 */
+ ID(sub); W(); DM(None, SADDR); SC(1);
+
+/*----------------------------------------------------------------------*/
+
+/** 0110 0001 1110 1101 halt */
+ ID(halt);
+
+/*----------------------------------------------------------------------*/
+
+/** 1010 0000 inc %e0%!0 */
+ ID(add); DM(None, IMMU(2)); SC(1); Fza;
+
+/** 0110 0001 0101 1001 inc %e0%0 */
+ ID(add); DM(HL, IMMU(1)); SC(1); Fza;
+
+/** 1000 0reg inc %0 */
+ ID(add); DRB(reg); SC(1); Fza;
+
+/** 1010 0100 inc %0 */
+ ID(add); DM(None, SADDR); SC(1); Fza;
+
+/*----------------------------------------------------------------------*/
+
+/** 1010 0010 incw %e0%!0 */
+ ID(add); W(); DM(None, IMMU(2)); SC(1);
+
+/** 0110 0001 0111 1001 incw %e0%0 */
+ ID(add); W(); DM(HL, IMMU(1)); SC(1);
+
+/** 1010 0rg1 incw %0 */
+ ID(add); W(); DRW(rg); SC(1);
+
+/** 1010 0110 incw %0 */
+ ID(add); W(); DM(None, SADDR); SC(1);
+
+/*----------------------------------------------------------------------*/
+
+/** 1100 1111 mov %e0%!0, #%1 */
+ ID(mov); DM(None, IMMU(2)); SC(IMMU(1));
+
+/** 1001 1111 mov %e0%!0, %1 */
+ ID(mov); DM(None, IMMU(2)); SR(A);
+
+/** 1001 1001 mov %e0%0,%1 */
+ ID(mov); DM(DE, 0); SR(A);
+
+/** 1100 1010 mov %e0%0, #%1 */
+ ID(mov); DM(DE, IMMU(1)); SC(IMMU(1));
+
+/** 1001 1010 mov %e0%0, %1 */
+ ID(mov); DM(DE, IMMU(1)); SR(A);
+
+/** 1001 1011 mov %e0%0,%1 */
+ ID(mov); DM(HL, 0); SR(A);
+
+/** 0110 0001 1101 1001 mov %e0%0, %1 */
+ ID(mov); DM2(HL, B, 0); SR(A);
+
+/** 1100 1100 mov %e0%0, #%1 */
+ ID(mov); DM(HL, IMMU(1)); SC(IMMU(1));
+
+/** 1001 1100 mov %e0%0, %1 */
+ ID(mov); DM(HL, IMMU(1)); SR(A);
+
+/** 0110 0001 1111 1001 mov %e0%0, %1 */
+ ID(mov); DM2(HL, C, 0); SR(A);
+
+/** 1100 1000 mov %0, #%1 */
+ ID(mov); DM(SP, IMMU(1)); SC(IMMU(1));
+
+/** 1001 1000 mov %0, %1 */
+ ID(mov); DM(SP, IMMU(1)); SR(A);
+
+/** 1000 1111 mov %0, %e1%!1 */
+ ID(mov); DR(A); SM(None, IMMU(2));
+
+/** 1000 1001 mov %0, %e1%1 */
+ ID(mov); DR(A); SM(DE, 0);
+
+/** 1000 1010 mov %0, %e1%1 */
+ ID(mov); DR(A); SM(DE, IMMU(1));
+
+/** 1000 1011 mov %0, %e1%1 */
+ ID(mov); DR(A); SM(HL, 0);
+
+/** 1000 1100 mov %0, %e1%1 */
+ ID(mov); DR(A); SM(HL, IMMU(1));
+
+/** 0110 0001 1100 1001 mov %0, %e1%1 */
+ ID(mov); DR(A); SM2(HL, B, 0);
+
+/** 0110 0001 1110 1001 mov %0, %e1%1 */
+ ID(mov); DR(A); SM2(HL, C, 0);
+
+/** 1000 1000 mov %0, %e1%1 */
+ ID(mov); DR(A); SM(SP, IMMU(1));
+
+/** 0101 0reg mov %0, #%1 */
+ ID(mov); DRB(reg); SC(IMMU(1));
+
+/** 0110 0rba mov %0, %1 */
+ ID(mov); DR(A); SRB(rba);
+
+/** 1000 1110 1111 1101 mov %0, %1 */
+ ID(mov); DR(A); SR(ES);
+
+/** 0000 1001 mov %0, %e1%1 */
+ ID(mov); DR(A); SM(B, IMMU(2));
+
+/** 0100 1001 mov %0, %e1%1 */
+ ID(mov); DR(A); SM(BC, IMMU(2));
+
+/** 0010 1001 mov %0, %e1%1 */
+ ID(mov); DR(A); SM(C, IMMU(2));
+
+/** 1000 1110 mov %0, %s1 */
+ ID(mov); DR(A); SM(None, SFR);
+
+/** 1000 1101 mov %0, %1 */
+ ID(mov); DR(A); SM(None, SADDR);
+
+/** 1110 1001 mov %0, %e1%!1 */
+ ID(mov); DR(B); SM(None, IMMU(2));
+
+/** 0111 0rba mov %0, %1 */
+ ID(mov); DRB(rba); SR(A);
+
+/** 1110 1000 mov %0, %1 */
+ ID(mov); DR(B); SM(None, SADDR);
+
+/** 1111 1001 mov %0, %e1%!1 */
+ ID(mov); DR(C); SM(None, IMMU(2));
+
+/** 1111 1000 mov %0, %1 */
+ ID(mov); DR(C); SM(None, SADDR);
+
+/** 1101 1001 mov %0, %e1%!1 */
+ ID(mov); DR(X); SM(None, IMMU(2));
+
+/** 1101 1000 mov %0, %1 */
+ ID(mov); DR(X); SM(None, SADDR);
+
+/** 1001 1110 1111 1100 mov %0, %1 */
+ ID(mov); DR(CS); SR(A);
+
+/** 0100 0001 mov %0, #%1 */
+ ID(mov); DR(ES); SC(IMMU(1));
+
+/** 1001 1110 1111 1101 mov %0, %1 */
+ ID(mov); DR(ES); SR(A);
+
+/** 0110 0001 1011 1000 mov %0, %1 */
+ ID(mov); DR(ES); SM(None, SADDR);
+
+/** 0001 1001 mov %e0%0, #%1 */
+ ID(mov); DM(B, IMMU(2)); SC(IMMU(1));
+
+/** 0001 1000 mov %e0%0, %1 */
+ ID(mov); DM(B, IMMU(2)); SR(A);
+
+/** 0011 1001 mov %e0%0, #%1 */
+ ID(mov); DM(BC, IMMU(2)); SC(IMMU(1));
+
+/** 0100 1000 mov %e0%0, %1 */
+ ID(mov); DM(BC, IMMU(2)); SR(A);
+
+/** 0011 1000 mov %e0%0, #%1 */
+ ID(mov); DM(C, IMMU(2)); SC(IMMU(1));
+
+/** 0010 1000 mov %e0%0, %1 */
+ ID(mov); DM(C, IMMU(2)); SR(A);
+
+/** 1100 1101 mov %0, #%1 */
+ ID(mov); DM(None, SADDR); SC(IMMU(1));
+
+/** 1001 1101 mov %0, %1 */
+ ID(mov); DM(None, SADDR); SR(A);
+
+/** 1100 1110 mov %s0, #%1 */
+ op0 = SFR;
+ op1 = IMMU(1);
+ ID(mov); DM(None, op0); SC(op1);
+ if (op0 == 0xffffb)
+ switch (op1)
+ {
+ case 0x01:
+ rl78->syntax = "mulhu"; ID(mulhu);
+ break;
+ case 0x02:
+ rl78->syntax = "mulh"; ID(mulh);
+ break;
+ case 0x03:
+ rl78->syntax = "divhu"; ID(divhu);
+ break;
+ case 0x04:
+ rl78->syntax = "divwu"; ID(divwu);
+ break;
+ case 0x05:
+ rl78->syntax = "machu"; ID(machu);
+ break;
+ case 0x06:
+ rl78->syntax = "mach"; ID(mach);
+ break;
+ }
+
+/** 1001 1110 mov %0, %1 */
+ ID(mov); DM(None, SFR); SR(A);
+
+/*----------------------------------------------------------------------*/
+
+/** 0111 0001 1bit 0001 mov1 %e0%0, cy */
+ ID(mov); DM(HL, 0); DB(bit); SCY();
+
+/** 0111 0001 1bit 1001 mov1 %e0%0, cy */
+ ID(mov); DR(A); DB(bit); SCY();
+
+/** 0111 0001 1bit 0100 mov1 cy, %e1%1 */
+ ID(mov); DCY(); SM(HL, 0); SB(bit);
+
+/** 0111 0001 1bit 1100 mov1 cy, %e1%1 */
+ ID(mov); DCY(); SR(A); SB(bit);
+
+/** 0111 0001 0bit 0100 mov1 cy, %1 */
+ ID(mov); DCY(); SM(None, SADDR); SB(bit);
+
+/** 0111 0001 0bit 1100 mov1 cy, %s1 */
+ ID(mov); DCY(); SM(None, SFR); SB(bit);
+
+/** 0111 0001 0bit 0001 mov1 %0, cy */
+ ID(mov); DM(None, SADDR); DB(bit); SCY();
+
+/** 0111 0001 0bit 1001 mov1 %s0, cy */
+ ID(mov); DM(None, SFR); DB(bit); SCY();
+
+/*----------------------------------------------------------------------*/
+
+/** 0110 0001 1100 1110 movs %e0%0, %1 */
+ ID(mov); DM(HL, IMMU(1)); SR(X); Fzc;
+
+/*----------------------------------------------------------------------*/
+
+/** 1011 1111 movw %e0%!0, %1 */
+ ID(mov); W(); DM(None, IMMU(2)); SR(AX);
+
+/** 1011 1001 movw %e0%0, %1 */
+ ID(mov); W(); DM(DE, 0); SR(AX);
+
+/** 1011 1010 movw %e0%0, %1 */
+ ID(mov); W(); DM(DE, IMMU(1)); SR(AX);
+
+/** 1011 1011 movw %e0%0, %1 */
+ ID(mov); W(); DM(HL, 0); SR(AX);
+
+/** 1011 1100 movw %e0%0, %1 */
+ ID(mov); W(); DM(HL, IMMU(1)); SR(AX);
+
+/** 1011 1000 movw %0, %1 */
+ ID(mov); W(); DM(SP, IMMU(1)); SR(AX);
+
+/** 1010 1111 movw %0, %e1%!1 */
+ ID(mov); W(); DR(AX); SM(None, IMMU(2));
+
+
+/** 1010 1001 movw %0, %e1%1 */
+ ID(mov); W(); DR(AX); SM(DE, 0);
+
+/** 1010 1010 movw %0, %e1%1 */
+ ID(mov); W(); DR(AX); SM(DE, IMMU(1));
+
+/** 1010 1011 movw %0, %e1%1 */
+ ID(mov); W(); DR(AX); SM(HL, 0);
+
+/** 1010 1100 movw %0, %e1%1 */
+ ID(mov); W(); DR(AX); SM(HL, IMMU(1));
+
+/** 1010 1000 movw %0, %1 */
+ ID(mov); W(); DR(AX); SM(SP, IMMU(1));
+
+/** 0011 0rg0 movw %0, #%1 */
+ ID(mov); W(); DRW(rg); SC(IMMU(2));
+
+/** 0001 0ra1 movw %0, %1 */
+ ID(mov); W(); DR(AX); SRW(ra);
+
+/** 0001 0ra0 movw %0, %1 */
+ ID(mov); W(); DRW(ra); SR(AX);
+
+/** 0101 1001 movw %0, %e1%1 */
+ ID(mov); W(); DR(AX); SM(B, IMMU(2));
+
+/** 0110 1001 movw %0, %e1%1 */
+ ID(mov); W(); DR(AX); SM(C, IMMU(2));
+
+/** 0111 1001 movw %0, %e1%1 */
+ ID(mov); W(); DR(AX); SM(BC, IMMU(2));
+
+/** 0101 1000 movw %e0%0, %1 */
+ ID(mov); W(); DM(B, IMMU(2)); SR(AX);
+
+/** 0110 1000 movw %e0%0, %1 */
+ ID(mov); W(); DM(C, IMMU(2)); SR(AX);
+
+/** 0111 1000 movw %e0%0, %1 */
+ ID(mov); W(); DM(BC, IMMU(2)); SR(AX);
+
+/** 1010 1101 movw %0, %1 */
+ ID(mov); W(); DR(AX); SM(None, SADDR);
+
+/** 1010 1110 movw %0, %s1 */
+ ID(mov); W(); DR(AX); SM(None, SFR);
+
+/** 11ra 1011 movw %0, %e1%!1 */
+ ID(mov); W(); DRW(ra); SM(None, IMMU(2));
+
+/** 11ra 1010 movw %0, %1 */
+ ID(mov); W(); DRW(ra); SM(None, SADDR);
+
+/** 1100 1001 movw %0, #%1 */
+ ID(mov); W(); DM(None, SADDR); SC(IMMU(2));
+
+/** 1011 1101 movw %0, %1 */
+ ID(mov); W(); DM(None, SADDR); SR(AX);
+
+/** 1100 1011 movw %0, #%1 */
+ ID(mov); W(); DM(None, SFR); SC(IMMU(2));
+
+/** 1011 1110 movw %0, %1 */
+ ID(mov); W(); DM(None, SFR); SR(AX);
+
+/*----------------------------------------------------------------------*/
+
+/** 1101 0110 mulu x */
+ ID(mulu);
+
+/*----------------------------------------------------------------------*/
+
+/** 0000 0000 nop */
+ ID(nop);
+
+/*----------------------------------------------------------------------*/
+
+/** 1110 0101 oneb %e0%!0 */
+ ID(mov); DM(None, IMMU(2)); SC(1);
+
+/** 1110 00rg oneb %0 */
+ ID(mov); DRB(rg); SC(1);
+
+/** 1110 0100 oneb %0 */
+ ID(mov); DM(None, SADDR); SC(1);
+
+/*----------------------------------------------------------------------*/
+
+/** 1110 0110 onew %0 */
+ ID(mov); DR(AX); SC(1);
+
+/** 1110 0111 onew %0 */
+ ID(mov); DR(BC); SC(1);
+
+/*----------------------------------------------------------------------*/
+
+/** 0110 1111 or %0, %e1%!1 */
+ ID(or); DR(A); SM(None, IMMU(2)); Fz;
+
+/** 0110 1101 or %0, %e1%1 */
+ ID(or); DR(A); SM(HL, 0); Fz;
+
+/** 0110 0001 1110 0000 or %0, %e1%1 */
+ ID(or); DR(A); SM2(HL, B, 0); Fz;
+
+/** 0110 1110 or %0, %e1%1 */
+ ID(or); DR(A); SM(HL, IMMU(1)); Fz;
+
+/** 0110 0001 1110 0010 or %0, %e1%1 */
+ ID(or); DR(A); SM2(HL, C, 0); Fz;
+
+/** 0110 1100 or %0, #%1 */
+ ID(or); DR(A); SC(IMMU(1)); Fz;
+
+/** 0110 0001 0110 1rba or %0, %1 */
+ ID(or); DR(A); SRB(rba); Fz;
+
+/** 0110 0001 0110 0reg or %0, %1 */
+ ID(or); DRB(reg); SR(A); Fz;
+
+/** 0110 1011 or %0, %1 */
+ ID(or); DR(A); SM(None, SADDR); Fz;
+
+/** 0110 1010 or %0, #%1 */
+ ID(or); DM(None, SADDR); SC(IMMU(1)); Fz;
+
+/*----------------------------------------------------------------------*/
+
+/** 0111 0001 1bit 0110 or1 cy, %e1%1 */
+ ID(or); DCY(); SM(HL, 0); SB(bit);
+
+/** 0111 0001 1bit 1110 or1 cy, %1 */
+ ID(or); DCY(); SR(A); SB(bit);
+
+/** 0111 0001 0bit 1110 or1 cy, %s1 */
+ ID(or); DCY(); SM(None, SFR); SB(bit);
+
+/** 0111 0001 0bit 0110 or1 cy, %s1 */
+ ID(or); DCY(); SM(None, SADDR); SB(bit);
+
+/*----------------------------------------------------------------------*/
+
+/** 1100 0rg0 pop %0 */
+ ID(mov); W(); DRW(rg); SPOP();
+
+/** 0110 0001 1100 1101 pop %s0 */
+ ID(mov); W(); DR(PSW); SPOP();
+
+/*----------------------------------------------------------------------*/
+
+/** 1100 0rg1 push %1 */
+ ID(mov); W(); DPUSH(); SRW(rg);
+
+/** 0110 0001 1101 1101 push %s1 */
+ ID(mov); W(); DPUSH(); SR(PSW);
+
+/*----------------------------------------------------------------------*/
+
+/** 1101 0111 ret */
+ ID(ret);
+
+/** 0110 0001 1111 1100 reti */
+ ID(reti);
+
+/** 0110 0001 1110 1100 retb */
+ ID(reti);
+
+/*----------------------------------------------------------------------*/
+
+/** 0110 0001 1110 1011 rol %0, %1 */
+ ID(rol); DR(A); SC(1);
+
+/** 0110 0001 1101 1100 rolc %0, %1 */
+ ID(rolc); DR(A); SC(1);
+
+/** 0110 0001 111r 1110 rolwc %0, %1 */
+ ID(rolc); W(); DRW(r); SC(1);
+
+/** 0110 0001 1101 1011 ror %0, %1 */
+ ID(ror); DR(A); SC(1);
+
+/** 0110 0001 1111 1011 rorc %0, %1 */
+ ID(rorc); DR(A); SC(1);
+
+/*----------------------------------------------------------------------*/
+
+/* Note that the branch insns need to be listed before the shift
+ ones, as "shift count of zero" means "branch insn" */
+
+/** 0011 0001 0cnt 1011 sar %0, %1 */
+ ID(sar); DR(A); SC(cnt);
+
+/** 0011 0001 wcnt 1111 sarw %0, %1 */
+ ID(sar); W(); DR(AX); SC(wcnt);
+
+/*----------------------------------------------------------------------*/
+
+/** 0110 0001 11rb 1111 sel rb%1 */
+ ID(sel); SC(rb);
+
+/*----------------------------------------------------------------------*/
+
+/** 0111 0001 0bit 0000 set1 %e0%!0 */
+ ID(mov); DM(None, IMMU(2)); DB(bit); SC(1);
+
+/** 0111 0001 1bit 0010 set1 %e0%0 */
+ ID(mov); DM(HL, 0); DB(bit); SC(1);
+
+/** 0111 0001 1bit 1010 set1 %0 */
+ ID(mov); DR(A); DB(bit); SC(1);
+
+/** 0111 0001 1000 0000 set1 cy */
+ ID(mov); DCY(); SC(1);
+
+/** 0111 0001 0bit 1010 set1 %s0 */
+ op0 = SFR;
+ ID(mov); DM(None, op0); DB(bit); SC(1);
+ if (op0 == RL78_SFR_PSW && bit == 7)
+ rl78->syntax = "ei";
+
+/** 0111 0001 0bit 0010 set1 %0 */
+ ID(mov); DM(None, SADDR); DB(bit); SC(1);
+
+/*----------------------------------------------------------------------*/
+
+/** 0011 0001 0cnt 1001 shl %0, %1 */
+ ID(shl); DR(A); SC(cnt);
+
+/** 0011 0001 0cnt 1000 shl %0, %1 */
+ ID(shl); DR(B); SC(cnt);
+
+/** 0011 0001 0cnt 0111 shl %0, %1 */
+ ID(shl); DR(C); SC(cnt);
+
+/** 0011 0001 wcnt 1101 shlw %0, %1 */
+ ID(shl); W(); DR(AX); SC(wcnt);
+
+/** 0011 0001 wcnt 1100 shlw %0, %1 */
+ ID(shl); W(); DR(BC); SC(wcnt);
+
+/*----------------------------------------------------------------------*/
+
+/** 0011 0001 0cnt 1010 shr %0, %1 */
+ ID(shr); DR(A); SC(cnt);
+
+/** 0011 0001 wcnt 1110 shrw %0, %1 */
+ ID(shr); W(); DR(AX); SC(wcnt);
+
+/*----------------------------------------------------------------------*/
+
+/** 0110 0001 1100 1000 sk%c1 */
+ ID(skip); COND(C);
+
+/** 0110 0001 1110 0011 sk%c1 */
+ ID(skip); COND(H);
+
+/** 0110 0001 1101 1000 sk%c1 */
+ ID(skip); COND(NC);
+
+/** 0110 0001 1111 0011 sk%c1 */
+ ID(skip); COND(NH);
+
+/** 0110 0001 1111 1000 sk%c1 */
+ ID(skip); COND(NZ);
+
+/** 0110 0001 1110 1000 sk%c1 */
+ ID(skip); COND(Z);
+
+/*----------------------------------------------------------------------*/
+
+/** 0110 0001 1111 1101 stop */
+ ID(stop);
+
+/*----------------------------------------------------------------------*/
+
+/** 0010 1111 sub %0, %e1%!1 */
+ ID(sub); DR(A); SM(None, IMMU(2)); Fzac;
+
+/** 0010 1101 sub %0, %e1%1 */
+ ID(sub); DR(A); SM(HL, 0); Fzac;
+
+/** 0110 0001 1010 000 sub %0, %e1%1 */
+ ID(sub); DR(A); SM2(HL, B, 0); Fzac;
+
+/** 0010 1110 sub %0, %e1%1 */
+ ID(sub); DR(A); SM(HL, IMMU(1)); Fzac;
+
+/** 0110 0001 1010 0010 sub %0, %e1%1 */
+ ID(sub); DR(A); SM2(HL, C, 0); Fzac;
+
+/** 0010 1100 sub %0, #%1 */
+ ID(sub); DR(A); SC(IMMU(1)); Fzac;
+
+/** 0110 0001 0010 1rba sub %0, %1 */
+ ID(sub); DR(A); SRB(rba); Fzac;
+
+/** 0010 1011 sub %0, %1 */
+ ID(sub); DR(A); SM(None, SADDR); Fzac;
+
+/** 0110 0001 0010 0reg sub %0, %1 */
+ ID(sub); DRB(reg); SR(A); Fzac;
+
+/** 0010 1010 sub %0, #%1 */
+ ID(sub); DM(None, SADDR); SC(IMMU(1)); Fzac;
+
+/*----------------------------------------------------------------------*/
+
+/** 0011 1111 subc %0, %e1%!1 */
+ ID(subc); DR(A); SM(None, IMMU(2)); Fzac;
+
+/** 0011 1101 subc %0, %e1%1 */
+ ID(subc); DR(A); SM(HL, 0); Fzac;
+
+/** 0110 0001 1011 0000 subc %0, %e1%1 */
+ ID(subc); DR(A); SM2(HL, B, 0); Fzac;
+
+/** 0110 0001 1011 0010 subc %0, %e1%1 */
+ ID(subc); DR(A); SM2(HL, C, 0); Fzac;
+
+/** 0011 1110 subc %0, %e1%1 */
+ ID(subc); DR(A); SM(HL, IMMU(1)); Fzac;
+
+/** 0011 1100 subc %0, #%1 */
+ ID(subc); DR(A); SC(IMMU(1)); Fzac;
+
+/** 0110 0001 0011 1rba subc %0, %1 */
+ ID(subc); DR(A); SRB(rba); Fzac;
+
+/** 0110 0001 0011 0reg subc %0, %1 */
+ ID(subc); DRB(reg); SR(A); Fzac;
+
+/** 0011 1011 subc %0, %1 */
+ ID(subc); DR(A); SM(None, SADDR); Fzac;
+
+/** 0011 1010 subc %0, #%1 */
+ ID(subc); DM(None, SADDR); SC(IMMU(1)); Fzac;
+
+/*----------------------------------------------------------------------*/
+
+/** 0010 0010 subw %0, %e1%!1 */
+ ID(sub); W(); DR(AX); SM(None, IMMU(2)); Fzac;
+
+/** 0110 0001 0010 1001 subw %0, %e1%1 */
+ ID(sub); W(); DR(AX); SM(HL, IMMU(1)); Fzac;
+
+/** 0010 0100 subw %0, #%1 */
+ ID(sub); W(); DR(AX); SC(IMMU(2)); Fzac;
+
+/** 0010 0rw1 subw %0, %1 */
+ ID(sub); W(); DR(AX); SRW(rw); Fzac;
+
+/** 0010 0110 subw %0, %1 */
+ ID(sub); W(); DR(AX); SM(None, SADDR); Fzac;
+
+/** 0010 0000 subw %0, #%1 */
+ ID(sub); W(); DR(SP); SC(IMMU(1)); Fzac;
+
+/*----------------------------------------------------------------------*/
+
+/** 0110 0001 1010 1010 xch %0, %e1%!1 */
+ ID(xch); DR(A); SM(None, IMMU(2));
+
+/** 0110 0001 1010 1110 xch %0, %e1%1 */
+ ID(xch); DR(A); SM(DE, 0);
+
+/** 0110 0001 1010 1111 xch %0, %e1%1 */
+ ID(xch); DR(A); SM(DE, IMMU(1));
+
+/** 0110 0001 1010 1100 xch %0, %e1%1 */
+ ID(xch); DR(A); SM(HL, 0);
+
+/** 0110 0001 1011 1001 xch %0, %e1%1 */
+ ID(xch); DR(A); SM2(HL, B, 0);
+
+/** 0110 0001 1010 1101 xch %0, %e1%1 */
+ ID(xch); DR(A); SM(HL, IMMU(1));
+
+/** 0110 0001 1010 1001 xch %0, %e1%1 */
+ ID(xch); DR(A); SM2(HL, C, 0);
+
+/** 0110 0001 1000 1reg xch %0, %1 */
+ /* Note: DECW uses reg == X, so this must follow DECW */
+ ID(xch); DR(A); SRB(reg);
+
+/** 0110 0001 1010 1000 xch %0, %1 */
+ ID(xch); DR(A); SM(None, SADDR);
+
+/** 0110 0001 1010 1011 xch %0, %1 */
+ ID(xch); DR(A); SM(None, SFR);
+
+/** 0000 1000 xch a, x */
+ ID(xch); DR(A); SR(X);
+
+/*----------------------------------------------------------------------*/
+
+/** 0011 0ra1 xchw %0, %1 */
+ ID(xch); W(); DR(AX); SRW(ra);
+
+/*----------------------------------------------------------------------*/
+
+/** 0111 1111 xor %0, %e1%!1 */
+ ID(xor); DR(A); SM(None, IMMU(2)); Fz;
+
+/** 0111 1101 xor %0, %e1%1 */
+ ID(xor); DR(A); SM(HL, 0); Fz;
+
+/** 0110 0001 1111 0000 xor %0, %e1%1 */
+ ID(xor); DR(A); SM2(HL, B, 0); Fz;
+
+/** 0111 1110 xor %0, %e1%1 */
+ ID(xor); DR(A); SM(HL, IMMU(1)); Fz;
+
+/** 0110 0001 1111 0010 xor %0, %e1%1 */
+ ID(xor); DR(A); SM2(HL, C, 0); Fz;
+
+/** 0111 1100 xor %0, #%1 */
+ ID(xor); DR(A); SC(IMMU(1)); Fz;
+
+/** 0110 0001 0111 1rba xor %0, %1 */
+ ID(xor); DR(A); SRB(rba); Fz;
+
+/** 0110 0001 0111 0reg xor %0, %1 */
+ ID(xor); DRB(reg); SR(A); Fz;
+
+/** 0111 1011 xor %0, %1 */
+ ID(xor); DR(A); SM(None, SADDR); Fz;
+
+/** 0111 1010 xor %0, #%1 */
+ ID(xor); DM(None, SADDR); SC(IMMU(1)); Fz;
+
+/*----------------------------------------------------------------------*/
+
+/** 0111 0001 1bit 0111 xor1 cy, %e1%1 */
+ ID(xor); DCY(); SM(HL, 0); SB(bit);
+
+/** 0111 0001 1bit 1111 xor1 cy, %1 */
+ ID(xor); DCY(); SR(A); SB(bit);
+
+/** 0111 0001 0bit 1111 xor1 cy, %s1 */
+ ID(xor); DCY(); SM(None, SFR); SB(bit);
+
+/** 0111 0001 0bit 0111 xor1 cy, %s1 */
+ ID(xor); DCY(); SM(None, SADDR); SB(bit);
+
+/*----------------------------------------------------------------------*/
+
+/** */
+
+ return rl78->n_bytes;
+}
Index: opcodes/rl78-dis.c
===================================================================
RCS file: opcodes/rl78-dis.c
diff -N opcodes/rl78-dis.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ opcodes/rl78-dis.c 24 Oct 2011 22:25:26 -0000
@@ -0,0 +1,327 @@
+/* Disassembler code for Renesas RL78.
+ Copyright 2011 Free Software Foundation, Inc.
+ Contributed by Red Hat.
+ Written by DJ Delorie.
+
+ This file is part of the GNU opcodes library.
+
+ This library is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
+
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+ MA 02110-1301, USA. */
+
+#include <stdio.h>
+
+#include "bfd.h"
+#include "dis-asm.h"
+#include "opcode/rl78.h"
+
+#define DEBUG_SEMANTICS 0
+
+typedef struct
+{
+ bfd_vma pc;
+ disassemble_info * dis;
+} RL78_Data;
+
+static int
+rl78_get_byte (void * vdata)
+{
+ bfd_byte buf[1];
+ RL78_Data *rl78_data = (RL78_Data *) vdata;
+
+ rl78_data->dis->read_memory_func (rl78_data->pc,
+ buf,
+ 1,
+ rl78_data->dis);
+
+ rl78_data->pc ++;
+ return buf[0];
+}
+
+static char const *
+register_names[] =
+{
+ "",
+ "x", "a", "c", "b", "e", "d", "l", "h",
+ "ax", "bc", "de", "hl",
+ "sp", "psw", "cs", "es", "pmc", "mem"
+};
+
+static char const *
+condition_names[] =
+{
+ "t", "f", "c", "nc", "h", "nh", "z", "nz"
+};
+
+static int
+indirect_type (int t)
+{
+ switch (t)
+ {
+ case RL78_Operand_Indirect:
+ case RL78_Operand_BitIndirect:
+ case RL78_Operand_PostInc:
+ case RL78_Operand_PreDec:
+ return 1;
+ default:
+ return 0;
+ }
+}
+
+int
+print_insn_rl78 (bfd_vma addr, disassemble_info * dis)
+{
+ int rv;
+ RL78_Data rl78_data;
+ RL78_Opcode_Decoded opcode;
+ const char * s;
+#if DEBUG_SEMANTICS
+ static char buf[200];
+#endif
+
+ rl78_data.pc = addr;
+ rl78_data.dis = dis;
+
+ rv = rl78_decode_opcode (addr, &opcode, rl78_get_byte, &rl78_data);
+
+ dis->bytes_per_line = 10;
+
+#define PR (dis->fprintf_func)
+#define PS (dis->stream)
+#define PC(c) PR (PS, "%c", c)
+
+ s = opcode.syntax;
+
+#if DEBUG_SEMANTICS
+
+ switch (opcode.id)
+ {
+ case RLO_unknown: s = "uknown"; break;
+ case RLO_add: s = "add: %e0%0 += %e1%1"; break;
+ case RLO_addc: s = "addc: %e0%0 += %e1%1 + CY"; break;
+ case RLO_and: s = "and: %e0%0 &= %e1%1"; break;
+ case RLO_branch: s = "branch: pc = %e0%0"; break;
+ case RLO_branch_cond: s = "branch_cond: pc = %e0%0 if %c1 / %e1%1"; break;
+ case RLO_branch_cond_clear: s = "branch_cond_clear: pc = %e0%0 if %c1 / %e1%1, %e1%1 = 0"; break;
+ case RLO_call: s = "call: pc = %e1%0"; break;
+ case RLO_cmp: s = "cmp: %e0%0 - %e1%1"; break;
+ case RLO_mov: s = "mov: %e0%0 = %e1%1"; break;
+ case RLO_or: s = "or: %e0%0 |= %e1%1"; break;
+ case RLO_rol: s = "rol: %e0%0 <<= %e1%1"; break;
+ case RLO_rolc: s = "rol: %e0%0 <<= %e1%1,CY"; break;
+ case RLO_ror: s = "ror: %e0%0 >>= %e1%1"; break;
+ case RLO_rorc: s = "ror: %e0%0 >>= %e1%1,CY"; break;
+ case RLO_sar: s = "sar: %e0%0 >>= %e1%1 signed"; break;
+ case RLO_sel: s = "sel: rb = %1"; break;
+ case RLO_shr: s = "shr: %e0%0 >>= %e1%1 unsigned"; break;
+ case RLO_shl: s = "shl: %e0%0 <<= %e1%1"; break;
+ case RLO_skip: s = "skip: if %c1"; break;
+ case RLO_sub: s = "sub: %e0%0 -= %e1%1"; break;
+ case RLO_subc: s = "subc: %e0%0 -= %e1%1 - CY"; break;
+ case RLO_xch: s = "xch: %e0%0 <-> %e1%1"; break;
+ case RLO_xor: s = "xor: %e0%0 ^= %e1%1"; break;
+ }
+
+ sprintf(buf, "%s%%W%%f\t\033[32m%s\033[0m", s, opcode.syntax);
+ s = buf;
+
+#endif
+
+ for (; *s; s++)
+ {
+ if (*s != '%')
+ {
+ PC (*s);
+ }
+ else
+ {
+ RL78_Opcode_Operand * oper;
+ int do_hex = 0;
+ int do_addr = 0;
+ int do_es = 0;
+ int do_sfr = 0;
+ int do_cond = 0;
+ int do_bang = 0;
+
+ s ++;
+
+ if (*s == 'x')
+ {
+ do_hex = 1;
+ s++;
+ }
+ if (*s == '!')
+ {
+ do_bang = 1;
+ s++;
+ }
+ if (*s == 'e')
+ {
+ do_es = 1;
+ s++;
+ }
+ if (*s == 'a')
+ {
+ do_addr = 1;
+ s++;
+ }
+ if (*s == 's')
+ {
+ do_sfr = 1;
+ s++;
+ }
+ if (*s == 'c')
+ {
+ do_cond = 1;
+ s++;
+ }
+
+ switch (*s)
+ {
+ case '%':
+ PC ('%');
+ break;
+
+#if DEBUG_SEMANTICS
+
+ case 'W':
+ if (opcode.size == RL78_Word)
+ PR (PS, " \033[33mW\033[0m");
+ break;
+
+ case 'f':
+ if (opcode.flags)
+ {
+ char *comma = "";
+ PR (PS, " \033[35m");
+
+ if (opcode.flags & RL78_PSW_Z)
+ { PR (PS, "Z"); comma = ","; }
+ if (opcode.flags & RL78_PSW_AC)
+ { PR (PS, "%sAC", comma); comma = ","; }
+ if (opcode.flags & RL78_PSW_CY)
+ { PR (PS, "%sCY", comma); comma = ","; }
+ PR (PS, "\033[0m");
+ }
+ break;
+
+#endif
+
+ case '0':
+ case '1':
+ oper = opcode.op + *s - '0';
+ if (do_bang)
+ PC ('!');
+
+ if (do_es)
+ {
+ if (oper->use_es && indirect_type (oper->type))
+ PR (PS, "es:");
+ }
+
+ else if (do_cond)
+ {
+ PR (PS, "%s", condition_names[oper->condition]);
+ }
+
+ else
+ switch (oper->type)
+ {
+ case RL78_Operand_Immediate:
+ if (do_addr)
+ dis->print_address_func (oper->addend, dis);
+ else if (do_hex
+ || oper->addend > 999
+ || oper->addend < -999)
+ PR (PS, "%#x", oper->addend);
+ else
+ PR (PS, "%d", oper->addend);
+ break;
+
+ case RL78_Operand_Register:
+ PR (PS, "%s", register_names[oper->reg]);
+ break;
+
+ case RL78_Operand_Bit:
+ PR (PS, "%s.%d", register_names[oper->reg], oper->bit_number);
+ break;
+
+ case RL78_Operand_Indirect:
+ case RL78_Operand_BitIndirect:
+ switch (oper->reg)
+ {
+ case RL78_Reg_None:
+ if (oper->addend == 0xffffa && do_sfr && opcode.size == RL78_Byte)
+ PR (PS, "psw");
+ else if (oper->addend == 0xffff8 && do_sfr && opcode.size == RL78_Word)
+ PR (PS, "sp");
+ else if (oper->addend >= 0xffe20)
+ PR (PS, "%#x", oper->addend);
+ else
+ dis->print_address_func (oper->addend, dis);
+ break;
+
+ case RL78_Reg_B:
+ case RL78_Reg_C:
+ case RL78_Reg_BC:
+ PR (PS, "%d[%s]", oper->addend, register_names[oper->reg]);
+ break;
+
+ default:
+ PR (PS, "[%s", register_names[oper->reg]);
+ if (oper->reg2 != RL78_Reg_None)
+ PR (PS, "+%s", register_names[oper->reg2]);
+ if (oper->addend)
+ PR (PS, "+%d", oper->addend);
+ PC (']');
+ break;
+
+ }
+ if (oper->type == RL78_Operand_BitIndirect)
+ PR (PS, ".%d", oper->bit_number);
+ break;
+
+#if DEBUG_SEMANTICS
+ /* Shouldn't happen - push and pop don't print
+ [SP] directly. But we *do* use them for
+ semantic debugging. */
+ case RL78_Operand_PostInc:
+ PR (PS, "[%s++]", register_names[oper->reg]);
+ break;
+ case RL78_Operand_PreDec:
+ PR (PS, "[--%s]", register_names[oper->reg]);
+ break;
+#endif
+
+ default:
+ /* If we ever print this, that means the
+ programmer tried to print an operand with a
+ type we don't expect. Print the line and
+ operand number from rl78-decode.opc for
+ them. */
+ PR (PS, "???%d.%d", opcode.lineno, *s - '0');
+ break;
+ }
+ }
+ }
+ }
+
+#if DEBUG_SEMANTICS
+
+ PR (PS, "\t\033[34m(line %d)\033[0m", opcode.lineno);
+
+#endif
+
+ return rv;
+}