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Commit: V850: Fix encoding of CMPF.S and CMPF.D instructions


Hi Guys,

  I am checking in the patch below to fix the encoding of the CMPF.S and
  CMPF.D instructions in the V850 port.

Cheers
  Nick

opcodes/ChangeLog
2011-05-19  Nick Clifton  <nickc@redhat.com>

	* v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
	operands.

Index: opcodes/v850-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/v850-opc.c,v
retrieving revision 1.12
diff -u -3 -p -r1.12 v850-opc.c
--- opcodes/v850-opc.c	23 Jul 2010 14:52:54 -0000	1.12
+++ opcodes/v850-opc.c	19 May 2011 11:05:37 -0000
@@ -1205,10 +1205,10 @@ const struct v850_opcode v850_opcodes[] 
 { "cmovf.s",	two (0x07e0, 0x0400),	two (0x07e0, 0x07f1),	{FFF, R1, R2, R3_NOTR0},		0, PROCESSOR_V850E2V3 },
 /* Default value for FFF is 0(not defined in spec).  */
 { "cmovf.s",	two (0x07e0, 0x0400),	two (0x07e0, 0x07ff),	{R1, R2, R3_NOTR0},			0, PROCESSOR_V850E2V3 },
-{ "cmpf.d",	two (0x07e0, 0x0430),	two (0x0fe1, 0x87f1),	{FLOAT_CCCC, R1_EVEN, R2_EVEN, FFF},	0, PROCESSOR_V850E2V3 },
-{ "cmpf.d",	two (0x07e0, 0x0430),	two (0x0fe1, 0x87ff),	{FLOAT_CCCC, R1_EVEN, R2_EVEN},		0, PROCESSOR_V850E2V3 },
-{ "cmpf.s",	two (0x07e0, 0x0420),	two (0x07e0, 0x87f1),	{FLOAT_CCCC, R1, R2, FFF},		0, PROCESSOR_V850E2V3 },
-{ "cmpf.s",	two (0x07e0, 0x0420),	two (0x07e0, 0x87ff),	{FLOAT_CCCC, R1, R2},			0, PROCESSOR_V850E2V3 },
+{ "cmpf.d",	two (0x07e0, 0x0430),	two (0x0fe1, 0x87f1),	{FLOAT_CCCC, R2_EVEN, R1_EVEN, FFF},	0, PROCESSOR_V850E2V3 },
+{ "cmpf.d",	two (0x07e0, 0x0430),	two (0x0fe1, 0x87ff),	{FLOAT_CCCC, R2_EVEN, R1_EVEN},		0, PROCESSOR_V850E2V3 },
+{ "cmpf.s",	two (0x07e0, 0x0420),	two (0x07e0, 0x87f1),	{FLOAT_CCCC, R2, R1, FFF},		0, PROCESSOR_V850E2V3 },
+{ "cmpf.s",	two (0x07e0, 0x0420),	two (0x07e0, 0x87ff),	{FLOAT_CCCC, R2, R1},			0, PROCESSOR_V850E2V3 },
 { "cvtf.dl",	two (0x07e4, 0x0454),	two (0x0fff, 0x0fff),	{R2_EVEN, R3_EVEN},			0, PROCESSOR_V850E2V3 },
 { "cvtf.ds",	two (0x07e3, 0x0452),	two (0x0fff, 0x07ff),	{R2_EVEN, R3},				0, PROCESSOR_V850E2V3 },
 { "cvtf.dul",	two (0x07f4, 0x0454),	two (0x0fff, 0x0fff),	{R2_EVEN, R3_EVEN},			0, PROCESSOR_V850E2V3 },


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