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Re: [PATCH, ARM] MSR/MRS assembly and disassembly tweaks
Hi Julian,
gas/
* config/tc-arm.c (parse_psr): Use selected_cpu not cpu_variant to
detect M-profile targets.
include/
* opcode/arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
Right - I have applied this patch together with some fixes of my own.
(Full patch attached). We now have zero unexpected failures in the GAS
testsuite for EABI, ELF and PE based ARM toolchains.
The problem with the SVC test was that removing ARM_EXT_OS from
ARM_AEXT_V7_ARM meant that -march=armv7 would select an architecture
that included v6m but which did not set ARM_EXT_OS. This is correct,
but the code in do_t_swi() did not allow for this and so triggered a
bogus error condition. I fixed this by extending the test in do_t_swi
to exclude all v7 and higher architectures.
One thing that I am not sure about is the correct name for V7M PSR
register 18. Is it BASEPRI_MASK or BASEPRI_MAX. Judging by the other
register names it is BASEPRI_MASK, but I could not find any
documentation to confirm this.
Cheers
Nick
gas/ChangeLog
2011-04-18 Julian Brown <julian@codesourcery.com>
Nick Clifton <nickc@redhat.com>
* config/tc-arm.c (parse_psr): Use selected_cpu not cpu_variant to
detect M-profile targets.
(do_t_swi): Exclude v7 and higher variants from arm_ext_os test.
(v7m_psrs): Fix typo: basepri_max should be basepri_mask.
gas/testsuite/ChangeLog
2011-04-18 Nick Clifton <nickc@redhat.com>
* gas/arm/arch7.s: Fix typo basepri_max should be basepri_mask.
* gas/arm/mrs-msr-thumb-v7e-m.s: Likewise.
* gas/arm/arch7.d: Update expected disassembly.
* gas/arm/attr-march-armv7.d: Remove Microcontroller tag.
* gas/arm/blx-bad.d: Only run for ELF based targets.
* gas/arm/mrs-msr-thumb-v6t2.d: Likewise.
* gas/arm/vldm-arm.d: Likewise.
* gas/arm/mrs-msr-thumb-v7-m.d: Likewise.
Remove qualifiers from PSR and IAPSR regsiter names.
* gas/arm/mrs-msr-thumb-v7e-m.d: Likewise.
* gas/arm/thumb2_bcond.d: Update expected disassembly to allow for
relaxing of branch insns.
* gas/arm/thumb32.d: Fix whitespace problems in disassembly.
opcodes/ChangeLog
2011-04-18 Nick Clifton <nickc@redhat.com>
* arm-dis.c (psr_name): Revert previous delta.
include/opcode/ChangeLog
2011-04-18 Julian Brown <julian@codesourcery.com>
* arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
Index: opcodes/arm-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/arm-dis.c,v
retrieving revision 1.141
diff -u -3 -p -r1.141 arm-dis.c
--- opcodes/arm-dis.c 12 Apr 2011 16:01:47 -0000 1.141
+++ opcodes/arm-dis.c 18 Apr 2011 13:11:50 -0000
@@ -3722,7 +3722,7 @@ psr_name (int regno)
case 9: return "PSP";
case 16: return "PRIMASK";
case 17: return "BASEPRI";
- case 18: return "BASEPRI_MAX";
+ case 18: return "BASEPRI_MASK";
case 19: return "FAULTMASK";
case 20: return "CONTROL";
default: return "<unknown>";
@@ -4192,15 +4192,6 @@ print_insn_thumb32 (bfd_vma pc, struct d
else
func (stream, "(UNDEF: %lu)", sysm);
}
- else if ((given & 0xff) <= 3)
- {
- func (stream, "%s_", psr_name (given & 0xff));
-
- if (given & 0x800)
- func (stream, "nzcvq");
- if (given & 0x400)
- func (stream, "g");
- }
else
{
func (stream, psr_name (given & 0xff));
Index: gas/config/tc-arm.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-arm.c,v
retrieving revision 1.480
diff -u -3 -p -r1.480 tc-arm.c
--- gas/config/tc-arm.c 12 Apr 2011 11:47:38 -0000 1.480
+++ gas/config/tc-arm.c 18 Apr 2011 13:11:52 -0000
@@ -5354,7 +5354,7 @@ parse_psr (char **str, bfd_boolean lhs)
const struct asm_psr *psr;
char *start;
bfd_boolean is_apsr = FALSE;
- bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m);
+ bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
/* CPSR's and SPSR's can now be lowercase. This is just a convenience
feature for ease of use and backwards compatibility. */
@@ -11760,7 +11760,9 @@ do_t_swi (void)
to ARM_EXT_V6M. */
if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m))
{
- if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os))
+ if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os)
+ /* This only applies to the v6m howver, not later architectures. */
+ && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7))
as_bad (_("SVC is not permitted on this architecture"));
ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os);
}
@@ -16632,7 +16634,8 @@ static const struct asm_psr v7m_psrs[] =
{"psp", 9 }, {"PSP", 9 },
{"primask", 16}, {"PRIMASK", 16},
{"basepri", 17}, {"BASEPRI", 17},
- {"basepri_max", 18}, {"BASEPRI_MAX", 18},
+ {"basepri_max", 18}, {"BASEPRI_MAX", 18}, /* Typo, preserved for backwards compatibility. */
+ {"basepri_mask",18}, {"BASEPRI_MASK", 18},
{"faultmask", 19}, {"FAULTMASK", 19},
{"control", 20}, {"CONTROL", 20}
};
Index: gas/testsuite/gas/arm/arch7.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/arch7.d,v
retrieving revision 1.8
diff -u -3 -p -r1.8 arch7.d
--- gas/testsuite/gas/arm/arch7.d 11 Apr 2011 18:49:05 -0000 1.8
+++ gas/testsuite/gas/arm/arch7.d 18 Apr 2011 13:11:52 -0000
@@ -57,13 +57,13 @@ Disassembly of section .text:
0+0c0 <[^>]*> f3ef 8009 mrs r0, PSP
0+0c4 <[^>]*> f3ef 8010 mrs r0, PRIMASK
0+0c8 <[^>]*> f3ef 8011 mrs r0, BASEPRI
-0+0cc <[^>]*> f3ef 8012 mrs r0, BASEPRI_MAX
+0+0cc <[^>]*> f3ef 8012 mrs r0, BASEPRI_MASK
0+0d0 <[^>]*> f3ef 8013 mrs r0, FAULTMASK
0+0d4 <[^>]*> f3ef 8014 mrs r0, CONTROL
0+0d8 <[^>]*> f380 8800 msr (CPSR_f|APSR_nzcvq), r0
-0+0dc <[^>]*> f380 8801 msr IAPSR_nzcvq, r0
-0+0e0 <[^>]*> f380 8802 msr EAPSR_nzcvq, r0
-0+0e4 <[^>]*> f380 8803 msr PSR_nzcvq, r0
+0+0dc <[^>]*> f380 8801 msr IAPSR, r0
+0+0e0 <[^>]*> f380 8802 msr EAPSR, r0
+0+0e4 <[^>]*> f380 8803 msr PSR, r0
0+0e8 <[^>]*> f380 8805 msr IPSR, r0
0+0ec <[^>]*> f380 8806 msr EPSR, r0
0+0f0 <[^>]*> f380 8807 msr IEPSR, r0
@@ -71,9 +71,10 @@ Disassembly of section .text:
0+0f8 <[^>]*> f380 8809 msr PSP, r0
0+0fc <[^>]*> f380 8810 msr PRIMASK, r0
0+100 <[^>]*> f380 8811 msr BASEPRI, r0
-0+104 <[^>]*> f380 8812 msr BASEPRI_MAX, r0
+0+104 <[^>]*> f380 8812 msr BASEPRI_MASK, r0
0+108 <[^>]*> f380 8813 msr FAULTMASK, r0
0+10c <[^>]*> f380 8814 msr CONTROL, r0
0+110 <[^>]*> f3ef 8003 mrs r0, PSR
-0+114 <[^>]*> f380 8803 msr PSR_nzcvq, r0
+0+114 <[^>]*> f380 8803 msr PSR, r0
0+118 <[^>]*> df00 svc 0
+#...
Index: gas/testsuite/gas/arm/arch7.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/arch7.s,v
retrieving revision 1.4
diff -u -3 -p -r1.4 arch7.s
--- gas/testsuite/gas/arm/arch7.s 11 Apr 2011 18:49:05 -0000 1.4
+++ gas/testsuite/gas/arm/arch7.s 18 Apr 2011 13:11:52 -0000
@@ -60,7 +60,7 @@ label2:
mrs r0, psp
mrs r0, primask
mrs r0, basepri
- mrs r0, basepri_max
+ mrs r0, basepri_mask
mrs r0, faultmask
mrs r0, control
msr apsr_nzcvq, r0
@@ -74,7 +74,7 @@ label2:
msr psp, r0
msr primask, r0
msr basepri, r0
- msr basepri_max, r0
+ msr BASEPRI_MASK, r0
msr faultmask, r0
msr control, r0
mrs r0, xpsr
Index: gas/testsuite/gas/arm/attr-march-armv7.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/attr-march-armv7.d,v
retrieving revision 1.4
diff -u -3 -p -r1.4 attr-march-armv7.d
--- gas/testsuite/gas/arm/attr-march-armv7.d 11 Apr 2011 15:23:08 -0000 1.4
+++ gas/testsuite/gas/arm/attr-march-armv7.d 18 Apr 2011 13:11:52 -0000
@@ -9,6 +9,5 @@ Attribute Section: aeabi
File Attributes
Tag_CPU_name: "7"
Tag_CPU_arch: v7
- Tag_CPU_arch_profile: Microcontroller
Tag_THUMB_ISA_use: Thumb-2
Tag_DIV_use: Not allowed
Index: gas/testsuite/gas/arm/blx-bad.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/blx-bad.d,v
retrieving revision 1.1
diff -u -3 -p -r1.1 blx-bad.d
--- gas/testsuite/gas/arm/blx-bad.d 6 Jan 2011 14:30:42 -0000 1.1
+++ gas/testsuite/gas/arm/blx-bad.d 18 Apr 2011 13:11:52 -0000
@@ -1,5 +1,7 @@
#objdump: -drw --show-raw-insn
#name: BLX encoding
+# This test is only valid on ELF based ports.
+#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
.*: file format .*arm.*
Index: gas/testsuite/gas/arm/mrs-msr-thumb-v6t2.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/mrs-msr-thumb-v6t2.d,v
retrieving revision 1.1
diff -u -3 -p -r1.1 mrs-msr-thumb-v6t2.d
--- gas/testsuite/gas/arm/mrs-msr-thumb-v6t2.d 11 Apr 2011 18:49:05 -0000 1.1
+++ gas/testsuite/gas/arm/mrs-msr-thumb-v6t2.d 18 Apr 2011 13:11:52 -0000
@@ -1,5 +1,7 @@
#objdump: -dr --prefix-addresses --show-raw-insn
#name: MRS/MSR test, architecture v6t2, Thumb mode
+# This test is only valid on ELF based ports.
+#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
.*: file format .*
Index: gas/testsuite/gas/arm/mrs-msr-thumb-v7-m.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/mrs-msr-thumb-v7-m.d,v
retrieving revision 1.1
diff -u -3 -p -r1.1 mrs-msr-thumb-v7-m.d
--- gas/testsuite/gas/arm/mrs-msr-thumb-v7-m.d 11 Apr 2011 18:49:05 -0000 1.1
+++ gas/testsuite/gas/arm/mrs-msr-thumb-v7-m.d 18 Apr 2011 13:11:52 -0000
@@ -1,6 +1,7 @@
#objdump: -dr --prefix-addresses --show-raw-insn
#name: MRS/MSR test, architecture v7-M, Thumb mode
-
+# This test is only valid on ELF based ports.
+#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
.*: file format .*
@@ -9,7 +10,7 @@ Disassembly of section .text:
0+00 <[^>]*> f3ef 8400 mrs r4, CPSR
0+04 <[^>]*> f3ef 8502 mrs r5, EAPSR
0+08 <[^>]*> f3ef 8610 mrs r6, PRIMASK
-0+0c <[^>]*> f383 8803 msr PSR_nzcvq, r3
+0+0c <[^>]*> f383 8803 msr PSR, r3
0+10 <[^>]*> f384 8800 msr CPSR_f, r4
-0+14 <[^>]*> f385 8801 msr IAPSR_nzcvq, r5
+0+14 <[^>]*> f385 8801 msr IAPSR, r5
0+18 <[^>]*> f386 8810 msr PRIMASK, r6
Index: gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.d,v
retrieving revision 1.1
diff -u -3 -p -r1.1 mrs-msr-thumb-v7e-m.d
--- gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.d 11 Apr 2011 18:49:05 -0000 1.1
+++ gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.d 18 Apr 2011 13:11:52 -0000
@@ -1,5 +1,7 @@
#objdump: -dr --prefix-addresses --show-raw-insn
#name: MRS/MSR test, architecture v7e-M, Thumb mode
+# This test is only valid on ELF based ports.
+#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
.*: file format .*
@@ -9,5 +11,5 @@ Disassembly of section .text:
0+04 <[^>]*> f3ef 8502 mrs r5, EAPSR
0+08 <[^>]*> f3ef 8610 mrs r6, PRIMASK
0+0c <[^>]*> f384 8c00 msr CPSR_fs, r4
-0+10 <[^>]*> f385 8401 msr IAPSR_g, r5
-0+14 <[^>]*> f386 8812 msr BASEPRI_MAX, r6
+0+10 <[^>]*> f385 8401 msr IAPSR, r5
+0+14 <[^>]*> f386 8812 msr BASEPRI_MASK, r6
Index: gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.s
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.s,v
retrieving revision 1.1
diff -u -3 -p -r1.1 mrs-msr-thumb-v7e-m.s
--- gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.s 11 Apr 2011 18:49:05 -0000 1.1
+++ gas/testsuite/gas/arm/mrs-msr-thumb-v7e-m.s 18 Apr 2011 13:11:52 -0000
@@ -7,4 +7,4 @@
mrs r6, primask
msr apsr_nzcvqg, r4
msr iapsr_g, r5
- msr basepri_max, r6
+ msr basepri_mask, r6
Index: gas/testsuite/gas/arm/thumb2_bcond.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/thumb2_bcond.d,v
retrieving revision 1.7
diff -u -3 -p -r1.7 thumb2_bcond.d
--- gas/testsuite/gas/arm/thumb2_bcond.d 12 Apr 2011 15:44:36 -0000 1.7
+++ gas/testsuite/gas/arm/thumb2_bcond.d 18 Apr 2011 13:11:52 -0000
@@ -4,24 +4,24 @@
.*: +file format .*arm.*
Disassembly of section .text:
-0+000 <[^>]+> bf18 it ne
-0+002 <[^>]+> f7ff bffd bne.w 0+0 <[^>]+>
-0+006 <[^>]+> bf38 it cc
-0+008 <[^>]+> f7ff bffa bcc.w 0+0 <[^>]+>
-0+00c <[^>]+> bf28 it cs
-0+00e <[^>]+> f7ff fff7 blcs 0+0 <[^>]+>
-0+012 <[^>]+> bfb8 it lt
-0+014 <[^>]+> 47a8 blxlt r5
-0+016 <[^>]+> bf08 it eq
-0+018 <[^>]+> 4740 bxeq r8
-0+01a <[^>]+> bfc8 it gt
-0+01c <[^>]+> e8d4 f001 tbbgt \[r4, r1\]
-0+020 <[^>]+> bfb8 it lt
-0+022 <[^>]+> df00 svclt 0
-0+024 <[^>]+> bf08 it eq
-0+026 <[^>]+> f8d0 f000 ldreq.w pc, \[r0\]
-0+02a <[^>]+> bfdc itt le
-0+02c <[^>]+> be00 bkpt 0x0000
-0+02e <[^>]+> bf00 nople
-0+030 <[^>]+> bf00 nop
+0+000 <[^>]+> bf18[ ]+it ne
+0+002 <[^>]+> [0-9a-f ]+[ ]+bne.[nw] 0+0 <[^>]+>
+0+00. <[^>]+> bf38[ ]+it cc
+0+00. <[^>]+> f7ff bff[ab][ ]+bcc.w 0+0 <[^>]+>
+0+00. <[^>]+> bf28[ ]+it cs
+0+0.. <[^>]+> f7ff fff[78][ ]+blcs 0+0 <[^>]+>
+0+0.. <[^>]+> bfb8[ ]+it lt
+0+0.. <[^>]+> 47a8[ ]+blxlt r5
+0+0.. <[^>]+> bf08[ ]+it eq
+0+0.. <[^>]+> 4740[ ]+bxeq r8
+0+0.. <[^>]+> bfc8[ ]+it gt
+0+0.. <[^>]+> e8d4 f001[ ]+tbbgt \[r4, r1\]
+0+0.. <[^>]+> bfb8[ ]+it lt
+0+0.. <[^>]+> df00[ ]+svclt 0
+0+0.. <[^>]+> bf08[ ]+it eq
+0+0.. <[^>]+> f8d0 f000[ ]+ldreq.w pc, \[r0\]
+0+0.. <[^>]+> bfdc[ ]+itt le
+0+0.. <[^>]+> be00[ ]+bkpt 0x0000
+0+0.. <[^>]+> bf00[ ]+nople
+0+0.. <[^>]+> bf00[ ]+nop
#...
Index: gas/testsuite/gas/arm/thumb32.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/thumb32.d,v
retrieving revision 1.41
diff -u -3 -p -r1.41 thumb32.d
--- gas/testsuite/gas/arm/thumb32.d 12 Apr 2011 16:01:48 -0000 1.41
+++ gas/testsuite/gas/arm/thumb32.d 18 Apr 2011 13:11:52 -0000
@@ -535,11 +535,11 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> e9d5 2300 ldrd r2, r3, \[r5\]
0[0-9a-f]+ <[^>]+> e9d5 230c ldrd r2, r3, \[r5, #48\].*
0[0-9a-f]+ <[^>]+> e955 230c ldrd r2, r3, \[r5, #-48\].*
-0[0-9a-f]+ <[^>]+> e95f 4505 ldrd r4, r5, \[pc, #-16\] ; 0+5f0 <^>]+>
+0[0-9a-f]+ <[^>]+> e95f 4504 ldrd r4, r5, \[pc, #-16\] ; 000005f0 <here>
0[0-9a-f]+ <[^>]+> e9c5 2300 strd r2, r3, \[r5\]
0[0-9a-f]+ <[^>]+> e9c5 230c strd r2, r3, \[r5, #48\].*
0[0-9a-f]+ <[^>]+> e945 230c strd r2, r3, \[r5, #-48\].*
-0[0-9a-f]+ <[^>]+> e94f 2308 strd r2, r3, \[pc, #-32\] ; 0+5f0 <^>]+>
+0[0-9a-f]+ <[^>]+> e94f 2308 strd r2, r3, \[pc, #-32\] ; 0+5f0 <here>
0[0-9a-f]+ <[^>]+> f815 1e00 ldrbt r1, \[r5\]
0[0-9a-f]+ <[^>]+> f815 1e30 ldrbt r1, \[r5, #48\].*
0[0-9a-f]+ <[^>]+> f915 1e00 ldrsbt r1, \[r5\]
@@ -1065,3 +1065,4 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> fa62 f103 ror.w r1, r2, r3
0[0-9a-f]+ <[^>]+> fa61 f103 ror.w r1, r1, r3
0[0-9a-f]+ <[^>]+> bf00 nop
+0[0-9a-f]+ <[^>]+> bf00 nop
Index: gas/testsuite/gas/arm/vldm-arm.d
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/arm/vldm-arm.d,v
retrieving revision 1.1
diff -u -3 -p -r1.1 vldm-arm.d
--- gas/testsuite/gas/arm/vldm-arm.d 9 Jun 2010 15:11:51 -0000 1.1
+++ gas/testsuite/gas/arm/vldm-arm.d 18 Apr 2011 13:11:52 -0000
@@ -2,6 +2,8 @@
# as: -mfpu=vfp3
# source: vldm.s
# objdump: -dr --prefix-addresses --show-raw-insn
+# This test is only valid on ELF based ports.
+#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
.*: +file format .*arm.*
Index: include/opcode/arm.h
===================================================================
RCS file: /cvs/src/src/include/opcode/arm.h,v
retrieving revision 1.25
diff -u -3 -p -r1.25 arm.h
--- include/opcode/arm.h 11 Apr 2011 15:23:09 -0000 1.25
+++ include/opcode/arm.h 18 Apr 2011 13:11:52 -0000
@@ -109,8 +109,7 @@
#define ARM_AEXT_V6KT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K)
#define ARM_AEXT_V6ZT2 (ARM_AEXT_V6T2 | ARM_EXT_SEC)
#define ARM_AEXT_V6ZKT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_SEC)
-#define ARM_AEXT_V7_ARM (ARM_AEXT_V6KT2 | ARM_EXT_V7 | ARM_EXT_BARRIER \
- | ARM_EXT_OS)
+#define ARM_AEXT_V7_ARM (ARM_AEXT_V6KT2 | ARM_EXT_V7 | ARM_EXT_BARRIER)
#define ARM_AEXT_V7A (ARM_AEXT_V7_ARM | ARM_EXT_V7A)
#define ARM_AEXT_V7R (ARM_AEXT_V7_ARM | ARM_EXT_V7R | ARM_EXT_DIV)
#define ARM_AEXT_NOTM \